timing in digital circuits

8/11/2019 Timing in digital circuits

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Jon Turner

Setup and hold time constraints

Input timing constraintsClock period analysisMetastability and synchronizer reliability

Timing Issues inDigital Circuits


2/18

Edge-Triggered D Flip FlopD lip lop stores !alue at D input"hen clock risesMost "idely used storage element

or se#uential circuits

Propagation time is time rom risingclock to output changeI input changes "hen clock rises$ne" !alue is uncertain

output may oscillate or may remain atintermediate !oltage % metastability)

D Q

Q >C

& Timing rules to a!oid metastability

' D input must be stable or setup time be ore rising clock edge' must remain stable or hold time ollo"ing rising clock edge

CDQ

setup hold

min, max propagation delay


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4/18

Clock 0eriod .nalysis rom Synthesis=======================================================================Timing constraint: Default period analysis for Clock 'clk' Clock period: 4.227ns (frequency: 2 !."!#$%& Total num er of pat)s * destination ports: 4" * "+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++Delay: 4.227ns (,e-els of ,ogic = ource: state/00d1 (00 Destination: cnt/2 (00 ource Clock: clk rising Destination Clock: clk rising

Data at): state/00d1 to cnt/2 3ate et Cell:in+5out fanout Delay Delay ,ogical ame ( et ame ++++++++++++++++++++++++++++++++++++++++ ++++++++++++ 0D6:C+5 8 #.!2! 1.12" state/00d1 (state/00d1 ,9T2: 1+5; 1 #.478 #.74# /mu# ( 12 ,9T4/,: 2+5,; 1 #.478 #.12 /mu# ( 118 ,9T4: +5; 1 #.478 #.### /mu


5/18

Implications o 3old Time Constraints

D Q

Q >CD Q

Q >Cclock source

combinationalcircuit path x

y

To a!oid hold time !iolations$ re#uirehold time 4 % min FF prop+ delay,

%min comb+ circuit delay, 5 %ma* clock ske",

C.D tools can check all FF-to-FF paths to !eri yIn F60.s$ it is o ten the case thathold time 7 %min FF prop+ delay, 5 %ma* clock ske",

so$ hold time !iolations cannot occur

clk

y

x

hold time

ff delay

cc delay


6/18

Input Timing

Setup and hold times constrain "hen inputs to acircuit can change

stable period starts at clock 5 %setup ma* delay, and lasts until clock hold 5 %min delay,

Common simpli ication is to hold input stable romclock 5 %setup ma* delay, until clock

D Q

>C

D Q

>Cclock

max delay path

x y

mindelay path #

clk

y,# stablemax delay

x stable min delay

set

up hold


7/18

Input Delay .nalysis rom Synthesis=========================================================================Timing constraint: Default ;00 BT B0;6B for Clock 'clk' Total num er of pat)s * destination ports: 17 * 12+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++;ffset: 4. "!ns (,e-els of ,ogic = 4 ource: d n ( D Destination: cnt/2 (00 Destination Clock: clk rising

Data at): d n to cnt/2 3ate et Cell:in+5out fanout Delay Delay ,ogical ame ( et ame ++++++++++++++++++++++++++++++++++++++++ ++++++++++++ 90: +5; 7 #.71" 1.2#1 d n/ 90 (d n/ 90 ,9T4: #+5; 1 #.478 #.7#4 /mu


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;e!ie" % ou may assume that the net delays don t change+,

(+ Consider a circuit in "hich there is a path rom an input x to a liplop that has a ma*imum possible delay o 9 ns$ and there is also a

path rom x to another lip lop "ith a minimum delay o ( ns+ Ithe setup and hold times are 2 ns and = ns respecti!ely and theclock input rises at time t $ is it ok or x to change at time t 5 > ?hat

about t 5=> ?hat about t > ?hat about t 5= >


9/18

Timing .nalysis 0rocedure=+Check or internal hold time !iolations or e!ery -to- path$ check

%minimum prop+ delay, % minimum comb+ circuit delay,) %hold time, %clock ske",

i* !iolations by adding delay no !iolations possible i hold-time7%min- -prop-delay,5ske"

2+Determine minimum clock period ind -to- path "ith largest !alue o

%maximum prop+ delay, % maximum comb+ circuit delay, %setup time, %clock ske",

(+ Input timing analysis each input must be stable rom

%clockGedge, %%maximum input-to- delay, %setup time,,to %%clockGedge, %hold time,, %minimum input-to- delay,

/+ Timing analysis or synchronous outputs synchronous outputs ha!e potential to change any time rom

%clockGedge, %minimum

clock-to-output delay,to %clockGedge, % maximum clock-to-output delay,

omit ske" or paths romoutput to input o same

omit ske" or paths rom

output to input o same


10/18

Timing .nalysis o Se#uential Comparator

& Minimum clock period - 2 8 = 2 = H == ns or M3zInput timing re#uirements' % and & must be stable rom % clock'edge 5 2, 5 / = until

%clock'edge =, 5 ( +2 $ so rom -8 ns to +2

utput timing - outputs can change + to 2 ns a ter clock

& Timing parameters' gate delayJ +2 to = ns' setup timeJ 2 ns' hold timeJ = ns' prop+ delayJ + -2 ns

' clock ske"J = nsInternal hold time !iolation>' yes - + /%+2 , 7 = =' add in!erter pair to eedback

paths rom s


11/18

Combining Circuits

?hen combining t"o components$ check setupconstraints manually

clock period ) %ma* output delay, %ma* input delay, %ma* inter-connect delay, ske"

Kote$ ske" much larger across di erentcomponents than "ithin a single component3old time !iolations unlikely across components

inter-chip delays much larger than %hold time, ske"

Circuit =

Circuit 2

clk

interconnect

delay D Q

>C

D Q

>C

ma* input

delay

ma* output

delay


12/18

Dealing "ith Timing Failures

To i* hold time errors$ add delay rarely issue in F06.s$ but can be in .SIC designs

To correct setup time ailures i you can t increase clock period$ must reduce delay ind long delay paths and modi y circuit to reduce adLust synthesis@implementation properties

ocus on speed optimization$ increase e ort le!el

study synthesis report to identi y "orst-case paths re"rite 3DA to produce aster circuit e+g+ replace ripple-carry circuits "ith carry lookahead i need be %and easible,$ insert pipeline registers to di!ide

long combinational paths into smaller parts


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MetastabilityMost digital systems ha!e asynchronous inputs

keyboard input on a computer$ sensor on a tra ic light controller$ card insertion on an .TM$ etc+

.synchronous inputs change at unpredictable times so$ can change during clock transition$ causing

metastability utput o a metastable lip lop can oscillate or remain

at intermediate !alue leads to unpredictable beha!ior in other lip lops metastability usually ends #uickly$ but no definite time

limit so$ circuit ailures due to metastability are una(oidable ho"e!er$ systems can be designed to make ailures rare


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Synchronizersynchroni#ers are used to isolate metastable signals until

they are Nprobably sa eO

D Q

>C

D Q

>Cclk

asynchronousinput

potentially metastable

signal *probablysafe+ signal

& I the clock period is long enough$ ailure probability is smalland e*pected time bet"een ailures is large

MTPF H Mean Time Pet"een Failures % T @T , eT @"here T is the clock period$ is the a!erage time bet"eenasynchronous input changes$ and T are parameters o the

lip lop being usedI T H ns$ = ms$ H = ns$ T H = ns$ MTPF : trillionyears$ i T H = ns$ MTPF becomes 22 secondsQ


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MTPF Chart

=+E-C

=+E-C8

=+E-C9

=+E-C:

=+E-CD

=+E-=C

=+E-==

=+E-=2

=C = 2C 2 (C ( /C / C 8C

T@

M T P F % s e c o n

d s ,

H= s

= year

= ns= ms = s

HT C HT

T@T

= years


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E*ercises

=+Consider the generic state machinesho"n belo" "ith the indicatedpropagation delays+ I the setup time orthe lip lops is =+ ns and the ma*imumclock ske" is + ns$ "hat is the smallest

clock period or "hich the circuit isguaranteed to "ork correctly>

2+ For the state machine sho"n belo"$assume that the lip lop setup time is 2ns$ the hold time is + ns and the lip lop

propagation delay is bet"een = and ( ns+.lso$ that the clock ske" is +( ns+

Is this circuit subLect to internal holdtime !iolations> Rusti y your ans"er+ ?hatis the smallest clock period or "hich thecircuit is not subLect to setup time!iolations> Pe sure to take into accountany modi ications rom the pre!ious step+?hat is the latest time relati!e to theclock$ "hen it is sa e or input & tochange> ?hat is the latest time a ter theclock "hen output - can be changing>


17/18

(+Consider a synchronizer used tosynchronize an asynchronous inputsignal+ Aet the a!erage time bet"een

changes o the input signal be microseconds+ Aet the lip lopparameters be T H ( ns and H 2 ns+ Ithe clock period or the synchronizer is= ns$ "hat is the mean time bet"eensynchronizer ailures> ?hat is thesmallest clock period %to the nearest ns,

or "hich the mean time bet"een ailuresis = years> ?hat is the smallest clockperiod or "hich the mean time bet"een

ailures is = $ years>


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Solutions

=+ The minimum clock period is=+ ( =+ + H8+ ns+2+ There are no hold time !iolationsbecause the minimum lip loppropagation delay is larger than the hold

time plus the ske"+ The ma*imum delay or the ne*t statelogic is ns+ This gi!es a minimum clockperiod o ( 2 +(H= +( ns+Input & has a ma*imum delay path o ns$ so it must be stable by ( 2H nsbe ore the clock rises+

The latest time a ter the clock "henoutput - can be change is ( /H9 ns+

(+ H *= -8$ T H (*= - and H

2*= - $ so or T H= *= - $ MTPF H

=89*=-8

e H 2/$9( *=-8

seconds orabout 2 milliseconds+ Py trial anderror$ one inds that or T H ( ns theMTPF is about +2 years and or T H /ns$ it is about = years$ so "e need atarget clock period o about / ns toget a = year MTPF+ .lso$ by trial anderror$ one inds that or T H88 ns theMTPF is about 9$8 years and orT H89 ns$ it is about =2$: years$ so"e need a target clock period oabout 89 ns to get a = $ yearMTPF+ So$ adding =( ns has impro!edthe reliability by a actor o =$ +

timing in digital circuits

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