ECE 683

Timing Characterization Using Cadence

OSU DIGITAL CELL LIBRARY DOCUMENTATION Matt Silverman 12/5/2005

1

TABLE OF CONTENTS INTRODUCTION ........................................................................................................................................ 3

TRANSIENT ANALYSIS WITH CADENCE ------------------------------------------------------------------- 3 PURPOSE OF THIS DOCUMENT............................................................................................................ 3

PURPOSE ------------------------------------------------------------------------------------------------------------- 3 SCOPE----------------------------------------------------------------------------------------------------------------- 3 FORMAT-------------------------------------------------------------------------------------------------------------- 4

GENERAL TIMING EXTRACTION WITH CADENCE....................................................................... 5 DESCRIPTION------------------------------------------------------------------------------------------------------- 5 CADENCE FLOW --------------------------------------------------------------------------------------------------- 5

CADENCE SETUP ...................................................................................................................................... 6 DESCRIPTION------------------------------------------------------------------------------------------------------- 6 SETTING UP CADENCE------------------------------------------------------------------------------------------- 6

CREATING TESTBENCHES .................................................................................................................... 7 DESCRIPTION------------------------------------------------------------------------------------------------------- 7 THE TESTBENCH--------------------------------------------------------------------------------------------------- 7 CREATING THE TESTBENCH----------------------------------------------------------------------------------- 8 STIMULUS ----------------------------------------------------------------------------------------------------------- 9 STIMULI CONDITIONING---------------------------------------------------------------------------------------10 LOADING THE OUTPUT OF THE TESTED CELL ----------------------------------------------------------10

SIMULATING WITH ANALOG ENVIRONMENT.............................................................................. 11 DESCRIPTION------------------------------------------------------------------------------------------------------11 SETTING UP ANALOG ENVIRONMENT FILES ------------------------------------------------------------11 SETTING UP THE SIMULATION-------------------------------------------------------------------------------12 SIMULATION, PLOTTING AND TIMING EXTRACTION-------------------------------------------------14

POST-LAYOUT SIMULATION WITH ANALOG ENVIRONMENT................................................ 15 DESCRIPTION------------------------------------------------------------------------------------------------------15 CREATING AN EXTRACTED CELLVIEW -------------------------------------------------------------------15 SIMULATING EXTRACTED LAYOUT IN ANALOG ENVIRONMENT --------------------------------17

CREATING TESTBENCHES WITH VERILOG AMS CELLVIEWS ............................................... 18 DESCRIPTION------------------------------------------------------------------------------------------------------18 CREATING VERILOG AMS CELLVIEWS--------------------------------------------------------------------18 CREATING THE STIMULUS MODULE-----------------------------------------------------------------------20 CREATING THE RESULTS EXTRACTOR--------------------------------------------------------------------24

SIMULATION WITH THE HIERARCHY EDITOR............................................................................ 26 DESCRIPTION------------------------------------------------------------------------------------------------------26 HIERARCHY EDITOR SETUP-----------------------------------------------------------------------------------27 RUNNING SIMULATIONS AND EXTRACTING TIMING INFORMATION ---------------------------29 NOTE ON SIMULATING THE EXTRACTED VIEW WITH HIERARCHY EDITOR ------------------32

COMPARISON OF RESULTS................................................................................................................. 33 DESCRIPTION------------------------------------------------------------------------------------------------------33 RESULTS ------------------------------------------------------------------------------------------------------------33

REMAINING LIBRARY WORK ............................................................................................................ 35 DESCRIPTION------------------------------------------------------------------------------------------------------35

2

CONCLUSION........................................................................................................................................... 35 APPENDIX A ............................................................................................................................................. 36

STIMULUS MODULE LOGIC TABLE -------------------------------------------------------------------------36 STIMULUS MODULE VERILOG AMS CODE ---------------------------------------------------------------37 RESULTS EXTRACTOR VERILOG AMS CODE ------------------------------------------------------------40

REFERENCES ........................................................................................................................................... 49

3

INTRODUCTION

TRANSIENT ANALYSIS WITH CADENCE With Cadence tools, one bottleneck in extracting timing information for cell libraries is the use of graphical interfaces to find input/output delays. For example, to find the delay time between the input and output of an inverter using Cadence, one must run a transient analysis using Analog Environment and then manually move cursors to obtain a reading. Furthermore, for cells with more than one input, the schematic must be altered and resimulated to get the information for delays of each input. This process can be very slow. By simulating using modules of Verilog AMS code and, thereby removing the graphical interface, one can make the entire process much faster. This is the focus of this paper. The first part of this paper will outline timing extraction using conventional graphical methods. The timing extraction was done for the AMI05 Digital Library. The first part will cover transient analysis of schematics and extracted layout. The second part of this paper will discuss attempts to automate the timing extraction process using Verilog AMS. This will include writing a stimulus module and a results extraction module.

PURPOSE OF THIS DOCUMENT

PURPOSE The purpose of this document is to describe two different ways of performing transient analysis on cell libraries using Cadence tools. I will try to provide a step-by-step procedure for simulation using Analog Environment and the Hierarchy Editor. Additionally, I will discuss attempts to transition from graphically based simulation and timing extraction to text based using Verilog AMS and scripting.

SCOPE The scope of this document will include a detailed description of transient analysis that was done on the AMI05 Digital Cell Library using Cadence Analog Environment and Hierarchy Editor. The transient analysis that will be discussed will focus on the extraction of timing information for cells in the library.

4

FORMAT This document is presented in a way that hopes to ease information transfer. Therefore, it will be formatted in a tutorial form so that readers will be able to find relevant information easily.

5

GENERAL TIMING EXTRACTION WITH CADENCE

DESCRIPTION This section will discuss the process of creating a testbench in order to run transient analysis on a cell library using Cadence. The process for extracting timing information by using Cadence is useful to understand the timing characteristics of gates, circuits, and systems. The process consists of opening a schematic editor and creating schematic testbench that consists of a stimulus, a tested cell and a load. Then, after the testbench has been created and checked for errors, there are multiple ways to simulate the schematic using Cadence tools. Two ways of running simulation are to use Analog Environment and the Hierarchy Editor. Both these methods will be discussed later. Similarly, timing information can be extracted from simulation in two different ways, graphically and textually. In the former, the transient analysis of the inputs and outputs of the tested cell in the testbench can be plotted and the delay times seen on the plot. The time delay between the transition in the input and that in the output can be manually, visually determined. In the later, the information can be extracted using a results extraction Verilog AMS module and displayed or logged. One important theme of this document is that textual extraction is superior from a time-to-market perspective because it is so much faster once the mechanism has been established. The following sections discuss the timing extraction by both these methods for the AMI05 Digital Library.

CADENCE FLOW In simulation using Analog Environment, the process consists of several steps. First a link to the cell library must be made. Then a testbench must be created using the schematic editor. Once the testbench is setup, a cell from the library can be instantiated into the testbench. Then, Analog Environment is opened, set up and a simulation is run. The simulation results are plotted, and the timing information is taking from the plot.

6

Simulation flow Using Analog Environment

In using the Hierarchy Editor, the flow is essentially the same except you invoke the Hierarchy Editor instead of Analog Environment when running simulation. The following sections will detail this flow—first, for graphically based extraction using Analog Environment and then for textually based extraction using the Hierarchy Editor.

CADENCE SETUP

DESCRIPTION The purpose of this section is to describe the setup procedures to create a testbench for analysis of the AMI05 Digital Library. This assumes that you have already setup Cadence and also NCSU Libraries. If you have not done this setup, go to www.ece.osu.edu/cadence for instructions.

SETTING UP CADENCE To setup Cadence properly for the creation of a schematic testbench, links must be made to the appropriate libraries. When it comes time to simulate the schematic, simulation directories and simulation models must be selected. This section outlines this process. First, a link must be made to the AMI05 Digital Library. The user should have the following libraries defined in the cds.lib located in the ~/cadence/NCSU directory.

7

INCLUDE $CDS_SITE/cdssetup/cds.lib DEFINE digital_lib_ami05 /rcc4/student/parryj/cadence/digital_lib_ami05/digital_lib_ami05 DEFINE analogLib $CDSHOME/tools/dfII/etc/cdslib/artist/analogLib SOFTINCLUDE $AMSHOME/tools/inca/files/cds.lib DEFINE basic $CDSHOME/tools/dfII/etc/cdslib/basic

Note: Only the “DEFINE digital_lib_ami05…” is necessary to run simulations using Analog Environment. The remaining will be needed later for simulations using the Hierarchy Editor. However, I include them now anyway. There are further steps that must be taken to make the Hierarchy Editor work properly, but those will be discussed later. Furthermore, there will be more steps needed to setup Analog Environment once a testbench is ready for simulation.

CREATING TESTBENCHES

DESCRIPTION The purpose of this section is to outline the steps to create a schematic testbench for simulation using Analog Environment. It will outline the different components to a testbench as well as their purpose.

THE TESTBENCH When attempting to simulate a cell, a testbench must be set up. This is done with the Cadence Schematic Editor. The testbench is merely a schematic that instantiates the component that is to be tested and contains a stimulus for the cell and a load. This appears as a symbol in the schematic. A testbench can be relatively simple and include only a voltage source for the input of the cell, a voltage source for vdd, gnd, a load, and the particular cell symbol that is to be analyzed. Below, the figure displays the testbench that was used to analyze cells in the AMI05 Digital cell library.

8

Example Testbench for AMI05 Digital Library

CREATING THE TESTBENCH To open the Schematic Editor, create a library or use an existing one through the library manager. Create a cell with a schematic cellview type. To do this, one can just type a new library name in the library. Create a new cell by typing a name in the field. You will be prompted to select the view type. Select schematic.

Selected Library

Selected Cell

View Schematic will appearonce schematic view type is selected

Once the schematic view is created for the newly created cell, the schematic editor will open. If it doesn’t open, double click on “schematic” listed in the “view”

9

field to open. Once the schematic editor is open, you can instantiate cell symbols to create the testbench.

STIMULUS The stimulus component can be as simple as the one in the figure above or a symbol of another cell that is instantiated into the testbench schematic. For repeated testing of cells with varying numbers of inputs, creating a stimulus with multiple stimuli to handle all cases may be preferable. In other words, just have enough voltage sources on standby to handle as many inputs as your biggest cell has—biggest meaning most number of inputs. One way to clean up the schematic is to create a separate cell that contains these voltage sources, and create a symbol from that schematic to be instantiated into the testbench. Below is an example of a symbol of a symbol created for use in testbench stimulus.

The schematic contains five voltage pulses that were instantiated from the NCSU Analog Library. The pulses are good to use in testbenches because you can control the widths and periods of each pulse separately from the Analog Environment without having to modify the schematic. This is done by setting the parameters in the schematic as variables. This is useful when analyzing a wide range of cells with different stimulus needs. By selecting a voltage source in the schematic and pressing “q”, you can edit that objects properties. The figure below illustrates that process. In the object properties editor, you can choose to put a variable name in any parameter field instead of a numeric value. Once in Analog Environment, you can give the variables values and simulate off them. In the figure below, I give the pulse period the variable name “per3” and the pulse width the variable name “pw3”. Once the schematic and symbol are created, they can be instantiated into the testbench. Simply press “i” when you have the schematic editor opened for the testbench. Then navigate with the component browser to the library where the stimulus symbol is located. Select it and place it in the schematic.

10

STIMULI CONDITIONING Notice that in the figure of the testbench on page 8, the tested cell is not merely stimulated with voltage pulses. Instead, it is run through inverters. This is necessary to create a more realistic stimulus. Using the voltage pulses directly would lead to shorter rise and fall times for the tested cell simply because the input signal would rise with an infinite slope.

LOADING THE OUTPUT OF THE TESTED CELL When testing a cell for timing, it is important to load the tested cell with another cell to create a more realistic timing situation. It is unlikely that one will find an unload cell within any circuit. Furthermore, an unloaded cell will have much faster rise and fall times than a loaded cell because it has no load capacitance. The rise and fall times are inversely proportional to the gate and load capacitances. In the timing simulations done on the AMI05 Digital Library, all the

11

tested cells were loaded with one of the inputs to a nand2x1 from the same library. This was used as the standard load in all simulations.

SIMULATING WITH ANALOG ENVIRONMENT

DESCRIPTION This section will detail running simulations in Analog Environment. The focus will be on setting Analog Environment to run simulation, carrying out transient analysis and extracting timing information.

SETTING UP ANALOG ENVIRONMENT FILES After creating a testbench with the schematic editor that is free of errors, the schematic can be simulated using Analog Environment. In the schematic editor, select Tools Analog Environment. The window displayed below will appear.

Next you must choose a simulation directory. Select Setup Simulator/Directory/Host. There you will need to type in the location of the simulation directory. Type ~/cadence/simulation in the field labeled project directory. This is shown below.

12

Next the model library must be setup. Select Setup Model Libraries… Select “Browse” to find the model library named “allModels.scs” found in /opt/local/cadence/design_kits/NCSU/current/local//models/spectre/nom/allModels.scs. After that model library has been selected, select “Add”. Then select “OK”.

SETTING UP THE SIMULATION After setting up the models files and simulation directory, you must set up the simulation. This includes setting up the type of simulation to be performed, setting up the parameters of that particular type of simulation (like simulation time for transient analysis, giving values to the variables in the schematic, and selecting outputs to be plotted.

SIMULATION TYPE To select the simulation type, select Analyses Choose and select the type of analysis that you wish to have performed. For timing information extraction, transient analysis is the most appropriate. To enable the transient analysis, write

13

a value for the time duration for the simulation and select the “Enabled” button at the bottom of the Choosing Analyses window.

SCHEMATIC VARIABLES Next the variables from the schematic must be given values. Select Variables Copy from cellview. The variables will appear in the design variables window as shown below.

14

After the variables appear, they must be given values. Double click on one of them and another window will open so that values can be given to the variables. If the design variables are the delays, pulse widths and periods of the voltage sources in the schematic, those values should be selected to maximize the useful information in the simulation. For example, if the testbench is simulating a nand4x1, a transition at the output will only occur if all four of the inputs are “high” and one input changes, or three are “high” and the “low” input transitions to “high”. To get the most information out of the simulation, all inputs should be “high” and one should transition “low” for a pulse period long enough for a transition at the output to complete and then return “high”. Then another input should follow the same sequence. Having a sequence that maximizes the amount of information per simulation will relieve you from having to run four separate simulations for to capture timing information for all inputs. Creating such a stimulus sequence is not always possible however.

SELECTING THE OUTPUTS TO BE PLOTTED Next the outputs must be selected for them to plot. Select Outputs To be plotted Select from schematic. Then the schematic will popup and you can select the nodes you want plotted. It is best to select a wire that is attached to the node instead of the node itself. To capture timing information for the tested cell, select all of the inputs and the output to the cell. Then press Escape.

SIMULATION, PLOTTING AND TIMING EXTRACTION When Analog Environment has been properly set up for simulation, the simulation button can be pressed to begin. Analog Environment will create a netlist and run the simulation. A waveform window will appear automatically if outputs were selected to be plotted as described in the previous section. Once the waveform appears, you can use the two cursors to measure the time delay between the change in an input and the change in an output of the tested cell. To measure delay from the beginning of the inputs transition to the end of the outputs transition overstates the delay. Therefore, our standard for measuring this delay is to measure the delay between when the input reaches halfway between VDD and ground during its transition and when the output reaches the same point. To use the cursors, press “a”, and a cursor will appear. This can be placed anywhere along any of the plots. Place it midway between ground and VDD on one of the input voltage waveforms while it is in transition. Press “b” and place that cursor midway between ground and VDD on the resulting output transition waveform. In the bottom left, the time and voltage values for each cursor’s intersection point with the waveform will be displayed as shown in the figure below. The red line is the input and the black is the output.

15

Delay Value: 90 ps

Measuring rise time Measure fall time here

POST-LAYOUT SIMULATION WITH ANALOG ENVIRONMENT

DESCRIPTION Several of the components in the digital cell library had extracted layouts in addition to schematics and symbols. The extracted layout creates a netlist that includes parasitic capacitances that are introduced in layout. Simulating the extracted layout is important to get more accurate timing information since rise and fall times are inversely proportional to capacitance. This section includes a brief overview of issues with creating extracted views and a description of how to simulate the extracted view using Analog Environment.

CREATING AN EXTRACTED CELLVIEW After layout has been completed, if the layout can be matched to the schematic by the Layout-Versus-Schematic (LVS) tool, then the layout can be extracted and simulated in the same way that you would simulate the schematic view. Creating a layout that matches the schematic is not trivial. Passing the Design Rule

16

Check (DRC) is no indication that the layout will match the schematic. This section outlines the LVS and extracted view generation.

LAYOUT VERSUS SCHEMATIC Once layout has passed the Design Rule Checker (DRC), the Layout Versus Schematic (LVS) tool can be used to really see how the layout compares to the schematic.

LAYOUT EXTRACTION To create an extracted view of the layout, open the layout after the DRC and LVS are without errors. Select Verify Extract. Then click on the “Set Switches” button and select “Extract parasitic caps”. This process is shown below.

Once you have selected to extract the parasitic capacitance, select “OK” and “OK” to create the extracted view.

17

SIMULATING EXTRACTED LAYOUT IN ANALOG ENVIRONMENT Once there is an extracted layout for a given cell, and the LVS check shows no errors, the extracted layout for that cell can be simulated in the testbench in the same way as the schematic was in the previous section. To simulate, open a testbench and instantiate the tested cell to be simulated. Check and save the schematic of the testbench. Open Analog Environment. The simulation will be nearly identical to that of simulating the schematic cellview. When the Analog Environment window opens, the “view” should be schematic just as it was when simulating the schematic view of the tested component. The view should be schematic because that means that the schematic for your testbench will be simulated—not your extracted view (because there is not an extracted view for the testbench). The difference in simulating the extracted view is that, before simulating, you must select Setup Environment. A window will appear like the one below. In the “Switch View List”, “extracted” must be placed before “schematic”. This will tell Analog Environment to simulate the extracted view before the schematic view of a given cell. If there is no extracted view for a cell in the testbench, the simulator will then use the schematic.

“extracted” must be placed before “schematic” in the switch view list

Once this change has been made, the simulation and extraction is identical to that described in the section “SIMULATION, PLOTTING AND TIMING EXTRACTION”. Note: This document does not include simulation results for the extracted cellviews of the AMI05 Digital Library. In attempting to simulate the extracted views, I encountered errors concerning a mismatching of pins between the extracted layout and the schematic.

18

CREATING TESTBENCHES WITH VERILOG AMS CELLVIEWS

DESCRIPTION In order to begin to move away from graphically based analysis, we used Verilog AMS cellviews to simulate and extract timing information for the AMI05 Digital Library. The Verilog AMS testbench consists of a stimulus module, inverter conditioning, results extractor module and the module of the component that is to be tested. The schematic representation of the testbench is shown below. The stimulus module will output several logic “high” and “low” values that, when changed, will bring about a transition at the output of the cell that is being tested. When that transition occurs at the output of the tested cell, the delay between the change at the output of the stimulus and the output of the tested cell can be determined and saved by the results extractor. These results can be displayed or written to file. The reason for using a system containing modules with Verilog AMS cellviews is that the process can be automated with scripting. Automation is the end goal of this project because it will reduce the amount of time required to extract library timing information, drastically. The automation script is outside the scope of this document, and is a topic that will be discussed in future work.

CREATING VERILOG AMS CELLVIEWS To create a Verilog AMS cellview, first create a schematic containing the inputs and outputs of the cell. This only requires opening up the schematic editor and placing input/output pins in the schematic. Once the Schematic Editor is open, press “p” to insert a pin. Fill in the pin type (output/input), and give the pin a name.

19

Select Input/Output Type and Write Pin Name in Field

Simply Place Pins in Schematic

Once that is done, Select Design Create Cellview from Cellview. The following window will appear.

Change the Tool/Data Type

Select Verilog AMS

Change the Tool/Data Type from Composer Symbol to Verilog AMS. Then press “OK”. Since a symbol cellview of the schematic does not yet exist, you will be prompted to create one. Create the symbol so that the cell can be instantiated into a testbench later. Next, the Emacs Editor will open containing automatically generated, though incomplete, Verilog AMS code. The header and declaration of inputs and outputs of the module will already be written in for you as shown below.

20

Now, the body of the code can be filled in to complete the cellview. In the following sections, I will give two examples of Verilog AMS cellviews. These include the stimulus module and the results extraction module that will be used to in a later testbench.

CREATING THE STIMULUS MODULE To create the stimulus module, I followed the process outlined in [2] and first created a schematic. This schematic and symbol are seen below in figure. It consists only of pins that represent the outputs of the stimulus module. There are four outputs that have been labeled “A”, “B”, “C” and “D”. These outputs will feed into inverters that will feed into the inputs to the tested cell. As mentioned in previous sections, the inverters serve to make the input to the tested cell a more realistic one—one without an infinite slew rate.

Stimulus Module Schematic (left) and Symbol (right) I chose to have four outputs for the stimulus module because four is the highest number of inputs for any cell that I have tested. The NAND4x1 and NOR4x1 are two examples. If a cell with more than four inputs is to be tested, a minor

21

modification to the stimulus and results extraction modules must be made to add additional outputs to the stimulus module. From the schematic shown in the figure above, I created a Verilog AMS cellview by selecting Design Create Cellview From Cellview. Then I selected to make a Verilog AMS cellview from the current schematic cellview. Then the Emacs editor appears with some of the code already written. The module header as well as the inputs and outputs are declared but the body of the code must be filled in. The body of my code was created by imitating portions of the Veriloga code for the invx1 in the AMI05 digital library [5]. Essentially, the module implements table 1a which is found in Appendix A. This table shows 1 for digital “high” and 0 for digital “low” values as a function of time. In analog, digital “high” is 5 V and digital “low” is 0 V. This is also illustrated in the below figure as a waveform of the stimulus output. The purpose of this sequence is to isolate changes that occur at the output of the tested cell to a change that occurs at a single input to that cell. Therefore, except for when all of the inputs change simultaneously at t=45, 90, 135, 180, 225, 270, 315 ns, only one output of the stimulus module changes in any 5 ns period. The simultaneous change at 45, 90, 135, 180, 225, 270, 315 ns is necessary to ensure that both NAND type gates and NOR type gates as well as hybrids of the two types can be tested properly. The simultaneous changing of the stimuli are for setting up a stimulus state that are necessary to test different types of gates. For example, to test a NAND type gate, all inputs must be high while one of the inputs is transitioning to see any change at the output. For a NOR type gate, all inputs must be low while one of the inputs is transitioning to see a change at the output. Therefore, there must be a switch between these tests at some point. Furthermore, to test the XOR or XNOR, requires both the remaining inputs “high” and remaining inputs “low” scenarios. To test a hybrid of the NOR and NAND types requires that some are tied low and some high. For example, to test the effect of a transition at input A for an ao22x1, B would need to be high, and C and D would need to be low during the transition at input A.

22

Output waveform from stimulus (from top to bottom) A, B, C, D 5 ns was chosen as the period between transitions, because I determined that is sufficient time for any cell component in the AMI05 digital library to complete a transition. Most of transient responses of the cells in the library die out within 1 ns. If a longer transition time is needed to accommodate a slower cell, the period of the stimulus can be increased from 5 ns to any arbitrary time period by modifying the Verilog AMS code. Some of the Verilog AMS code for the stimulus module is included below. The full code is in appendix A. The code consists of digital logic and analog sections. In the logic section, the logical values is initialized and assigned in time. In the analog section, the analog execution of the digital section occurs.

initial begin a=0; b=0; c=0; d=0; #5 a=1; #5 a=0; #5 b=1; #5 b=0; #5 c=1; #5 c=0; #5 d=1; #5 d=0; #5 a=1;b=1;c=1;d=1; In the digital section, “initial begin” signifies the simulation time starting point. Time is incremented by writing “#5”. Each time that is written, 5 time steps

23

advance. In this code, a single time step is 1 ns so #5 advances 5 ns. The above code runs through the first 45 ns of simulation time. In the analog section, an analog electrical value is placed at the output using the “transition” function as shown below. V(Out1) <+ transition( vout_val1,delay,rise time, fall time); The voltage of output Out1 is passed a value of vout_val1 and the parameters for how it is passed appear as arguments in transition(). The parameters values “delay”, “rise” and “fall” were purposefully made as close to 0 as possible to mimic a step function (0 rise time and fall time values were prohibited so 1ps was used). The value of vout_val1 was determined by logic statements in the body of the code. vout_val1 = !(a) ? vlogic_high : vlogic_low; “a” is the variable that appears in the “initial begin” section of the code. So at any simulation time, the value of “a” is checked and the logic statement is evaluated and either vlogic_high or vlogic_low is passed to vout_val1. In the simulations of the AMI05 Digital Library, vlogic_low = 0 and vlogic_high = 5 because this is in the analog domain. Identical code was used to control all four stimuli. The full code appears in Appendix A. The outputs from the module are fed into inverters from the digital library (invx1) in order to condition the stimuli to be more realistic. In the figure below, the final conditioned stimulus output is shown below feeding a nand4x1.

24

CREATING THE RESULTS EXTRACTOR The results extractor monitors the inputs and outputs of the tested cell and determines the rise and fall times of the cell due to a transition at each input. The schematic for the results extractor is included below in the figure below.

Schematic (left) and symbol (right) for results extractor The results extractor contains only inputs. These inputs are A, B, C, D, Out1 and Out2. The lettered inputs are there to monitor voltage values of the four outputs from the conditioned stimulus, which I discussed in a previous section. Out1 and Out2 are to monitor up to two voltage values for the outputs of the tested cell. If a cell has more than two outputs, the code must be modified to add that capability. Out1 and Out2 are loaded with an input to a nand2x1. The wires labeled gnd! and vdd! are to make use of the global variables for ground and vdd.

TIME CAPTURE WITH cross() and last_crossing() FUNCTIONS The inputs of the results extractor are all given type electrical. Type electrical allows for analysis of these inputs as electrical signals. The results extractor is constantly obtaining voltage values for all of the inputs of type electrical. We can use this constant monitoring to test when the an input has crossed a certain voltage value by using the cross() and last_crossing() functions as found in [4]. Since our standard for measuring delays between the input and output of a cell is to take time measurements when the input and output voltages of that cell cross the midway point between vdd and gnd. We can call this point Vmid. Vmid is calculated by the following: Vmid = (vdd+gnd)/2+gnd The cross() and last_crossing() functions will return the time value for when an input voltage crosses Vmid. These functions appear in the following form in the code for the results extractor.

25

V(inputA) is the voltage value of the input named inputA. This is monitored constantly by the results extractor. When V(inputA)-Vmid = 0 and the next value is positive (signifying that V(inputA) is rising) , the above code will capture the current simulation time in the variable named “time_value1”. If the second argument in both the cross() and last_crossing() functions were -1 instead of +1, then the functions would only capture the simulation time value if V(inputA) had crossed on a falling edge. Determining the whether there is a rising or falling edge for an input is important to distinguish between rising and falling times for a tested cell. So, during any point in the simulation time, if an input or output voltage of the tested cell transitions between “low” and “high”, the simulation time is captured. If this occurs at one of the outputs, the results extractor determines whether that transition in the output was due to a single input. If it was due to a single input, then a delay time is calculated, and labeled as a rising or falling delay time due to a single input.

DETERMINING THE INPUT Once the cross() function has been triggered by one of the tested cell’s output voltages, the results extractor seeks the cause of the change in the output. The results extractor determines the cause of the change at the output by comparing the cross() times for the inputs. The input that most recently crossed the midway point between vdd and gnd is determined to be the cause of the change at the output. Since, the stimulus module has a sequence that includes multiple stimuli voltages changing at the same time, it is not certain that a sensed change at the tested cell’s output is due to a single input. Therefore, the results extractor disregards changes at the output that are due to more than one input. Multiple coincident input changes occur, because they are needed in the stimulus module to set up different simulation states—to test all possible types of cells (nand, nor, xor, etc.)

26

The results extractor determines whether or not to disregard an output change by comparing the cross() values for the inputs. If the most recent input to cross the midway point is within a certain time period, Tcoincident, of another input’s crossing time, the results extractor disregards the output change. Since the stimulus module’s sequence is known, a time period can be chosen that is short enough to allow the results extractor to capture timing information. In the stimulus module, the period between stimuli changes is 5 ns. Therefore, Tcoincident must be significantly smaller than 5 ns, because, otherwise, all results may be discarded. Furthermore, Tcoincident must be large enough to accommodate small differences in the captured times of inputs that change simultaneously. Even though the stimulus module outputs simultaneous changes, they are usually captured by the results extractor with slight differences. I determined a good Tcoincident to be 1 ns, which is in the proper range to accommodate both issues.

FINDING THE GREATEST DELAY TIME During the life of the simulation, there can be multiple values for a delay due to an input. The import value is the greatest value since that represents the most delay and, therefore, the worst case scenario that will occur at that input to the tested cell. A simple algorithm causes the results extractor to capture a delay value only if it is greater than the previously stored value. This algorithm is included below. If (new_delay_value>old_delay_value) begin old_delay_value = new_delay_value; end The old_delay_value will be the final value displayed at the final step of the simulation.

SIMULATION WITH THE HIERARCHY EDITOR

DESCRIPTION In addition to simulation using Analog Environment, simulation with the Hierarchy Editor allows for the extraction of timing information. This section discusses running simulations through the Hierarchy Editor.

27

HIERARCHY EDITOR SETUP The setup procedure for the Hierarchy Editor can be found in Brian Dupaix ECE 894z report [2]. This report covers most of the setup procedure. However, the library and cell names should be different according to which library and cell you wish to simulate. In addition to the setup procedure listed in that report, make sure that your cds.lib contains the lines listed on page 7. Furthermore, I include the Hierarchy Editor windows below to illustrate how the fields were filled in for simulating a cell called TESTBENCH2 from library ParryLibTest. This cell was a testbench used to simulate cells. It made use of the simulation module called TESTBENCH and a results extractor called TESTBENCH_CAPTURE. ParryLibTest was a library I created specifically for the simulation of the cells in the AMI05 Digital Cell Library. Here is the schematic TESTBENCH2.

To create a config cellview from this schematic cellview, select Design Create Cellview From Cellview. This opens the Hierarchy Editor. After updating and selecting the AMS plug-in, the window should appear like below.

28

Tested Cell: nand4x1View to use: schematic

nand2x1 load (use schematic view)

Stimulus ConditioningInverters

(use schematic view)

pmos4/nmos4 from invx1 and nand2x1(use Spectre view)

Use schematic view

Must select pluggin AMS to access AMS tab

NOTE: To simulate the extracted view, you only need to change thetested cell’s “View to Use” to “extracted” from “schematic”. In thcase the nand4x1 view would be “extracted” while all other views would remain the same.

Selecting AMS Analog Models Setup is necessary to resolve the nmos4 and pmos4 found in the schematic views of the invx1, nand2x1 and nand4x1. The window below shows the model library to use. It is the same model library used in the Analog Environment simulation. /opt/local/cadence/design_kits/NCSU/ncsu_cdk.1.3VT/local/models/spectre/nom/allModels.scs

29

The final step in fully setting up the Hierarchy Editor for simulation is filling in certain fields in the simulation window. Select AMS Run Simulation. If that prompts the program to ask if you want to run design prep then do so. After design prep completes, click “OK” and the simulation window should appear as it does below. The library and cell will be different if you are not using this particular library and cell.

Fill in Connect Ruleswith these values

RUNNING SIMULATIONS AND EXTRACTING TIMING INFORMATION Once the Hierarchy Editor is setup, the simulation can be run directly from the window shown above. Selecting run will bring up the SimVision Design Browser shown below.

30

When this window appears, you can simulate immediately or bring up the waveform window first and then simulate. You can not simulate more than once. If you do not bring up the waveform window before you simulate, you will not be able to view the waveform unless you return to the Hierarchy Editor and restart the simulation. In addition to the SimVision Design Browser, the SimVision Console appears. When simulating with the results extractor, the delay times will be displayed in the console. The console appears as it does below.

To simulate the tested cell with the waveform window, click on the waveform window button that is located on the Design Browser. The waveform will appear.

31

Click the simulate button. The simulation with run and the results will appear as they do below.

If you zoom in to the point where the output transitions (the output is the bottom line), you can use the cursors to capture the timing information as shown in the figure below.

However, the point of using the results extractor was to steer away from extracting the information graphically. The results extractor displays the results automatically on the SimVision Console.

32

NOTE ON SIMULATING THE EXTRACTED VIEW WITH HIERARCHY EDITOR The extracted view can be simulated instead of the schematic view for a given test cell. This requires that there is a working extracted view. All that needs to be changed to simulate the extracted view is that, in the Hierarchy Editor, the field named “View to Use” should be change to extracted view for the tested cell. This should be switched for the tested cell only.

33

COMPARISON OF RESULTS

DESCRIPTION I detailed two methods of results extraction. The first, using Analog Environment waveform window, is a graphical way to extract information. This can be very time consuming. Throughout this project, I resimulated several times and it can be very slow and tedious. The second method, using a Verilog AMS results stimulus and results extractor in the testbench and simulating with the Hierarchy Editor, provides a slightly faster way to extract the timing information. This section discussed the results from the two different methods.

RESULTS The results from the two different simulation types corroborate. Therefore, I have confidence that the results extractor does a proper job in extracting information. The table below contains the results for several of the logic gates in the AMI05 Digital Library. The simulation was done with VDD=5V, GND=0V. The load was an input to a nand2x1. In each simulation, the system was in steady-state before any transition was made. The measurements for the Analog Environment simulations are less precise because measurements were taken visually with cursors.

Analog Environment Results Extractor Schematic View Simulation Schematic Simulation

Cell Name

Rise Time (ps)

Fall Time (ps)

Rise Time (ps)

Fall Time (ps)

ao22x1 a 565 546 565.2 548.9 B 535 486 537.4 488 C 366 382 367 383.5 D 390 440 394.3 442.3

aoi22x1 A 385 403 386.2 405 B 333 376 334.3 376.9 C 230 215 229.7 216.5 D 278 241 279.2 243.3

bufx1 198 193 197.7 194 bufx4 285 275 285.3 277.2 bufzx1

A 371 348 372.9 349.7 Tristate 315 237 316.4 236.5 invzx1

A 223 235 225.6 237.3

34

Tristate Na Na 147.6 227.8 invx1 89 100 90.6 99.6 invx4 90 101 92.1 103.2

nand2x1 A 108 180 110 181.9 B 133 206 133.5 208.9

nand3x1 A 165 371 164.3 371 B 151 338 153.4 339.9 C 127 280 128 279

nand4x1 A 187 579 187.9 581.2 B 185 547 185.2 550.5 C 169 483 170.8 484.9 D 145 390 144.6 391.4

nor2x1 A 210 153 208 154.7 B 154 114 154 117.5

nor3x1 A 378 181 379 182.7 B 326 171 326.4 172.1 C 215 129 212.8 130.6

nor4x1 A 265 142 267 142.7 B 434 179 435.6 185.3 C 547 201 548.8 200.9 D 593 198 598.9 198.1

xnor2x1 A 391 369 392.9 372.2 B 413 339 415.5 340.7

xor2x1 A 345 456 344 456.8 B 328 403 330.5 405.8

35

REMAINING LIBRARY WORK

DESCRIPTION Although, using the Hierarchy Editor along with the results extractor does save some time, the real benefit of using Verilog AMS modules in simulation will only be realized once an automation script is written to completely remove any graphical interfacing from the timing extraction process. Writing this script is the next step. It will require a thorough understanding of how the process works at the command line level. Secondly, work must be done to prepare the extracted views of the AMI05 Digital Library to be simulated. This will require removing any discrepancies between the layout pins and the schematic and the extracted layout.

CONCLUSION Both Analog Environment and the Hierarchy Editor are useful for running transient analysis of cells. However, timing extraction using a GUI is a very tedious process, especially if you have to do it repeatedly because you failed to load the tested cell properly or used the wrong VDD value (trust me). If a library contains only a handful of cells, using a GUI may be worthwhile. But if one encounters a sizable library, simulation with a GUI makes little sense. As the AMI05 Digital Library expands to a size that is too large to simulate one-by-one, the use of Verilog AMS modules and automation are a necessity. The results extractor takes a step towards that end. The results extractor performed nicely by matching the results found manually from plotting. The next step is to write and automation script to remove the dependency on the GUI and speed up the process. Furthermore, the results extractor can be expanded to find different types of information beyond input delay.

36

APPENDIX A

STIMULUS MODULE LOGIC TABLE

Time (ns) A B C D Time

(ns) A B C D 0 0 0 0 0 180 1 0 0 1 5 1 0 0 0 185 0 0 0 1

10 0 0 0 0 290 1 0 0 1 15 0 1 0 0 195 1 1 0 1 20 0 0 0 0 200 1 0 0 1 25 0 0 1 0 205 1 0 1 1 30 0 0 0 0 210 1 0 0 1 35 0 0 0 1 215 1 0 0 0 40 0 0 0 0 220 1 0 0 1 45 1 1 1 1 225 0 1 1 0 50 0 1 1 1 230 1 1 1 0 55 1 1 1 1 235 0 1 1 0 60 1 0 1 1 240 0 0 1 0 65 1 1 1 1 245 0 1 1 0 70 1 1 0 1 250 0 1 0 0 75 1 1 1 1 255 0 1 1 0 80 1 1 1 0 260 0 1 1 1 85 1 1 1 1 265 0 1 1 0 90 1 1 0 0 270 0 1 0 1 95 0 1 0 0 275 1 1 0 1 100 1 1 0 0 280 0 1 0 1 105 1 0 0 0 285 0 0 0 1 110 1 1 0 0 290 0 1 0 1 115 1 1 1 0 295 0 1 1 0 120 1 1 0 0 300 0 1 0 1 125 1 1 0 1 305 0 1 0 0 130 1 1 0 0 310 0 1 0 1 135 0 0 1 1 315 1 0 1 0 140 1 0 1 1 320 0 0 1 0 145 0 0 1 1 325 1 0 1 0 150 0 1 1 1 330 1 1 1 0 155 0 0 1 1 335 1 0 1 0 160 0 0 0 1 340 1 0 0 1 165 0 0 1 1 345 1 0 1 0 170 0 0 1 0 350 1 0 1 1 175 0 0 1 1 355 1 0 1 0

37

STIMULUS MODULE VERILOG AMS CODE //Verilog-AMS HDL for "ParryLibTest", "TESTBENCH" "verilogams" `include "constants.vams" `include "disciplines.vams" `timescale 1ns/1ns `include "constants.h" `include "disciplines.h" /* This module provides stimuli for the testing of cell components in a testbench. The purpose is to provide a sequence of stimuli from which all the timing information about delays between the inputs to a given tested cell and the outputs to that cell can be determined. This must be true regardless of what type of cell is being tested. The symbol of this module can be instantiated into a testbench as the input stimulus to the tested cell. */ module TESTBENCH ( VDD, Out1,Out2,Out3,Out4, GND ); //Module has only stimuli outputs and VDD, GND output VDD; output GND; output Out1; output Out2; output Out3; output Out4; electrical VDD,GND,Out1,Out2,Out3,Out4; //The vdd value is set as a parameter so it can be changed from //outside the code. Vdd can be set anywhere between -20 and 20, //but it was just an arbitrary range. parameter real vdd=5 from [-20:20]; parameter real gnd=0 from [-20:20]; // vout_val is a local variable that will be passed to the outputs using // the transition() function. vlogic_high and vlogic_low are local variables // that store vdd and gnd to be passed to vout_val. real vout_val1,vout_val2,vout_val3,vout_val4, vlogic_high, vlogic_low;

38

//int a,b,c,d are to establish a sequence in time for the output. They //are initialized at zero and begin to change at t=5ns. integer a,b,c,d; //The "initial" section contains the digital representation of the //sequence of the stimulus outputs. Every #5 advanced time 5 ns. initial begin a=0; b=0; c=0; d=0; #5 a=1; #5 a=0; #5 b=1; #5 b=0; #5 c=1; #5 c=0; #5 d=1; #5 d=0; #5 a=1;b=1;c=1;d=1; #5 a=0; #5 a=1; #5 b=0; #5 b=1; #5 c=0; #5 c=1; #5 d=0; #5 d=1; #5 a=1;b=1;c=0;d=0; #5 a=0; #5 a=1; #5 b=0; #5 b=1; #5 c=1; #5 c=0; #5 d=1; #5 d=0; #5 a=0;b=0;c=1;d=1; #5 a=1; #5 a=0; #5 b=1; #5 b=0;

39

#5 c=0; #5 c=1; #5 d=0; #5 d=1; #5 a=1;b=0;c=0;d=1; #5 a=0; #5 a=1; #5 b=1; #5 b=0; #5 c=1; #5 c=0; #5 d=0; #5 d=1; #5 a=0;b=1;c=1;d=0; #5 a=1; #5 a=0; #5 b=0; #5 b=1; #5 c=0; #5 c=1; #5 d=1; #5 d=0; #5 a=0;b=1;c=0;d=1; #5 a=1; #5 a=0; #5 b=0; #5 b=1; #5 c=1; #5 c=0; #5 d=0; #5 d=1; #5 a=1;b=0;c=1;d=0; #5 a=0; #5 a=1; #5 b=1; #5 b=0; #5 c=0; #5 c=1; #5 d=1; #5 d=0; end //This is the analog section. It assigns either vdd or gnd to the four //outputs based on the sequence established in the previous section. analog begin

40

//This passed vdd to the output VDD so that the testbench can use //one value of vdd that originates from the stimulus module V(VDD)<+vdd; //This does the same thing for gnd. Although it is not useful because //it cannot be connected with the global gnd! wire. V(GND)<+gnd; //This sets the dummy variables for high and low to vdd and gnd vlogic_high = V(VDD); vlogic_low = V(GND); //This code was taken from the code for the inverter invx1 in the //AMI05 digital library. It assigns a value of vlogic_high or vlogic_low //to each of the vout_vals based on the sequence established in the //initial section. vout_val1 = !(a) ? vlogic_high : vlogic_low; vout_val2 = !(b) ? vlogic_high : vlogic_low; vout_val3 = !(c) ? vlogic_high : vlogic_low; vout_val4 = !(d) ? vlogic_high : vlogic_low; //Then it passes that value to the corresponding output using the //function transition(vout_val,delay,rise,fall). Delay time was set //to 0, rise and fall times were set to 1ps. The idea was to have a //perfect step function, but the rise/fall times cannot be 0, so I set //them as small as possible. V(Out1) <+ transition( vout_val1,0,1p,1p); V(Out2) <+ transition( vout_val2,0,1p,1p); V(Out3) <+ transition( vout_val3,0,1p,1p); V(Out4) <+ transition( vout_val4,0,1p,1p); end endmodule

RESULTS EXTRACTOR VERILOG AMS CODE //Verilog-AMS HDL for "ParryLibTest", "TESTBENCH_CAPTURE" "verilogams" `include "constants.vams" `include "disciplines.vams" `timescale 1ns/1ns

41

/* This module is a results extractor that captures information about the delay between each input of a cell and its output. The inputs to the module are A,B,C,D,Out1,Out2. The lettered inputs are the inputs to the tested cell. Out1 and Out2 are the outputs of the cell. When one of the input voltages crosses halfway between vdd and gnd, the simulation time is saved. If the voltage of Out1 or Out2 crosses halfway between vdd and gnd, simulation time is saved, and the delay between that input and A,B,C, or D is calculated. The extractor knows which input to the tested cell caused the change in output by determining which input to the cell most recently changed. If two or more inputs to the cell change at one time, the extractor ignores any change at the output of the cell. Therefore, it is able to find the delay information due to each input. */ module TESTBENCH_CAPTURE ( A, B, C, D, Out1, Out2); input C; input Out1; input A; input D; input B; input Out2; electrical A,B,C,D,Out1,Out2,r1,r2,r3,r4,f1,f2,f3,f4; real half, time1, time1a, time1ad, time2, time2ad, time2a, time3, time3a, time3ad, time4, time4a, time4ad, time1o, time1oad, time1oa, time2o, time2oa, time2oad, difference1_rise, difference1_fall, difference2_rise, difference2_fall, difference3_rise,difference3_fall,difference4_rise,difference4_fall; parameter real vdd=5 from [-20:20]; parameter real gnd=0 from [-20:20]; integer logic1,logic2,logic3,logic4,logic1o,logic2o; analog begin @(initial_step) begin //Half is the voltage value halfway between vdd and gnd half=(vdd+gnd)/2+gnd; //These are the simulation time values when an input to the

42

//tested cell crosses half. They are initialized at zero. time1=0; time2=0; time3=0; time4=0; //These are the simulation time values when an output of the //tested cell crosses half. They are initialized at zero. time1o=0; time2o=0; end half=(vdd+gnd)/2+gnd; /* logic1=V(A)>half; logic2=V(B)>half; logic3=V(C)>half; logic4=V(D)>half; logic1o=V(Out1)>half; logic2o=V(Out2)>half; */ /* This is the heart of the time capturing mechanism. The functions last_crossing() and cross() are used in tandem to provide accurate timing information. When the @(cross()) function is triggered by one of the inputs or outputs to the tested cell crossing the halfway voltage, the simulation time returned by last_crossing() is saved to the corresponding input or output to the tested cell. Whether the halfway voltage is crossed on the way up or down is determined by the function. For example, last_crossing(a,+1) only triggers when a=0 and the next value of a is positive Thus signifying a rising voltage. */ time1a=last_crossing(V(A)-half,1); time1ad=last_crossing(V(A)-half,-1); time2a=last_crossing(V(B)-half,1); time2ad=last_crossing(V(B)-half,-1); time3a=last_crossing(V(C)-half,1); time3ad=last_crossing(V(C)-half,-1); time4a=last_crossing(V(D)-half,1); time4ad=last_crossing(V(D)-half,-1);

43

time1oa=last_crossing(V(Out1)-half,1); time1oad=last_crossing(V(Out1)-half,-1); time2oa=last_crossing(V(Out2)-half,1); time2oad=last_crossing(V(Out2)-half,-1); @(cross(V(A)-half,1)) begin time1=time1a; end @(cross(V(A)-half,-1)) begin time1=time1ad; end @(cross(V(B)-half,1)) begin time2=time2a; end @(cross(V(B)-half,-1)) begin time2=time2ad; end @(cross(V(C)-half,1)) begin time3=time3a; end @(cross(V(C)-half,-1)) begin time3=time3ad;end @(cross(V(D)-half,1)) begin time4=time4a;end @(cross(V(D)-half,-1)) begin time4=time4ad;end /* When one of the outputs to the cell crosses the halfway voltage, the extractor determines the delay between that output and the most recent input of the tested cell to change. If the change in the tested cell's output occurs because of a change in more than one input, a delay is not calculated. More accurately, if more than one input to the cell change within 1ns of one another, the only way that a delay time is calculated is if neither of those inputs were the most recent input to change. The most recent input to change is determined by merely comparing "time1","time2",time3" and "time4" to see which stored simulation time is higher. */ @(cross(V(Out1)-half,1)) begin time1o=time1oa; if ((time1 > time2 && time1 > time3 && time1 > time4) && abs(time4-time1)>1n && abs(time1-time2) > 1n && abs(time1-time3) > 1n) begin //this will ensure that only the longest delay time will be the final value if (time1o-time1>difference1_rise) begin difference1_rise=time1o-time1; end end if ((time2>time1 && time2>time3 && time2>time4) && abs(time1-time2)>1n && abs(time2-time3)>1n && abs(time4-time2)>1n) begin

44

if (time1o-time2>difference2_rise) begin difference2_rise=time1o-time2; end end if ((time3>time2 && time3>time1 && time3>time4) && abs(time1-time3)>1n && abs(time2-time3)>1n && abs(time4-time3)>1n) begin if (time1o-time3>difference3_rise) begin difference3_rise=time1o-time3; end end if ((time4>time2 && time4>time3 && time4>time1) && abs(time4-time1)>1n && abs(time4-time3)>1n && abs(time4-time2)>1n) begin if (time1o-time4>difference4_rise) begin difference4_rise=time1o-time4; end end end @(cross(V(Out1)-half,-1)) begin time1o=time1oad; if ((time1>time2 && time1>time3 && time1>time4) && abs(time4-time1)>1n && abs(time1-time2)>1n && abs(time1-time3)>1n) begin if (time1o-time1>difference1_fall) begin difference1_fall=time1o-time1; end end

45

if ((time2>time1 && time2>time3 && time2>time4) && abs(time1-time2)>1n && abs(time2-time3)>1n && abs(time4-time2)>1n) begin if (time1o-time2>difference2_fall) begin difference2_fall=time1o-time2; end end if ((time3>time2 && time3>time1 && time3>time4) && abs(time1-time3)>1n && abs(time2-time3)>1n && abs(time4-time3)>1n) begin if (time1o-time3>difference3_fall) begin difference3_fall=time1o-time3; end end if ((time4>time2 && time4>time3 && time4>time1) && abs(time4-time1)>1n && abs(time4-time3)>1n && abs(time4-time2)>1n) begin if (time1o-time4>difference4_fall) begin difference4_fall=time1o-time4; end end end @(cross(V(Out2)-half,1)) begin time2o=time2oa; if ((time1>time2 && time1>time3 && time1>time4) && abs(time4-time1)>1n && abs(time1-time2)>1n && abs(time1-time3)>1n) begin if (time2o-time1>difference1_rise) begin difference1_rise=time2o-time1;

46

end end if ((time2>time1 && time2>time3 && time2>time4) && abs(time1-time2)>1n && abs(time2-time3)>1n && abs(time4-time2)>1n) begin if (time2o-time2>difference2_rise) begin difference2_rise=time2o-time2; end end if ((time3>time2 && time3>time1 && time3>time4) && abs(time1-time3)>1n && abs(time2-time3)>1n && abs(time4-time3)>1n) begin if (time2o-time3>difference3_rise) begin difference3_rise=time2o-time3; end end if ((time4>time2 && time4>time3 && time4>time1) && abs(time4-time1)>1n && abs(time4-time3)>1n && abs(time4-time2)>1n) begin if (time2o-time4>difference4_rise) begin difference4_rise=time2o-time4; end end end @(cross(V(Out2)-half,-1)) begin time2o=time2oad; if ((time1>time2 && time1>time3 && time1>time4) && abs(time4-time1)>1n && abs(time1-time2)>1n && abs(time1-time3)>1n) begin

47

if (time2o-time1>difference1_fall) begin difference1_fall=time2o-time2; end end if ((time2>time1 && time2>time3 && time2>time4) && abs(time1-time2)>1n && abs(time2-time3)>1n && abs(time4-time2)>1n) begin if (time2o-time2>difference2_fall) begin difference2_fall=time2o-time2; end end if ((time3>time2 && time3>time1 && time3>time4) && abs(time1-time3)>1n && abs(time2-time3)>1n && abs(time4-time3)>1n) begin if (time2o-time3>difference3_fall) begin difference3_fall=time2o-time3; end end if ((time4>time2 && time4>time3 && time4>time1) && abs(time4-time1)>1n && abs(time4-time3)>1n && abs(time4-time2)>1n) begin if (time2o-time4>difference4_fall) begin difference4_fall=time2o-time4; end end end time1a=last_crossing(V(A)-half,1); time1ad=last_crossing(V(A)-half,-1); time2a=last_crossing(V(B)-half,1); time2ad=last_crossing(V(B)-half,-1); time3a=last_crossing(V(C)-half,1); time3ad=last_crossing(V(C)-half,-1); time4a=last_crossing(V(D)-half,1); time4ad=last_crossing(V(D)-half,-1);

48

time1oa=last_crossing(V(Out1)-half,1); time1oad=last_crossing(V(Out1)-half,-1); time2oa=last_crossing(V(Out2)-half,1); time2oad=last_crossing(V(Out2)-half,-1); /* This section is commented out. It was used to test the values of the delay times of the entire life of the simulation to see how they change. to reactivate it, r1,r2...f3,f4 must be declared as outputs to the module so they can be plotted. V(r1)<+transition(difference1_rise,0,0,0); V(f1)<+transition(difference1_fall,0,0,0); V(r2)<+transition(difference2_rise,0,0,0); V(f2)<+transition(difference2_fall,0,0,0); V(r3)<+transition(difference3_rise,0,0,0); V(f3)<+transition(difference3_fall,0,0,0); V(r4)<+transition(difference4_rise,0,0,0); V(f4)<+transition(difference4_fall,0,0,0); */ /* At the final step of the simulation, the delay values are displayed. There will be rise and fall values for each input to the tested cell. If there are less than four inputs to the tested cell, those unused stimulus inputs will appear to have delays of zero, which is the value they were initialized at. */ @(final_step) begin

//This displays the delays due to each input. The values are multiplied by //1e12 so they will be in pico seconds

$display("\nInput 1\n rise 1 = %f fall 1 = %f \nInput 2\n rise 1 = %f fall 2 = %f\nInput 3\n rise 3 = %f fall 3 = %f\nInput 4\n rise 4 = %f fall 4 = %f\n\n",1e12*difference1_rise,1e12*difference1_fall,1e12*difference2_rise,1e12*difference2_fall,1e12*difference3_rise,1e12*difference3_fall,1e12*difference4_rise,1e12*difference4_fall); end end endmodule

49

REFERENCES

[1] James Robert Copus, “Open Digital HDL to Synthesized Layout Flow for Mixed-Signal IC’s,” Master’s Thesis, The Ohio State University, 2003.

[2] Brain Dupaix, “Report for EE894Z,” ece 894z report, The Ohio State University, 2004.

[3] “Cadence Tutorial.” Internet: VLSI Cad Laboratory Worchester Polytechnic Institute, http://lsmwww.epfl.ch/Education/CadenceTutorial/examples/post.3.html, accessed November, 2005.

[4] Open Verilog International, “VerilogA Language Reference Manual: Analog Extensions to Verilog HDL,” August, 1996 [5] Jason Parry, AMI05 Digital Library, The Ohio State University, May 2001.