Through Silicon Via(TSV) in System On Chip(SOC)

Team Members

Zalak Rathod (1000710910) Deval Pandya (1000614250)

Umang Dighe (1000677463) Sahil Ajani (1000726667)

Outline of presentation

• Introduction of 3D integration and TSV

Definition: fabrication of stacked and vertically interconnected device layers

Why 3D integration?:◦ Form factor: reduced volume,

weight, reduced foot print◦ Performance: short

interconnection, improved transmission speed, less power consumption

◦ More than Moore application: Integration of heterogeneous application.

3D Integration Technologies:◦ Stacking packages◦ Die stacking without TSV◦ TSV Technology

3D Integration

P. Ramm, A. Klumpp, J. Weber, N. Lietaer, M. Taklo, W. De Raedt, T. Fritzsch and P. Couderc, “3D integration technology: Status and application development,” in Proc. 2010 ESSCIRC, Seville, 2010, pp. 9-16.

In simple words, holes are etched through the chip, the holes are plated with metal, and the metal connects to contact points on a second chip lying immediately below the first chip.

Advantages of TSV :◦ High Thermal

Conductivity ◦ High Electrical

Conductivity◦ Excellent Heat

Spreading◦ Tremendous Adhesion

Strength ◦ PC Board Etchable

TSV(Through Silicon Via)

Ref: InterPACK '07, Dr. Agnofer , July 8-12, 2007 ,The Westin Bayshore, 1601 Bayshore Drive, Vancouver, BC

High cost of wafer scale equipment Slow etch rate of silicon that curtails

production Complexities of additional processes to

fabricate conductive pipes insulated from silicon through which they pass

Issues of reliability

Reasons for no wide scale adoption of TSVs

University of Japan and Fujitsu labs. Thinned wafer was stacked on a base wafer After TSV was patterned, it was filled with Cu for

interconnection Wafers were bonded by Benzocyclobutene (BCB) BCB layer also acted as dielectric medium TSVs created By DRIE ( Deep reactive Ion Etching) and

filled by Cu electroplating 7 layers of thinned wafers were stacked.

TSV Interconnect on Wafer on Wafer

Patterned wafer was temporarily bonded to glass wafer Thinned layer was 20μm and BCB was 5μm

Process

Ref : TSV interconnections on Wafer on Wafer with MEMS technology, Fujimoto, et. Al., Japan

Process

Ref : TSV interconnections on Wafer on Wafer with MEMS technology, Fujimoto, et. Al., Japan