thermal noise in n-channel s-si mosfets universidad de salamanca k. fobelets 1 and j.e. velázquez 2...

Thermal Noise in n-Channel s-Si MOSFETs

Universidad de Salamanca

Noise in strained-Si MOSFET for low-power applications

K. Fobelets1 and J.E. Velázquez2

____________________________________________

1Dept. of Electrical and Electronic Engineering, Imperial College, London, UK

2Dept. de Física Aplicada - Universidad de Salamanca



Motivation

Traditionally the improvement of circuit performance in CMOS has been achieved by shifting to the next technology node. But, shrinking under 100-nm, leads to

• Higher fields + Higher channel doping = Mobility degradation

• Leakage currents = Thermal challenges → Interest of low-power

• Increased costs at each new node: Inexorable reduction of ROI

Outcome: Need for performance improvement at the device level in each future technological node



Motivation

Non-optimized BC SiGe MODFET nearly matches 90-nm CMOS performance at low-power!!!

K. Fobelets, W. Jeamsaksiri, C. Papavasilliou, T. Vilches, V. Gaspari, J.E. Velazquez-Perez, K. Michelakis, T. Hackbarth, U. König “Comparison of sub-micron Si:SiGe heterojunction nFETs to Si nMOSFET in present-day technologies”, Solid-State Electronics 48 (2004) 1401–1406



Presentation Outline

1. SS n-channel FETs

2. Device Under Study & Description of the simulation

3. DC and RF results

4. Noise Behaviour

5. Conclusions



Introduction

• Si/SiGe FET technologies will improve analog circuits:

Expected cost than III-V (Si wafers!?)Native CMOS (p-channel or both)SOI way exists!Promising low-power performancesMismatches impact @ a frequency given is if

increases :

• Still a lack of widely established models, measurements, Spice equivalent circuits… and noise analysis

effDD WLII /



• Si strained n-channel on a SiGe relaxed wafer & its equivalent in SGOI (IBM1) – expected at 65-nm

• N-channel stress induced by Si3N4 (Intel2) – introduced at

90-nm

1Rim et al. “Strained Si CMOS (SS CMOS) technology: oportunities and chalenges”, Solid-State Electronics 47 (2003) 1133–11392Mistry et al. “Delaying forever: Uniaxial Strained Silicon Transistors in a 90nm CMOS Technology”, 2004 Symposium on VLSI Technology, Digest of Technical Papers 50-51

Two main ways for SC SS MOSFETs



Si Si1-xGex

a=1 1+0.042x

Strained Si

(100)

(010)

(001)Perpendicular 2 valleys

In-plane 4 valleys

6

4

2

C

Biaxial tensile strain-induced EC splitting in Si



Typical layer sequence for a N-channel BC MODFET

Graded Si1-xGex

P+ Si Substrate

Constant composition Si Ge

N+ Supply layer SiGe

nid Strained Si layernid Spacer layer Si Ge

Ec

e-

Select Doping levelto adjust VTH

Si wafer!!!

Expensive!!!



Graded Si1-xGex

Si Substrate

Constant composition Si0.7 Ge0.3

Supply layer Si0.7 Ge0.3

Si sacrificial layer

Strained Si layerSi0.7 Ge0.3 Spacer layer

Typical layer sequence for a N-channel BC MOSFET

Graded Si1-xGex

Si Substrate

Constant composition Si0.7 Ge0.3

Supply layer Si0.7 Ge0.3

SiO2

Strained Si layerSi0.7 Ge0.3 Spacer layer



Strained-Si MOSFETs vs MODFETs

Trade-off!!!

-More control over the channel by the gate

-Lower mobilities in the channel



Advantages of SC MOSFETs as compared to BC MOSFETs:

• A single epi layer can potentially enhance both electrons and holes mobilities• SC leads to better scaling for nanometric devices• Higher quality of oxides as Ge far from surface• Better channel control (gm potentially higher)• Better S/D resistances (no Ge on the top layer)

Advantages of SC MOSFETs as compared to bulk MOSFETs:

• Extended immunity of Vth face to L reduction• Enhanced mobility for both electrons and holes



Experimental results from Sugii et al. IEEE Trans. Electron Dev. 49 Dec 2002

Vth dependence on Leff






4. Noise Behaviour

5. Conclusions



Virtual Substrate

8nm QW

n-poly

Gate

Source Drain

500nm SBL

6nm SiO2

Simulated Structures

StrainedChannel

Description of the transistor:- SBL composition Si0.7Ge0.3

- VS 0<x<0.3- QW channel is n.i.d.- Lg=100nm-20nm- tox=6nm-2nm-Assumed Z=1m-Implanted S/D regions-Vds very low



Simulation

• 2D Taurus-Medici bipolar simulation

– Parasitic access resistances added RS=RD=100– Fermi statistics– Roldán model to account for mobility degradation at the SiO2/s-Si

interface– High-field transverse and longitudinal effects on mobility

(Caughey-Thomas model)– Doping in S/D regions like Si-implanted

• Hydrodynamic model for electron transport• Parameters from MC simulations• Only thermal noise considered (diffusion noise sources)• No analytic models available, difficulties to use MC codes.



Using the impedance field method (IFM) microscopic AC noise sources distributed throughout the device are modeled for each dc operating point. The noise spectral density is calculated as SV(, i, j) for a couple of electrodes i, j and using SV(, i, j) and Yij parameters the current noise spectral density is calculated SI(, i, j)1.

1F. Bonani, G. Ghione, M.R. Pinto, R.K. Smith, “An Efficient Approach to Noise Analysis Through Multidimensional Phsics-Based Models”, IEEE Transactions on Electron Devices, Vol 45, pp. 261-269, 1998.

Noise Calculation




1. Introduction to SS n-channel FETs



4. Noise Behaviour

5. Conclusions



Transfer Characteristics

LgateVth (V) S(mV/dec)

100nm -0.420 110.0

80nm -0.429 118.0

60nm -0.442 131.1

40nm -0.464 154.0

20nm -0.502 200.8

Poor Sub-threshold behaviour

SGOI

Significant Vth roll-offChannel mobility/Subthreshold slope trade-off (no pockets!!!)S≈3Soptim

VGATE (volts)

-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4

I DR

AIN

(A

)

1e-11

1e-10

1e-9

1e-8

1e-7

1e-6

1e-5

1e-4

20nm 40nm 60nm 80nm 100nm



Transconductance Gate Capacitance

Comments: There is a noticeable shift of the maximum of gm for 20-nm in agreement with the extracted Vth and a large reduction of Cgs

Gate Overdrive (volts)

-0.2 0.0 0.2 0.4

Tra

nsco

nduc

tanc

e (S

/m

)

0

5

10

15

20

25



-0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5

Cgg

(aF

)

1e-1

1e+0




Comments: •At the beginning of the weak-inversion region the cut-off frequency is larger than 1GHz for Lgate in the studied range. •Pure gate-length reduction doesn’t guarantees a better behaviour neither for low-power nor for “conventional” applications.


-0.2 0.0 0.2 0.4

f T (

GH

z)

0

5

10

15

20

25

30



-0.2 0.0 0.2 0.4

Eff

icie

ncy

of

the

tra

nsc

on

du

cta

nce

(vo

lts-1

)

0

5

10

15

20

25

30




Output-Input Capacitive Coupling Feedback: Miller Effect


-0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5

Cgd

(aF

)

1e-1

1e+0



-0.2 0.0 0.2 0.4

Cgd

/Cgg

rat

io

0.30

0.35

0.40

0.45

0.50

0.55

0.60

0.65


Comments: •In strong accumulation the feedback capacitance saturates at 60%. •Pure gate-length reduction doesn’t guarantees a better AC behaviour for low-power applications!







4. Noise Behaviour

5. Conclusions



NFmin vs Idrain

Starting @ 0.1W

20-nm non optimal in terms of NFmin!!!

IDRAIN (A)

1e-8 1e-7 1e-6 1e-5

NF

min (

dB)

0

5

10

15

20

25


IDRAIN (A)

1e-8 1e-7 1e-6 1e-5

NF

min (

dB)

0

5

10

15

20

25


IDRAIN (A)

1e-8 1e-7 1e-6 1e-5

NF

min (

dB)

0

5

10

15

20

25


10MHz 100MHz 1GHz



Noise figure @ 1GHz Analysis

IDRAIN (A)

1e-8 1e-7 1e-6 1e-5

Rno

ise

()

0.0

2.0e+6

4.0e+6

6.0e+6

8.0e+6

1.0e+7

1.2e+7

1.4e+7

1.6e+7

1.8e+7


IDRAIN (A)

1e-8 1e-7 1e-6 1e-5

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40




Noise figure @ 1GHz Analysis

SI,GATE @ 1GHz

Gate Overdrive

1e-7 1e-6 1e-5

Spe

ctra

l Den

sity

(m

A2/H

z)

1e-24

1e-23

1e-22

1e-21

1e-20


SI,DRAIN @ 1GHz

Gate Overdrive

1e-7 1e-6 1e-5

Sp

ect

ral D

en

sity

(m

A2 /H

z)

1e-20

1e-19

1e-18

1e-17




Evolution of NFmin with frequency (20nm)

The range of minimum NFmin shrinks as f increases whereas gm,max stands at VGS>Vth (≈0.5W)

Idrain (A)

1e-7 1e-6 1e-5

NF

min

(d

B)

0

2

4

6

8

10

12

14

16

18

1GHz 100MHz 10MHz



Transfer Characteristics

toxVth (V) S(mV/dec)

2nm -0.467 148.0

3nm -0.477 118.0

4nm -0.487 131.1

5nm -0.497 154.0

6nm -0.506 200.8

Moderate impact on SVGATE (volts)

-1.0 -0.5 0.0 0.5 1.0

I DR

AIN

(A

)

1e-9

1e-8

1e-7

1e-6

1e-5

1e-4

2nm 3nm 4nm 5nm 6nm




-0.2 0.0 0.2 0.4

NF

min

(dB

)

0

5

10

15

20

25

2nm 3nm 4nm 5nm 6nm

Lgate=20nm, varying tox



Scaled structures comparison

IDRAIN (A)

1e-8 1e-7 1e-6 1e-5

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

20nm_2nm 40nm_4nm 60nm_6nm

X Data

1e-8 1e-7 1e-6 1e-5

NF

min

0

5

10

15

20

25

20nm_2nm 40nm_4nm 60nm_6nm



Conclusions

No special precautionary measures were taken against SCE to reduce Lgate (scaling) SCE must be mitigated without degrading the channel mobility (SGOI)

Therefore: high-mobility in the channel has been preserved, but both a roll off of V th and a significant S degradation arise for short enough gate lengths

The cut-off frequency at Vth exhibits a maximum, but it moves out of the low-powerregion when Lgate decreases in the range 20-100nm.

Gate length shrinking doesn’t guarantees a better NFmin at low currents and leads to noticeable degradation for positive values of gate overdrive in excess of 0.2V.

Finally we shows that the current level at which optimum NFmin is achieved is stable with f in the range (1MHz-1GHz) and it is close to the one that provides gm,max.

A study of the thermal noise @ 300K in the channel of a s-Si SCMOSFET has been presented.



This work was partly funded by EPSRC, MCYT and JCyL



Method for thermal noise calculation (Goo et al. IEEE Trans. Electron Dev. 47 Dec 2000)

xzyqn

kTx

zynDq

fi

S acnn

nin

44 22



ndg

ng

nd

idgii

igi

idi

SAAS

SAS

SAS

*

2

2

IFM

),(),0(),(),0(

,(

1)(

),(),0(),(

)(

1122

2112

21

1122

21

LxYxYLxYxY

LxY

i

ixA

LxYxYLxY

ii

xA

n

gg

n

dd



Transmission Line Model

0

00

0

0

0

02

0

0

0

0

1

1

1

)1(

1

1

1

1

rg

CrjrgD

rg

CrgCj

rg

CCrC

rg

rB

rg

CrjA

m

gsm

m

gdmgs

m

gdgs

m

m

gd

ss

ss

gg

gg

YY

YY

YY

YY

DC

BA

2221

1211

2221

1211



2

2

4x

qNkT

fi

S acelec

nin

Position (m)

0.0 0.2 0.4 0.6 0.8

Tem

pera

ture

(K

)

200

300

400

500

600

700

800

900

1000

VGS = 1.00 V

VGS = 0.85 V

VGS = 0.75 V

VGS = 0.65 V

ID-VGS @ 50mV

VTH=-233mV

S=72mV/decadeZ=100mx=5nmy=8nm

Out of the threshold region y=8nm (QW)

Electron’s temperature @ VGS=1V

Telec,N



Carrier number profile

Position (m)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Noi

se S

pect

rum

(A

2 Hz-1

)

1e-9

1e-8

Vgs = 1.00 V Vgs = 0.85 V Vgs = 0.75 V Vgs = 0.65 V

Noise across the channel



Importance of the lateral design to reduce the Tn!!!

MOSFET vs. MODFET



Position (microns)

0.0 0.2 0.4 0.6 0.8

Abs

olut

e V

alue

of E

lect

ron

char

ge (

C)

1e-17

1e-16

Vgs=0.15V Vgs=0.25V Vgs=0.35V Vgs=0.45V Vgs=0.55V Vgs=0.65V Vgs=0.75V Vgs=0.85V Vgs=1.00V

Influence of the bias point

Position (m)

0.0 0.2 0.4 0.6 0.8

Ele

ctro

n te

mpe

ratu

re (

K)

200

400

600

800

1000

1200

1400

Vgs=0.15V Vgs=0.25V Vgs=0.35V Vgs=0.45V Vgs=0.55V Vgs=0.65V Vgs=0.75V Vgs=0.85V Vgs=1.00V

Position (m)

0.0 0.2 0.4 0.6 0.8

Spe

ctra

l de

nsity

(A

2 s)

1e-10

1e-9

1e-8

Changing VGS

VDS is kept constant



Influence of the SBL doping @ ND

Position (microns)

0.0 0.2 0.4 0.6 0.8

Cur

rent

Sp

ectr

al D

ensi

ty (

A2 s)

1e-9

1e-8 1.1016cm-3

1.1017cm-3 1.1018cm-3

VDS & VGS-VTH kept constant

Virtual Substrate

8nm QW

n-poly

Gate

Source Drain

500nm SBL

5nm SiO2ND



Position (m)

0.0 0.2 0.4 0.6 0.8 1.0

Ele

ctro

n T

em

pe

ratu

re (

K)

200

400

600

800

1000

1200

Lg_0.3micron Lg_0.4micron Lg_0.45micron

Position (m)

0.0 0.2 0.4 0.6 0.8 1.0

Cu

rre

nt S

pec

tra

l De

nsity

(A

2 s)

1e-9

1e-8 Lg_0.3micron Lg_0.4micron Lg_0.45micron

Impact of Lg (VDS scaled down )



Acknowledgements

This work was partly funded by EPSRC (UK) under grant GR/N65844/01, Ministerio de Ciencia y Tecnología (Spain) under grant number TIC2001-1757 and Consejería de Educación, Cultura y Turismo Junta de Castilla y León under grant SA066/02.

thermal noise in n-channel s-si mosfets universidad de salamanca k. fobelets 1 and j.e. velázquez 2...

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