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Design a Clock Distribution for a WCDMA Transceiver System

CSNDSP 2006CSNDSP 2006

Session: B.11 Systems - Simulators Session: B.11 Systems - Simulators

Presenter: Dimitrios EfstathiouPresenter: Dimitrios Efstathiou

July 20July 20thth, 2006, 2006

2

In this presentation we will cover

Where we need Clock Distribution Devices?

Clock Design for a WCDMA Transceiver System

Introduction to ADIsimCLKTM

ADIsimCLKTM Results versus Lab measurements

3

Telecom Infrastructure

ATM Based Network IP Core Network (IPv6, MPLS)

ATM Based Network IP Core Network (IPv6, MPLS)

3G Macro3G Macro

2G Macro2G Macro

4

Solution to save cost, board space

U3U3

Divide by 4Divide by 4

LVPECLLVPECL

U5U5

Delay 1-10nsDelay 1-10ns

LVPECLLVPECL

U1U1

1:4 Fanout1:4 Fanout

BufferBuffer

LVPECLLVPECL

U4U4

Divide by 8Divide by 8

LVPECLLVPECL

U7U7

LVPECL to LVPECL to

CMOSCMOS

U6U6

LVPECL to LVPECL to

CMOSCMOS

Integrated Circuit Solution in one small packageIntegrated Circuit Solution in one small package

FanoutFanout DividersDividers DelayDelay Logic Logic TranslationTranslation

U2U2

Divide by 2Divide by 2

LVPECLLVPECL

5

Application – Wireless Transceiver Card

Critical Clock Functions on Transceiver Card:• clean-up jitter on user’s input reference• up-convert user reference frequency to highest frequency needed, usually driven by DAC clock requirements• generate multiple frequencies for Rx & Tx• provide low jitter clocks for data converters• generate mix of LVPECL, LVDS, CMOS clocks• adjust phase or delay between clock channels• offer isolation between clock channels

ADC

Transmitter/ReceiverClock Distribution IC

ADC

ADC

ADC

DDC orASIC

DAC

DUC orFPGA

DAC

User’sReference

Clock

Clock to A-D Converters

Clock to D-A Converters

Clock to Digital Chips

TRX Cards

6

Transceiver clock design using ADIsimCLK™

AD9510

19.20 MHz

DAC 1

DAC 2

AD6633DUC

LVPECL307.20 MHz

I-channel

Q-channel

CMOS76.80 MHz

AD9430

AD9445AD6636

DDC

LVPECL153.60 MHz

AD9215

614.40 MHz

Auxilarytemperature

measurementADC

To reconstructionfilters andmodulator

Receiver pathfrom Mixer

Carriers 1 & 2

OUT0

OUT7

OUT3

OUT4

OUT6

OUT2CMOS30.72 MHz OUT5

FPGADPD

AD9779

Observation pathdown-converted from

Power AmplifierCarriers 1 & 2

LVDS614.40 MHz

LVPECL102.40 MHz

LVDS102.40 MHz

Carrier 1I/Q

Carrier 2I/Q

RxBaseband

TxBaseband

Real

Imaginary

OUT1LVEPCL

19.20 MHz

Carrier 1I/Q

Carrier 2I/Q

7

A Clock Distribution Device with integrated PLL

LF

VCO

8

ADC Output clocked by AD9510

AD9510

19.20 MHz

DAC 1

DAC 2

AD6633DUC

LVPECL307.20 MHz

I-channel

Q-channel

CMOS76.80 MHz

AD9430

AD9445AD6636

DDC

LVPECL153.60 MHz

AD9215

614.40 MHz

Auxilarytemperature

measurementADC

To reconstructionfilters andmodulator

Receiver pathfrom Mixer

Carriers 1 & 2

OUT0

OUT7

OUT3

OUT4

OUT6

OUT2CMOS30.72 MHz OUT5

FPGADPD

AD9779

Observation pathdown-converted from

Power AmplifierCarriers 1 & 2

LVDS614.40 MHz

LVPECL102.40 MHz

LVDS102.40 MHz

Carrier 1I/Q

Carrier 2I/Q

RxBaseband

TxBaseband

Real

Imaginary

OUT1LVEPCL

19.20 MHz

Carrier 1I/Q

Carrier 2I/Q

1M 10M 100M 1GIF Frequency (Hz)

50

60

70

80

90

100

110

120

SN

R (

dB

)

SNR from Jitter

9

DAC Output clocked by AD9510

AD9510

19.20 MHz

DAC 1

DAC 2

AD6633DUC

LVPECL307.20 MHz

I-channel

Q-channel

CMOS76.80 MHz

AD9430

AD9445AD6636

DDC

LVPECL153.60 MHz

AD9215

614.40 MHz

Auxilarytemperature

measurementADC

To reconstructionfilters andmodulator

Receiver pathfrom Mixer

Carriers 1 & 2

OUT0

OUT7

OUT3

OUT4

OUT6

OUT2CMOS30.72 MHz OUT5

FPGADPD

AD9779

Observation pathdown-converted from

Power AmplifierCarriers 1 & 2

LVDS614.40 MHz

LVPECL102.40 MHz

LVDS102.40 MHz

Carrier 1I/Q

Carrier 2I/Q

RxBaseband

TxBaseband

Real

Imaginary

OUT1LVEPCL

19.20 MHz

Carrier 1I/Q

Carrier 2I/Q

10

ADIsimCLK™

ADIsimCLK is a powerful and flexible tool. It can help a user design high performance clocking systems using low-jitter clock chips.

ADIsimCLK phase noise simulations match the product information sheet typical values within ~2 dB.

Timing simulations align well with product information sheet typical values.

11

Select the ADI clock chip: AD9510

specs

ClockDevice

see product informationsheet

12

Select the configuration:Use integrated PLLDefault Configuration Use integrated PLL

Use external filter

Use clock

distribution

circuit only

13

VCO Selection:

VCO

librarysee productinformationsheet

14

PLL Loop Filter Selection:

Passive and active filters

Loop bandwidth and phase margin

15

Clock Distribution Configuration:Enable Outputs

Eight clock

outputs Configuration

per output

16

Clock Distribution Configuration:Configure Output

Integration

Interval

Divider value

Output Freq.

17

Results Page: OUT2 (LVPECL)

18

Another Design Example: Clock Distribution circuit only

19

ADIsimCLK versus Lab measurements

101

102

103

104

105

106

107

-165

-160

-155

-150

-145

-140

-135

-130OUT3 Phase Noise (LVPECL 61.44 MHz)

Frequency Offset (Hz)

Pha

se N

oise

Den

sity

(dB

c/H

z)

AD9510 Datasheet

ADIsimCLK

100

102

104

106

108

-160

-155

-150

-145

-140

-135

-130

-125

-120

-115OUT5 Phase Noise (LVDS, 122.88 MHz)

Frequency Offset (Hz)

Pha

se N

oise

Den

sity

(dB

c/H

z)

AD9510 Datasheet

ADIsimCLK

20

In summary we discussed

A Clock Design Strategy for a WCDMA Transceiver System

ADIsimCLKTM: A Clock generation and distribution simulator

Download this free tool at Download this free tool at www.analog.com/ADIsimCLK

Thank you!

21

PLL Frequency Set-up:PLL

Frequency

PFD

Frequency

22

Input Clock Selection:

Choose an input

Reference

frequency.

23

Information on the PLL: Frequency Domain

24

Phase noise and timing jitter at a divider’s input and output

102

103

104

105

106

107

108

-165

-160

-155

-150

-145

-140

-135

-130

-125

fm (Hz) frequency offset

Pha

se N

oise

Den

sity

(dB

c/H

z)

)( mfS

f1f2

Root mean square (rms) value of integrated phase noise (units in radians)

)2(2 )( outrmsjitter FTrms

)3(2

(sec))(outout

rmsjitter FT rmsrms

Transition of a divider’s output is re-sampled with a transition of its input, a jitter of value Tjitter occurring at the input will cause the same amount of jitter at the output.

)5(22,

NN

FTFT

ininjitteroutjitter

rms

rms

)4(N

FF inout

)6(222

(sec),

,

)(IN

i

IN

i

ormsjitter F

N

FN

FT rms

rms

rms

)1(1022

1

10

)(sin/)(

f

f

sidegleHzdBcfS m

rms

25

Get the results: schematic

26

Get the results: text report

27

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40Time (ns)

CLK2

FPGA

REF

ADC1

ADC2

ADC3

ASIC2

ASIC1

DAC

Timing Diagram

Get the results: timing

0.11 ns