the “ultimate” cmos device: a 2003 perspective · the “ultimate” cmos device: a 2003...
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The “Ultimate” CMOS Device: A 2003 Perspective
(Implications for Front-End Characterization and Metrology)
Howard R. Huff and Peter M. ZeitzoffInternational SEMATECH
Austin, TX 78741
2003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
22003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Agenda• Introduction
– MOSFET scaling drivers
• Front-end approaches and solutions
• Non-classical CMOS structures
• Summary / Trends
• Acknowledgements
32003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Simplified Cross-Section of MOSFET Transistor Structure
Upper interfacial region
Bulk high-k film
Lower interfacial region
Gate electrode, poly
Si Substrate (or SOI with Si
thickness ≈1/3 Lg)
Source Drain
Spacer
High-k Gate Dielectric Stack
Lg
Modified from P.M. Zeitzoff, R.W. Murto and H.R. Huff, Solid State Technology, July 2002
42003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Integrated Circuit Historical Scaling Trends
• 4K DRAM (1974)• SiO2 thickness ≈ 75-100 nm • Channel physical length (Lg) ≈ 7500 nm• Junction depth ≈ several µm
• Power supply = 5 V
• High-performance MPU (2003) - ITRS: 100 nm technology generation
• SiO2 equivalent oxide thickness (EOT) ≈ 1.1 - 1.6 nm • Channel physical length (Lg) ≈ 45 nm• Extension junction depth ≈ 25 nm
• Power supply = 1 V
52003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
• Learning curve (Haggerty)– Market elasticity (1960’s …)
• Moore & device scaling (Dennard –1968 -1T/1C DRAM cell) – Moore’s Law
• Number of transistors per chip doubles every year (1965) – Technology: Feature reduction – Design: Reduction in number of transistors per memory cell
from 6 (SRAM) to 1.5 (DRAM)• Number of transistors per chip doubles every two years (1975)
– Technology: Feature reduction– Design: No more reduction in transistors per memory cell
possible. Benefits derived only from improvements in layout• Industrial concern in mid ’90s as regards fab economic
constraints might reduce return on capital investment• Int’l Technology Roadmap for Semiconductors (ITRS)
– Focus to ensure Moore’s law by realizing the roadmap– Expansion of economy (GWP) - market elasticity (2000’s) -
accommodates IC CAGR
Pervasiveness of Microelectronics Revolution
62003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Introduction• Moore’s law and scaling – lower cost per function
– Lower power dissipation per function– Increased speed (intrinsic transistor gate delay)– Increased transistor and function density
• MOSFET scaling: processes/structures/tools – Meet both increased Ion and low Ioff (Ileak) metrics – Reduce Igate for ≤ 1.5 nm gate dielectric– Fabrication / control for abrupt, shallow, low sheet
resistance S/D extensions– Control short channel effects (SCE) ….
• Potential solutions & approaches:– Material and processes (front end): high-k gate
dielectric, metal gate electrodes, elevated source / drain– Structural configurations: non-classical CMOS devices
• Fully depleted, multi-gate SOI structures• Challenge of uniformity control in scaling body thickness and
width in fully depleted SOI with decreasing Lg
72003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
2001 ITRS Projections of EOT for High-Performance Logic and Low Standby-Power
EOT vs. Calendar Year
0.00
0.50
1.00
1.50
2.00
2.50
3.00
2001 2003 2005 2007 2009 2011 2013 2015
Calendar Year
EOT
(nm
)
EOT, High-Perf.EOT, LSTP
1 molecular layer of oxide
82003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
2001 vs. 1999 ITRS Projections of Physical Gate Length (Lg): High Performance Logic
0
10
20
30
40
50
60
70
80
90
100
2000 2002 2004 2006 2008 2010 2012 2014 2016
Year
L g (n
m)
Lg, ’01 ITRS
Lg, ’99 ITRS
92003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
ITRS Projections of Vdd and Vt Scaling
0.0
0.2
0.4
0.6
0.8
1.0
1.2
2001 2003 2005 2007 2009 2011 2013 2015
Year
Vdd
, Vt (
V)
Vdd-Low Power
Vdd-High Perf.
Vt-Low PowerVt-High Perf.
102003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
2001 ITRS Projected Scaling of 1/τ and Isd,leak for High Performance & Low Standby Power
(under revision)
100
1000
10000
2001 2003 2005 2007 2009 2011 2013 2015
Year
1/ (G
Hz)
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
Isd,leak (µA/µm)
Isd,leak, High Perf.
Isd,leak, Low Power Driver
1/τ, Low Power
1/τ , High Perf. Driver
112003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Idsat Trends
• Idsat trending slightly above 1 mA/µm for nMOS and approaching > 0.5 mA/µm for pMOS
• Concurrently, intrinsic transistor gate delay has trended below sub 1 psec for nMOS and slightly below 1 psec for pMOS as Lg ≤ about 20 nm
122003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Relative Chip Power Dissipation for High Performance MPU (Based on 2001 ITRS)
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
2001 2003 2005 2007 2009 2011 2013 2015
Year
Rel
ativ
e C
hip
Pow
er D
issi
patio
nN
orm
aliz
ed to
200
1
Allowable Total Chip Power Dissipation
Chip Dynamic Power Dissipation
Chip Static Power Dissipation
Assumptions:
•Only one type of (high Ion, high Ileak) transistor and no power reduction techniques
•Simple scaling
•Unrealistic scenario, only meant to clearly illustrate static power dissipation issues
132003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Agenda• Introduction
– MOSFET scaling drivers
• Front-end approaches and solutions
• Non-classical CMOS structures
• Summary / Trends
• Acknowledgements
142003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Difficult Transistor Scaling Issues• Previously discussed scaling results involve high-level,
idealized MOSFET physics– Assumption: highly scaled MOSFETs with required characteristics
can be successfully fabricated
• Lateral / vertical MOSFET dimensions (EOT, xj’s, spacer width, etc.) scaling down rapidly with Lg
• Increasing difficulty in meeting transistor requirements with scaling
– High gate leakage• Direct tunneling increases rapidly as Tox is reduced
– Poly depletion in gate electrode⇒ increased effective TEOT, reduced Ion
– Quantum effect on near-surface charge additionally increases TEOT
– High Rseries,s/d ⇒ reduces Ion in scaling source / drain extension and deep source / drain junctions
152003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Advanced CMOS Scaling Options
Device Type High-k MG DM SiGe Process R S/D SOI Permutations
Scaled Bulk CMOS X X X X X X 47
Partially Depleted X X X X X X Req'd 47
Fully Depleted X X X X X Req'd 31
Multi-Gate FET FinFET - 2 gates X X X X Req'd 15
MuG-FET >2 gates X X X X Req'd 15
Strained SiMetal Gate
Courtesy of Rinn Cleavelin and Rick Wise, Texas Instruments, Inc.
162003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
High-k Gate Dielectric Candidates (and Issues)• Modest k (<10)
• Al2O3• Negative charge, complicated defect structure
• Medium k (10-25)• Group IV Oxides - ZrO2, HfO• Low crystallization temperature, unless “doped”• Group III Oxides - Y2O3, La2O3,…
• Charge, epitaxial configurations• Silicates - (Zr, Hf, La, Y, ..) • SiO4
• Lower k if too diluted with SiO2• Aluminates - (Zr, Hf, La, Y, ..) • Al2O3
• Charge issue, complicated defect structure
• High k (≥ 25)• Ta2O5 , TiO2
• Low-barrier heightC. M. Osburn & H. R. Huff, Spring ECS Meeting, 2002, abst. #366
172003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
High-K Issues• Process integration
– Thermal stability of high-k material• Retain high-k performance with planar CMOS flow (S/D anneal
temperature, ambient, oxygen partial pressure, etc.,) – “Replacement gate” flow useful to quickly assess materials
– Thermal, chemical compatibility with polysilicon• Boron penetration• Metal electrode may be required
– Interface with both Si substrate and gate electrode• Deposition / post process anneals modify interfacial SiO2 layer,
TEOT
• Interface properties: Dit, Nt, Qf, µ = µ(interfacial SiO2)• Leakage, reliability• Short channel effects (SCE)⇒ fringing field effects• New material: major challenge
182003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Process - Structure - Property Relation• Crystalline / polycrystalline
– Phase structure• Epitaxial alignment to substrate
– Stoichiometry– Bond coordination– Morphology– Interfacial microroughness
• Retention of amorphicity by doping
• Mixed oxide phase separation
• Spatial inhomogeneity / periodicity in energy gap(s)
192003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
MOCVD HfO2 CV Curve (EOT = 0.95 nm)
0
20
40
60
80
100
120
140
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6
Voltage [V]
Cap
acita
nce
[pF]
Corrected Freq DataCVC Model
CVC ModelEOT = 0.95
nmVfb = -0.239 V
Nsurf = 2.11E15
Area = 5.0E-5 cm2Frequency = 100 and 250 kHzGate Electrode : PVD TiN
Gate Leakage4.3 A/cm2 @ 1V10 A/cm2 @ Vfb+1
HfO2 @ 485CInterface: N2O at 750C
Avinash Agarwal et al., (Alternatives to SiO2 as Gate Dielectrics for Future Si-Based Microelectronics, 2001 MRS Workshop Series (2001) (reprinted with permission of the MRS Society)
202003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
MOCVD HfO2 TEM (EOT = 0.95 nm)(HfO2 on HF-last, N2O-750°C Pre-Deposition Anneal)
PVD TiN 450 Å
HfO2 21 Å Interfacial layer 12 Å
Silicon substrate
• Effective k for above dielectric stack ≈ 13.5• k for interfacial layer may be significantly greater than SiO2 indicating
reaction or intermixing of HfO2 film with interfacial SiO2• “High” surface roughness at HfO2 / TiN interface may contribute to high Jg
Avinash Agarwal et al., Alternatives to SiO2 as Gate Dielectrics for Future Si-Based Microelectronics, 2001 MRS Workshop Series (2001) (reprinted with permission of the MRS Society)
212003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
2001 ITRS Projections Versus Simulations of Direct Tunneling Gate Leakage Current Density for Low Standby Power Logic
(under revision)
1.E-071.E-061.E-051.E-041.E-031.E-021.E-01
1.E+001.E+011.E+02
2001 2003 2005 2007 2009 2011 2013 2015
Year
J gat
e (A
/cm
2 )
0
0.5
1
1.5
2
2.5
3T
ox (nm)
Simulated Jgate, oxynitride
Specified Jgate, ITRS
Tox
Beyond this point, oxynitride too leaky; high k needed
Implementation of high-k driven by low standby power logic in 2005Simulations by C. Osburn, NCSU and ITRS
222003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Polysilicon Limitations• Polysilicon depletion
– Increases effective “electrical” EOT ⇒ reduces Eox and hence inversion charge
– As EOT is scaled ⇒ poly doping must increase • Ge:Si facilitates increased B incorporation
• Boron penetration (PMOSFET) in thin oxides– Oxynitrides & reduction of (DT)0.5 effective now
• Compatibility with high-k• Gate resistance of thin gates (with silicide)
232003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Metal Gate Electrodes• Metal gate electrodes potential solution
when poly “runs out of steam”– Implement <≈ 65 nm technology node (2007)– No depletion, very low resistance gate, no
boron penetration, compatibility with high-k• Issues
– Different work functions for PMOS and NMOS⇒ 2 different metals required
• Process complexity, process integration• Utilize one metal: tune work function via N implant
(i.e., Mo)– Plasma etching / damage of metal electrodes– Compatibility with spacer and sidewall profile– New materials: major challenge
242003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
SC-1 SC-2 / HO / Poly-Si
0.0E+00
5.0E-07
1.0E-06
1.5E-06
2.0E-06
2.5E-06
-2 -1.5 -1 -0.5 0 0.5 1Voltage [V]
Cap
acita
nce
[F/c
m^2
]
Poly-Si Electrode ; +2V->-2VPoly-Si Electrode ; -2V->+2VPoly-Si Electrode ; CVC modelTaN/Al Electrode ; +2V->-2VTaN/Al Electrode ; -2V->+2VTaN/Al Electrode ; CVC model
Frequency = 100 kHz
EOT = 18.62 AVfb = -0.751 VRMS = 9.7 %poly Con.=1e20 /cm3
EOT = 15.3 AVfb = -0.471 VRMS = 1.7 %
ALD HfO2 / Poly-Si vs. HfO2 /TaN/Al
Bottom Interface
Top Interface
3 nm HfO2/poly- Si transistor ( Yudong Kim)
• EOT increase by poly-Si gate process comes from both top and bottom interfaces, former suppressed by metal electrode
• CV stretch-out becomes worse in HfO2 / poly stacks, suggesting degraded interface quality after thermal cycle process
252003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Source / Drain Extension Issues
• Increasingly abrupt, shallow, heavily doped profiles required for successively scaled technologies
–Needed for optimal devices, especially to control SCE
–Difficult ρs,ext-xj,ext tradeoffs, especially for PMOS (B) ⇒ difficult to control RS/D,series
262003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Source / Drain Extension Potential Solutions• Near-term
– Ultra-low energy implants (< 1 KeV, B)– Rapid Thermal Processing (RTP) and spike
anneal: reduces (DT)0.5 and thermally enhanced diffusion
• Role of residual Sii during “slow” cool-down– Increase dose as much as possible ⇒ reduced
Rseries,s/d
• Beyond 90 nm technology generation– Doped, selective epi– Co-implant– Laser thermal annealing, …
272003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Potential Front-end Solutions for Power Dissipation Problems, High-Performance Logic
• Increasingly common approach to concurrently meet chip power, performance and density requirements to place multiple transistor types on chip ⇒ multi-Vt, TEOT, Lg, Xj…
– Utilize high-performance, high-leakage transistors only in critical paths - lower leakage transistors elsewhere
– Improves flexibility for system-on-chip (SOC)
• Electrical or dynamically adjustable Vt devices (future possibility)
• Circuit and architectural techniques: pass gates, power down circuit blocks, etc.
282003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Agenda• Introduction
– MOSFET scaling drivers
• Front-end approaches and solutions
• Non-classical CMOS structures
• Summary / Trends
• Acknowledgements
292003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Device Metrics• Power
• Pdynamic = fclock Cload Vdd2 and Pstatic = NtrW Ileak Vdd
• Intrinsic transistor gate delay (speed)• τ = Cload Vdd / IDSAT
• Idsat (maximum saturated drain current)• Idsat = (W/2Lg) (3.9KoA) (TEOT,INV)-1 µeff (VG-VT)2 (long-channel, ideal)– W and Lg device width and physical gate length– TEOT,INV = equivalent oxide thickness in inversion
• TEOT = (khigh k / kSiO2) Tphys
– µeff = mobility, generally determined in long-channel device (gm)– VG-VT = gate overdrive, where VG is voltage applied to gate
(VG ⇒ Vdd) and VT is threshold voltage
• Transconductance– gm = (W/Lg) (3.9KoA) (TEOT,INV)-1 µeff Vdd (long-channel, ideal)– Sub-threshold swing ⇒ Inverse slope of ln ID versus VG
• Drain-induced-barrier-lowering (DIBL)
302003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Limits of Scaling Planar, Bulk MOSFETs• 65 nm technology generation (Lg = 25 nm, 2007) ⇒ beyond
– Increased difficulty meeting device metrics with classical planar, bulk CMOS (even with material and process solutions: high k, metal electrodes, elevated source/drain ….)
• Control of SCE • Impact of quantum effects • Dopant stochastic variations (number and spatial location in channel)• Need for enhanced mobility, Id,sat• Impact of high substrate doping• Control of series source / drain resistance (Rseries,s/d)• Other contributors
• Alternative structures (non-classical CMOS) may be required
– Band engineered transistors ⇒ improved transport/mobility– Ultra thin body SOI– Multi- gate SOI - Including FinFET and Vertical FETs
312003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Electrostatic Scaling - Channel Leakage (Ioff)
TunnelingBTB
E VB
E CB
EmissionThermionic
QMTunneling
DrainSourceLgate
Substrate
Gate
Source Drain
Gate Leakage
Channel Leakage
Sum = Ioff
Channel Leakage
Jim Hutchby
High Resolution TEM Showing 30 nm Channel Length
Polysilicon Gate
30 nm Channel Length78 columns of Si atoms
Source Drain
13 layers of Si atomsconsumedto create
3.5nm SiO2
4 nm
3.5nm SiO2
polysilcon gate
electronmean free path
two decadesin 10 nm
donor atom
acceptor atom
inversion charge
Courtesy of Yoshi Nishi / Dick Chapman
Mar 25, 2003 2003 International Conference on Characterization and Metrology for ULSI Technology
332003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Representative Theoretical and Universal Mobility Curve
µpk
µpk,univ
µhi
µhi,univ
µ eff
(cm
2 /v-s
ec)
Universal curve
Degraded high-k curve
Eeff (MV/cm)Epk EhiET
342003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Mobility Considerations• Theoretical
– Low electric field• Unscreened (by inversion layer free carriers) ionized dopant
scattering centers in silicon– High electric field
• Surface acoustic phonons• Surface microroughness
– H x L (where H is height of surface undulation and L is undulation correlation length)
• Remote scattering by high-k phonons (modulated by interfacial SiO2)
• Experimental adders (not presently theoretically modeled)– Interfacial and high k bulk traps – Crystalline inclusions in amorphous high k gate dielectric– N, Al and other elemental (interface) scatterers– Remote scattering due to gate electrode
• Universal curve ignores scattering from ionized dopants
352003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Band Engineered MOSFETs: Surface-channel Strained-Si MOSFET Structures
Graded Layer0.05
=x
Drain
p+
n- Si1-yGeyy=
y
n+ Si Substrate
n+poly
n Strained Si
SourceSiO
p- Si1-yGey Graded Layery=0.05
y=x
p+ Si Substrate
n+poly
p Strained Si
DrainSiO2
Gate
n+ n+
high mobilitychannels
p- Relaxed Si1-xGex
2
Gate
n- Relaxed Si1-xGex
Strained Si1-xGexp+
Source
+ Increased effective mobility, increased Ion- Difficult integration issues, manufacturability- Compatibility with ultra-thin body SOI- Cost
Judy Hoyt, MIT
362003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Electron Mobility Enhancement in Strained SiMOSFETs (Rim,et al., IEDM 1998)
Vertical Effective Field, Eeff (MV/cm)0.00 0.25 0.50 0.75 1.00 1.25
Effe
ctiv
e El
ectro
n M
obilit
y, µ
eff (
cm2 / V
sec
)
0
200
400
600
800Strained Si onrelaxed Si0.8Ge0.2
Unstrained Si controlUniversal Mobility
(S. Takagi et. al., TED '94)
Welser et. al., IEDM '94
this work
Room T
• Electron mobility enhancement of ~ 1.8X persists up to high Eeff (~ 1MV/cm)• Strained-Si allows “moving off” universal mobility curve
Judy Hoyt, MIT
372003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Strained Si:Ge
382003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Strained Si Device Structures
392003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Electron Transport in εMOS™
Unstrained
[001]
[010]
[100]
in-plane∆4 valleysperpendicular
∆2 valleys
BiaxialTension
Tensile strain splitsconduction band
degeneracy
• Reduced intervalley scattering• Light in-plane effective mass
[010]
[100]
[001]
Courtesy of Matt CurrieAmberWave Systems Corp.
402003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Hole Transport in εMOS™
E
kHeavy Hole
Light HoleSplit-Off
in-plane out-of-plane
Unstrained BiaxialTension
Tensile strain splitsvalence banddegeneracy
• Reduced intervalley scattering• Light in-plane effective mass
in-plane out-of-plane
Courtesy of Matt CurrieAmberWave Systems Corp.
412003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
εMOS™ Electronic Structure
Si substrate
Graded SiGe
Uniform SiGe layer
Strained Si channel
ECEV EF
Type II Band Offset Vt ShiftCourtesy of Matt CurrieAmberWave Systems Corp.
422003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Defect Control: SiGe Virtual Substrates
aSi
Threadingdislocation
aSiGe Misfit dislocationarray at eachinterface
Each layer relaxedto intermediatelattice constant
• Constant low strain rate• minimize dislocation nucleation
• Relaxation via existing defects• low threading dislocation density
Courtesy of Matt CurrieAmberWave Systems Corp.
432003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Systems Substrate Technology
• Underlying misfit dislocation array affects local epitaxial growth rates
• “Crosshatch” surface roughness can be problematic for device manufacturability– Photolithography– Optical metrology
Courtesy of Matt CurrieAmberWave Systems Corp.
442003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Substrate Technology
After CMP : <2 ÅRMS Roughness before CMP : 50-100 Å
Proprietary planarization & regrowth process is akey differentiator of AmberWave substrate technology
Courtesy of Matt CurrieAmberWave Systems Corp.
452003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Strained Silicon: XTEM
Relaxed SiGe
Si Substrate
Graded SiGe
Strained Si
Relaxed SiGe
• 20% SiGe virtual substrate• 175 Å strained Si
Well-controlled introduction of misfit dislocations resultsin a high quality relaxed SiGe substrate for strained Si
Courtesy of Matt CurrieAmberWave Systems Corp.
462003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Drain Current versus Source-Drain Voltage
15-20%self-heatingdegradation
K.A. Jenkins and K. Rim, Measurement of the Effect of Self-Heating in Strained-Silicon MOSFETs,Electron Dev. Lett., 23, 360-362 (2002) (© 2002, IEEE)
472003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Strained-Si PMOSFET on SiGe-on-Insulator
Strained SiRelaxedSi1-xGex
SiGe Buffer
Si Substrate
Gate
p+ p+
SiO2
S
G
D
Tensile Strain
Buried SiO2
T. Mizuno et al., IEDM, 934-936 (© 1999, IEEE)
482003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Strained-Si PMOSFET on SiGe-on-Insulator
Si0.9Ge0.1 (340 nm)
Buried-Oxide (100 nm)
Strained-Si (20 nm)
SiO2 (9 nm)
n+-Poly Gate(200 nm)
T. Mizuno et al., IEDM, 934-936 (© 1999, IEEE)
492003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Limits of Scaling Planar, Bulk MOSFETs• 65 nm technology generation (Lg = 25 nm, 2007) ⇒ beyond
– Increased difficulty meeting device metrics with classical planar, bulk CMOS (even with material and process solutions: high k, metal electrodes, elevated source/drain ….)
• Need for enhanced mobility, Id,sa t• Control of SCE • Impact of quantum effects • Dopant stochastic variations (number and spatial location in channel)• Impact of high substrate doping• Control of series source / drain resistance (Rseries,s/d)• Others
• Alternative device structures (non-classical CMOS) may be required
– Band engineered transistors ⇒ improved transport/mobility– Ultra thin body SOI– Multi- gate SOI - Including FinFET and Vertical FETs
502003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Transistor Structures
G
Planar Bulk Partially Depleted Fully DepletedSOI SOI
2. Mark Bohr, ECS Meeting PV 2001-2, Spring, 2001
+ Lower junction cap- SCE scaling difficult- High Rseries,s/d⇒raised S/D
- Sensitivity to Si thickness (very thin)
- Wafer cost/availability
G
Substrate
BOX
SD
SD
Substrate
Buried Oxide (BOX)
+ Lower junction cap+ F.B. performance
boost- F.B. history effect- SCE scaling difficult- Wafer cost/availability
SD
G
Substrate
Depletion Region
+ Wafer cost / availability- SCE scaling difficult- High doping effects and statistical variation
- Parasitic junction capacitance
References:1. P. Zeitzoff, J. Hutchby and H. Huff, Internat. Jour. High Speed Electronics & Systems
512003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Source Drain
Gate
Silicon wafer (back gate)
E-fieldlines
Short-channel MOSFET: DIBLShort-channel MOSFET: DIBL
or: Drain-Induced Barrier Loweringor: Drain-Induced Barrier Lowering
Electric field lines from the drain encroach on the channel region. Any increase of drain voltage decreases the threshold voltage (the “NPN” potential barrier between source and drain is lowered).
J-P Colinge, U.California., Davis
Electric field lines from drain encroach on channel region.
Any increase of drain voltage decreases threshold voltage(the “NPN” potential barrier between source and drain is lowered)
522003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Electrostatic Scaling - Channel Leakage (Ioff)
TunnelingBTB
E VB
E CB
EmissionThermionic
QMTunneling
DrainSourceLgate
Substrate
Gate
Source Drain
Gate Leakage
Channel Leakage
Sum = Ioff
Channel Leakage
Jim Hutchby
532003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
E-Field lines
S D
G
P+ P+
S D
G
P-Si
P+
P-Si
Ground-plane SOI MOSFETsJ-P Colinge, U.California., Davis
542003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
S D
G
S D
G
G
E-Field lines
Regular SOI MOSFETDouble-gate MOSFEJ-P Colinge, U.California., Davis
552003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Schematic Cross Section of Planar Bulk, UTB SOI and DG SOI MOSFET
Ultra-thin silicon film
Double-Gate SOI MOSFET
Si Substrate
BOX
Tsi
-++
-
Ultra-thin silicon film
Double-Gate SOI MOSFET
Si Substrate
BOX
Tsi
-++
-
Ultra-thin silicon film
Double-Gate SOI MOSFET
Si Substrate
BOX
Tsi
Ultra-thin silicon film
Double-Gate SOI MOSFET
Si Substrate
BOX
Tsi
-++
-
-++
-
Bulk MOSFET
+
+
+ +++-+-
--- -
-
Inversion Layer
Depletion Region
+
Bulk MOSFET
+
+
+ +++-+-
--- -
-
Inversion Layer
Depletion Region
+
Si Substrate
Ultra-Thin Body SOI
Ultra-thin silicon film
BOX
Tsi
S D+-
Si Substrate
Ultra-Thin Body SOI
Ultra-thin silicon film
BOX
Tsi
S D+ -+ -
-+
-+
562003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Ultra-Thin Body, Fully Depleted Single and Double-Gate Transistors: Pros and Deltas
Single Gate:
S D
G
Buried Oxide (BOX)
SUB
S D
Top
Bottom
SUB
+ Lower junction capacitance
+ Reduced channel doping for metal gate electrode, fully depleted
- SCE scaling difficult- Sensitivity to Si thickness- Wafer cost/availability
Ultra-thin Si body
Buried Oxide
Tbody
+ Enhanced scalability+ Near ideal subthreshold slope, S+ Reduced channel doping for metal
gate electrode, fully depleted+ Lower junction capacitance+ ~2x drive current- ~2x gate capacitance- Complex process - Wafer cost/availability- Most advanced, optimal device
structure, difficult to fabricate
Double Gate SOI:
Tbody
P. M. Zeitzoff, J. Hutchby and H.R. Huff M. Bohr, ECS Meeting PV 2001-2, Spring, ‘01
572003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
S
DG
S
DG
S
DG
1 2 3Buried Oxide
S
DG
S
DG
4 5Buried Oxide
“Multiple Gates”
1: Single gate 2: Double gate 3: Triple gate 4: Quadruple gate (GAA) 5: Π gate
J-P Colinge, U.California., Davis
582003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Simulation of Multiple-Gate SOI MOSFETs
Π Gate
IDo
2 ID
3iIDo
4 IDo
π IDo
ooo
o
1 Gate 2 Gates 3 Gates 4 GatesJ-P Colinge, U.California., Davis
592003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Double-Gate Transistor Structures
S DG
source
top gate
bottom gate drain
100 nmIBM ‘97
Double GateSOI
Simplified view ofFinFET
(one type of double-gate
MOSFET)
S G DS G D
Source Drain
Poly Gate
Fin
Source Drain
Poly Gate
Fin
Top View
SiO2
BOXBOX
GateGate
DrainDrainSourceSourceSiOSiO22 SiOSiO22
Schematic Cross-Section
Simplified view ofFinFET
(one type of double-gate
MOSFET)
S G DS G D
Source Drain
Poly Gate
Fin
Source Drain
Poly Gate
Fin
Top View
Simplified view ofFinFET
(one type of double--gate MOSFET)
S G DS G D
Source Drain
Poly Gate
Fin
Source Drain
Poly Gate
Fin
Top View
SiO2
BOXBOX
GateGate
DrainDrainSourceSourceSiOSiO22 SiOSiO22
Schematic Cross-Section
SiO2
BOXBOX
GateGate
DrainDrainSourceSourceSiOSiO22 SiOSiO22
Schematic Cross-Section
SiO2
BOXBOX
GateGate
DrainDrainSourceSourceSiOSiO22 SiOSiO22
Schematic Cross-Section
SiO2
BOXBOX
GateGate
DrainDrainSourceSourceSiOSiO22 SiOSiO22
SiO2
BOXBOX
GateGate
DrainDrainSourceSourceSiOSiO22 SiOSiO22
Schematic Cross-Section
T-J. King and C. Hu, UC/Berkeley and Mark Bohr, ECS Meeting PV 2001-2, Spring, 2001Key advantage: relatively
conventional processing, largely compatible with current techniques
FinFET
602003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Tri-gate Relaxes TSi Requirement of Single-gate
Courtesy of Robert Chau et al., ISSDM, 2002
612003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Tri-gate Relaxes WSi Requirement of Double-gate
Courtesy of Robert Chau et al., ISSDM, 2002
622003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
PI-Gate / OMEGA Gate Structure
Buried oxide
SOI island
Silicon substrate
Buried oxide
SOI island
Silicon substrate
Buried oxide
Silicon substrate
Gate material
α
β1 Π
Buried oxide
Silicon substrate
Gate material
Buried oxide
SOI island
Silicon substrate
β2 Ω
J-P Colinge, U.California., Davis
632003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
TSMC's Ω-gate (IEDM'02)
Fu-Liang Yang et al., IEDM, 255-258 (2002) (© 2002, IEEE)
642003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Quantum Wire MOSFET(UCL SOI Conf., 1995)
J-P Colinge, U.California., Davis
652003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003J-P Colinge, U.California., Davis
662003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
The Ideal MOS Transistor
672003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
One Can Utilize Multiple Fins to Enhance Transistor Total Drive Current
Source Drain
Poly Gate
Fin
Source Drain
Poly Gate
Fin
Source Drain
Poly Gate
Fin
Source Drain
Poly Gate
Fin
T-J. King and C. Hu, UC/Berkeley and Mark Bohr, ECS Meeting PV 2001-2, Spring, 2001
682003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Other 3-D Transistor Structures
Agere ‘02c-Sibody
source
drain
PSG
gate gate PSG
HfO2
100 nm
S
G
D
S
G
D
Vertical FET(one type of double-gate
MOSFET)
REF: Mark Bohr, ECS Meeting PV 2001-2, Spring, 2001
Silicon on Nothing (SON):
localized buried oxide
(BOX)
S. Monfray et al., IEDM, 645-648 (2001) (© 2002, IEEE)
STM ’01
692003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Other 3-D Transistor Structures (con’t)Agere ’02
7 Å
under- layer
nitride
45 Å
HfO2
gate
poly-Si gate
nitride
nitride
c-Si body
HfO2
50 nm
Jack Hergenrother et. al., 50 nm Vertical Replacement-Gate (VRG) nMOSFETs with ALD HfO2 Gate Dielectrics, Semiconductor Silicon/2002, ECS PV 2002-2, 929-942 (2002)
Reproduced by permission of The Electrochemical Society, Inc.
702003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Agenda• Introduction
– MOSFET scaling drivers
• Front-end approaches and solutions
• Non-classical CMOS structures
• Summary / Trends
• Acknowledgements
712003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
2001 ITRS Key MOSFET Scaling Results• High-performance logic
– Average 17%/yr improvement in 1/τ attained– Isd,leak very high, particularly for 2007 and beyond
• Chip static power dissipation scaling an issue
• Assumption: Igate ≤ Isd,leak ⇒ unacceptably large Igateunder revision
• Low standby power logic– Very low Isd,leak target met
• Igate ≤ Isd,leak ⇒ Igate low, but difficult to achieve – 1/τ scales considerably slower (14%) than high-
performance MPU
• ITRS MOSFET targets are chosen to aggressively drive technology scaling
722003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Summary• MOSFET device scaling “raw material” for meeting projected overall
chip power, performance, and density requirements– Goals/requirements/tradeoffs jointly established between
designers and technologists– Considerable design innovation and focus required, even with
aggressive technology scaling• Scaling goals vary for different applications
– High-performance logic driven by transistor speed requirements• Result: high speed, but high leakage, static power dissipation issues
– Low standby power logic driven by transistor leakage requirements• Result: lower speed than high-performance logic
• Material and process potential solutions include high-k gate dielectric, metal gate electrodes, elevated source / drain, spike annealing, and eventually, novel S/D annealing and doping
– High-k needed first for low standby power (mobile) chips in ~ 2005• Structural configurations: non-classical CMOS• Material, process and structural solutions pursued in parallel and may
be combined in “ultimate,” end-of-roadmap device– Lg ≤ 10 nm MOSFETs anticipated end of ITRS in 2016 (if not earlier)
• Lg~10 – 20 nm experimental devices reported in literature and simulations indicate 5 nm or less feasible
732003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Summary• Gate stack is a multi-element arrayed structure wherein
high-k and metal electrodes must be successfully integrated into planar, scaled CMOS processes
– Extremely stringent material, electrical and integration challenges
• Impact of surface clean and wafer pre-conditioning prior to high-k deposition as well as post-deposition anneal (temperature, time and partial pressure of oxygen in ambient) significantly impacts EOT and leakage
• Control of electrical charges incorporated at interfaces and bulk high-k during high-k deposition /anneals critical
• Mobility complicated compilation of various contributors
• Interactive effects within Gate Stack process modules and IC fabrication process requires utmost attention to achieve requisite IC performance characteristics
742003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Non-Classical CMOS Summary• Planar bulk CMOS < Lg ≈ 25 nm scaling difficult
– Enhanced mobility required• Strained Si on relaxed or strained Si:Ge may be potential solution
• Key issues:– Effectiveness of planar bulk CMOS scaling regime
• Working devices with Lg ≈ 10-20 nm recently noted– Effective non-planar solutions must rectify very difficult
process issues for multi-gate, FD ultra-thin SOI– Control short-channel effects by gate shielding – Lg ≈ 5 nm may be possible with FD ultra-thin body SOI without
excessive band-to-band tunneling • Ultimate MOSFET (Lg < 10 nm) may be lightly doped
channel, ultra-thin body SOI (multiple fins) with high-k gate dielectric, multi-gate metal electrodes (mid-gap work function), elevated source / drain, strained Si, etc. ⇒“ultimate” CMOS device
752003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Evolving Trends of Alternative Novel Device Structures Beyond CMOS
• Requirements– Capability to be integrated with Si-CMOS– Room-temperature operation– Capability for SOC, including gigabytes of memory storage– Portable capability, with opportunity for large-scale market
• Examples (non-ranked)– Opto-electronic system (with multi-layered epitaxial structures)– Spintronics– Self-assembled nanostructures (including molecular structures)– Nanowire arrays– Microclusters/quantum dots in “SiO2” (in higher-dimensional matrix)– Carbon nanotubes– Cellular automata– Fullerenes– Single-electron structures– Optical computers– DNA computers– Quantum computers
762003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
CMOL CONCEPT
molecular single-electron latching switch
longer bridge as an insulator/capacitor
diimide acceptor as an island
thiol group as an alligator clip
single-electron transistor
single-electron trap
S
S
N
NO
O
O
O
O
O
S
N
N
O O
O O
N
N
O O
O O
O
O
S
OPE bridge as a tunnel junction
Si substrate
SOI MOSFET
CMOS wiring
CMOSplug
SiO2 insulation
CMOS--to-MOL
plug
gold nanowires
gate
Possible density: 3×1012 functions per cm2
K. Likharev and A. Mayr, 2002(see http://rsfq1.physics.sunysb.edu/~likharev/nano/GigaNano010603.pdf)
772003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
MOSFETS Below 10 nm: Quantum Theory Konstantin K. Likharev – NanoMES 2003* – Tempe, AZ
• “Room-temperature devices with gate length (Lg) as short as 5 nm still have high transconductance and relatively small DIBL effects and thus may be suitable for nearly all digital applications. Moreover, transistors with Lg as small as 2.5 nm may still feature voltage gain above unity and hence may be the basis for digital electronics
• However, all characteristics of such devices are extremely sensitive to very small variations of their geometrical parameters (Lg, TSi and TEOT) as well as single charged impurities inside (or in the immediate vicinity of the channel)
• As a result of this sensitivity, fabrication of sub-10 nm devices with acceptable yield will require extremely tight specifications, far exceeding recent ITRS projections for the year 2016”
* To be published in Physica E (2003)
782003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Jim Hutchby
792003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Microelectronics Revolution
• Gordon Moore (a)– “But then you see the numbers or hear your
company’s name on the evening news … and you are once again reminded that this is no longer just an industry, but an economic and cultural phenomenon, a crucial force at the heart of the modern world.”
• Gordon Moore (b)– “No exponential is forever: but “forever” can
be delayed!”(a) Beyond Imagination:Commemorating 25 Years, SIA (2002) [Introduction by Gordon Moore] (b) ISSCC 2003 / Session 1/ Plenary 1.1 (2003)
802003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Gordon Moore
812003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Agenda• Introduction
– MOSFET scaling drivers
• Front-end approaches and solutions
• Non-classical CMOS structures
• Summary / Trends
• Acknowledgements
822003 International Conference on Characterization and Metrology for ULSI TechnologyMar 25, 2003
Acknowledgements– Mark Bohr– Douglas Buchanan– Dick Chapman– Robert Chau– Jim Chung– Rinn Cleavelin– J-P Colinge– Matt Currie– Paolo Gargini– Evgeni Gusev– Jack Hergenrother– Judy Hoyt– Chenming Hu– Jim Hutchby– T- J. King
– Konstantin Likharev– Gerry Lucovsky– Veena Misra– T. Mizuno– S. Monfray– Patricia Mooney– Yoshi Nishi– Carl Osburn– Gregory Parsons– Darrell Schlom– Thomas Skotnicki– Bob Wallace– Glen Wilk– Rick Wise– Fu-Liang Yang
Assistance of IC Fab line and FEP team at International SEMATECH and our colleagues at the FEP- RC, IMEC, ASM and AMAT