the srod module for the atlas tile calorimeter phase-2...
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The sROD Module for the ATLAS Tile Calorimeter
Phase-2 Upgrade Demonstrator
The ATLAS Tile Calorimeter
Introduction
The LHC is a particle accelerator designed to handle
proton-proton collisions at up to a center of mass energy
of 14 TeV (center of mass). ATLAS is one of its main
experiments. Being a general purpose particle detector, it
is composed of various sub-systems: the inner detector for
tracking the particles, the calorimeters for measuring their
energy and position and the muon spectrometer for the
detection of muons.
TileCal is the hadronic barrel calorimeter for ATLAS and it
provides accurate energy and position measurements for,
hadrons, jets, taus and missing transverse energy.
ATLAS TDAQ
The Trigger and Data Acquisition System (TDAQ)
manages the hardware resources for the read-out of the
detector. It defines three domains in the dataflow, called
levels of trigger, which establish different methods and
rates for the selection of events,
Front-end electronics
TileCal is built in steel as absorber medium and
scintillating plastic tiles as active material. The tiles are
arranged in cells that produce light in the interaction with
the particles. The light produced in a cell is converted to
an electrical pulse in a photomultiplier tube (PMT), and
digitized on a subsequent step, forming a TileCal read-out
channel.
Tilecal is divided in four cylindrical partitions: EBA, LBA,
LBC, EBC which are azimuthally segmented in 64
instrumented modules each hosting up to 48 PMTs. The
complete read-out of the calorimeter is formed by 9856
channels which are serialized and transmitted at 640
Mbps to the back-end electronics located in a separated
cavern.
Back-end electronics
The Read-Out Driver (ROD) plays a key role in the data
acquisition chain. It is responsible of the deployment of
first processing algorithms to data in real time (online
algorithms). It receives the data from the front-end links
deserializes and routes them to its two Processing Unit
(PUs) daughter-cards that are populated with commercial
DSPs. These DSPs compute the reconstruction of the
energy and the time as well as a quality factor, with a
maximum latency defined by the Level 1 trigger rate (100
KHz). The Output Controller FPGAs receive the
processed events and packages them into ROD data
fragment format. Finally, the resulting data fragments are
serialized and transmitted to the Read-Out Buffers,
located on the Level 2 trigger.
F. Carrió1, A. Ferrer1,V. Castillo1, Y. Hernández1, E. Higón1, L. Fiorini1, B. Mellado2, L. March1, P. Moreno2, R. Reed2, C. Solans3 A. Valero1, J. A. Valls1
On behalf of the Tile Calorimeter System
1- IFIC (Spain) , 2- University of the Witwatersrand (South Africa), 3 - CERN (Switzerland)
Poster presented on the TWEPP 2013 Topical Workshop on Electronics for Particle Physics
TileCal Upgrade Demonstrator ProgramTileCal Phase II Upgrade
In order to cope with the luminosity increase by a factor of ten
on the LHC at 2022, an upgrade is foreseen for the most part
of the readout electronics. The new architecture will provide:
• Full digital L1 trigger
• Complete detector data sent to back-end every bunch
crossing (25 ns)
• Redundant data links to back-end
• Redundant power supplies
• Higher radiation tolerance
A remarkable difference resides in the fact that the L1 trigger
decision will be made upon data stored in the ROD. This
change on the L1 boundary, together with the added
redundancy on the data links, imply a considerable increase
of the detector output bandwidth.
sROD Demosntrator
TileCal Upgrade Electronics Demonstrator
In order to test the future architecture, a demonstrator
program is being developed for its installation at the end of
2013 shutdown. It comprises all the front-end and back-end
electronics needed for the readout of 1 module. Electronics
within this module will be hybrid in order to maintain
compatibility with the present system, and will provide both
analog and digital trigger signals.
The sROD demonstrator requires:
• Reception of data from 48 PMTs@40 MHz
• Pipeline and de-randomizer memories
• Reconstruction algorithms
• Data transmission to ROS
• Control and configuration of front-end electronics
• Trigger preprocessing and transmission for L1 Calo
sROD Demonstrator Board Design
The LHC
ATLAS
The ATLAS Trigger System
Present architecture
DAQ
Future architecture
Virtex7XC7VX485T-2FFG1558
Kintex7XC7K420T-2FFG901
Parallel Flash
DDR3 512 MB
Power Modules
Front-End LinksQSFP+
QSFP+
QSFP+
QSFP+
ETH
USB-UART
MMC
SFP+
CLOCKUNIT
Input
MiniPOD
Output
MiniPOD
AM
C co
nn
ector
Parallel Flash
DDR3 512 MB
IPMI JTAG
12V
1.0 V
1.5 V
1.8 V
1.2 V
3.3 V
sROD block diagram
Optical Connectors
Four QSFP connectors, an input and an
output MiniPOD and an extra SFP+
provide the board with a total input and
output bandwidth of 290 Gbps.
FPGAs
Present Upgrade
Total BW 165 Gbps 20 Tbps
Nb fibers 256 4096
Fiber BW 640 10 Gbps
ATCA framework
The sROD demo board will be working in an ATCA
equipment framework. The Chassis is a SYS6000
platform, with six horizontal slots and a dual star
topology backplane. The data transfers between
blades through the backplane are managed by a shelf
manager integrated in a switch. The 4500 is an ATCA
computer module allows the user direct access to the
backplane. Besides, there is a ATCA-1200 carrier,
which provides mechanical support for AMC
modules. It also provides power distribution and high-
speed communication to the RTM, to the backplane
and between AMCs.
Mechanical design
The sROD demo board is AMC
standard compliant with a double mid-
size AMC form factor (180.6 mm x
148.5 mm). It can be plugged as a
mezzanine into an ATCA carrier or
directly to the back plane in a uTCA
crate. An integrated edge connector
has been chosen to achieve a more
compact design.
Double-mid size AMC
Layout and PCB Design
This is a real size picture of the
layout of the PCB. The design is
now in routing process. The sROD
includes around 1200 components,
requiring high integration levels. The
critical areas are the FMC HPC
connector with 400 pins and the two
high density package FPGAs: the
Kintex-7 with 900 pins and the Virtex-
7 with 1556 pins. Also on the power
section six 144 LGA packages are
used for the DC/DC μModule
regulators.
The stack-up has been carefully
selected to fulfill the high-speed
design requirements. A special
dielectric (NELCO 4000-13 SI) has
been chosen for optimal values of
dielectric constant (3.2 @ 10 GHz)
and dissipation factor (0.008 @ 10
GHz). Using 8 layers for power and
grounding and 6 layers for signals,
the PCB has a total thickness of 1.6
mm, making it this way AMC
standard compliant.
IPMI Tools and TileIpmiGUI
The IPMI is a microcontroller board that
establishes connection between the
ATCA modules and the shelf manager for
providing basic services as power and
monitoring functionalities. The OpenIpmi
is an open-source library that interfaces
software to the IPMI. A specific graphical
interface for the demonstrator has been
designed based on OpenIpmi and Qt.
tools
IPMI
module
Virtex-7 Kintex-7
LEs 485 k 480 k
MGTs .. 48 24
DSPs 2800 1920
BRAM 37,080 kb 34,380 kb
Quad-QSFP caseMiniPODs
ROD board
Mezzanine PU
ATCA Carrier
ATCA System
sROD board layout sROD stack-up