THE MEMORY SYSTEM

&

INTERCONNECTION STRUCTURE

OBJECTIVES• Define Memory hierarchy and its

characteristics

• Define various types of memories

• Define the characteristics of an Interconnection Structure

CHARACTERISTICS OF MEMORY SYSTEMS

• MEMORY CAPACITY

• WORD SIZE

• NUMBER OF WORDS

UNIT OF TRANSFER

• WORD

• BLOCK

ACCESS METHOD

• SEQUENTIAL ACCESS

• DIRECT ACCESS

• RANDOM ACCESS

• ASSOCIATIVE ACCESS

MEMORY ACCESS TIME

• For Random Access:

Time taken to read-write a location

• For non-random Access:

Time taken to position read-write mechanism on the desired location

PHYSICAL CHARACTERISTICS

• VOLATILE/NON-VOLATILE

• ERASABLE/NON-ERASABLE (ROMs)

THE MEMORY HIERARCHY

Tradeoff among the memory characteristics:

• Cost

• Capacity

• Access Time:

Time taken to Read/Write a location in the memory

RELATIONSHIPS AMONG THE THREE TERMS

ACCESS TIME COSTLow High

CAPACITY COSTHigher Smaller Cost per bit

CAPACITY ACCESS TIMEHigher Higher

Designers want large-capacity but

low access time

Employ Memory Hierarchy

REGISTERS

CACHE

MAIN MEMORY

DISK CACHE

MAGNETIC DISK

MAGNETIC TAPE/OPTICAL DISK

As you go down the hierarchy:

• It decreases cost/bit

• Increases capacity

• Increases access time

• Decreases frequency of access of memory by the CPU

LOCALITY OF REFERENCE

During the course of execution of a program, memory references by the processor, for both instructions and data tend to cluster.

Main reasons for clustering:• Iterative loop in programs

• Subroutines/function in programs

• use of data structures such as arrays in data

TYPES OF SEMICONDUCTOR MEMORY

• RANDOM ACCESS MEMORY (RAM)

• READ ONLY MEMORY (ROM)

SEMICONDUCTOR MEMORY TYPESMEMORY TYPE

CATEGORY ERASURE WRITE MECHANISM

VOLATILITY

Random-access memory (RAM)

Read-Write memory

Electrically, byte-level

Electrically Volatile

Read-only memory (ROM)

Masks

Programmable ROM (PROM)

Read-only memory

Not possible

Erasable PROM (EPROM)

UV light, chip-level

Flash Memory

Electrically, block-level

Electrically Erasable PROM (EEPROM)

Read-mostly memory Electrically

byte-level

Electrically

Nonvolatile

RAM TECHNOLOGIES

• DYNAMIC RAM (DRAM):– Cells store data as charge capacitor– Require periodic refreshing

• STATIC RAM (SRAM):– Traditional flip-flop– Logic-gate configurations– No refreshing

DRAM Vs SRAM

• DRAM is more dense, less expensive but require circuitary for refreshing.

• DRAMs are slower than SRAMs.

• For large memory DRAMs are preferred.

• For small faster memories SRAMs are used.

CACHE MEMORY

• Is built from SRAM technologies

• Level 1 Cache (L1 Cache) is built into microprocessor

• Level 2 Cache is normally external to the microprocessor

DISK CACHE

Used to speedup access to data on a disk.

• A portion of RAM (called soft disk cache) or

• A RAM as a part of Hard disk (hard disk Cache) (More expensive).

INTERCONNECTION STRUCTURES

• Collection of paths connecting various modules such as memory, Input/Output & CPU.

• Most common interconnection structure is BUS and Multiple bus structure.

BUS INTERCONNECTION

• A shared transmission media

• Only one module transmits at a time, thus, requires arbitration

• Multiple lines/pathways each transmitting one bit.

• A bus that connects CPU, memory, I/O is called System bus.

SYSTEM BUS

• Typically 50-100 separate lines.

• Each line may be assigned a particular meaning.

• Three functional groups of bus lines:– Data lines– Address lines– Control lines

• Few lines are also used for Power distribution.

• Bus may be dedicated or Multiplexed.

A TRADITIONAL BUS BASED SYSTEM

MAIN MEMORY PROCESSOR I/O SYSTEM

DATA

ADDRESS

CONTROL

CONTROL BUS

SUMMARY

We Have Discussed About:

• The Memory Hierarchy

• The Characteristics Terms of Memory

• DRAM & SRAM

• ROMs & its Variants

• Bus Interconnections

• System Bus