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The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci.

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Page 1: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

The Architecture of the ENIACThe Electronic Numerical Integrator and Computer

Brian J. ShelburneDept. of Math and Comp Sci.

Page 2: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

Computer architecture deals with the functional behavior of a computer system as viewed by a programmer.

OverviewBackground and Origin of Project PXThe Decade CounterRepresenting Numbers on the ENIACUnits of the ENIACThe AccumulatorsA Sample Calculation

Sequencing Accumulators The Master Programmer

Epilogue

Page 3: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

Background and Origins of Project PX

Page 4: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

The ENIAC (Moore School of Electrical Engineering at UPenn) was funded by the US Army during WWII to compute ballistic tables.

Page 5: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

Vannevar Bush’s Differential Analyzer

http://www.library.upenn.edu/exhibits/rbm/mauchly/img/5women.jpg

The Moore School had one of the existing three Differential Analyzers , the other two being at MIT and the Army’s BRL at Aberdeen MD

Page 6: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

The People

John W. Mauchly 1907 – 1980

J. Presper Eckert Jr. 1919 - 1995

Page 7: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

The People

H.H. Goldstine 1913 - 2004

Page 8: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

http://coolphotobench.com/images/Cars/adele-goldstine.jpg

Project PX – the “ENIAC” - proposed 1942, contract signed 1943, delivered 1946

Page 9: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

"ENIAC OFFICIALS" From left to right: J. Presper Eckert, Jr., Chief Engineer; Professor J. G. Brainerd, Supervisor; Sam Feltman, Chief Engineer for Ballistics, Ordnance Department; Captain H. H. Goldstine, Liaison Officer; Dr. J. W. Mauchly, Consulting Engineer; Dean Harold Pender, Moore School of Electrical Engineering, University of Pennsylvania; General G. M. Barnes, Chief of the Ordnance Research and Development Service; Colonel Paul N. Gillon, Chief, Research Branch of the Army Ordnance Research and Development Service.

http://explorepahistory.com/kora/files/1/2/1-2-1573-25-ExplorePAHistory-a0l4o2-a_349.jpg

Page 10: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

Project PX: The ENIAC Project: 1943-1946

30 units (40 panels) including20 Accumulators capable of storing a signed 10

digit decimal number (200 digits of storage)Capable of 5000 additions/second (200 msec)~18,000 vacuum tubes30 tons - 1800 ft2 - 150 KW powerCost ~$500,000.00

Page 11: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

Functional Diagram of the ENIAC

cc

cM

M

• Accumulator× Multiplier÷ Divider/Square Rooterc Constant TransmitterM Master Programmer

Page 12: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

The Decade Counter:the basic computational unit

Page 13: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

Representing Numbers

A digit was stored in a 10 stage ring counter circuit (10 two-tube flip-flops) – a.k.a. “decade counter”. only one of the ten flip-flops being in an abnormal state (thus indicating the digit value)

If the decade counter received a “pulse” the position of the abnormal state advanced to the next position mod 10 (with a carry out pulse!)

Ten decade counters plus an 11th two-state counter for the sign allowed a signed 10 digit decimal number to be stored per accumulator.

Page 14: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

The Decade Counter: 7 + 4 = 1 plus carry

…0

1

2

3

45

6

7

8

90

1

2

3

45

6

7

8

9

4

Page 15: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

Representing Numbers on the ENIAC – Doing Arithmetic

Page 16: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

Ten Digit 10’s Complement Notation

P 9 999 999 999 <- positive integer a sign plus ten digits

M 9 999 999 999 <- negative integer

In 10’s Comp. Not. the sign digit is given a value P = 0 , M = -1010

So -1 is represented by M 9 999 999 999, -2 by M 9 999 999 998 etc.

Page 17: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

Simple Example: Three Digit 10’s Complement Notation

Sign “digit” has value: P = 0; M = -1 but it’s “position” has weight is 1000

Therefore - 124 is represented by M 876Ck: -1000 + 876 = -124Addition “works” with 10’s Comp. Notation 257 → P 257 → 0257 - 124 → M 876 → 1876 133 P 133 0133

throw out carry outs

Page 18: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

It’s easy to negate numbers – form the 9’s complement of each digit and add 1

Example: -257 → 742 + 1 → 743Check: Add 743 to 257 and throw out the carry

0 257 +1 743 0 000

If you negate M 743 → P 256 + 1 → P 257 Note: Electronically it was easy for the ENIAC to

negate a number

Page 19: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

Unit of the ENIAC

Page 20: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

30 Units – 40 Panels

20 AccumulatorsMultiplier (3 panels)Divider/Square Rooter3 Function Tables (2 panels each)Constant Transmitter (3 panels)<- Card ReaderCard Punch Unit (3 panels) -> Card Punch Initiating Unit/Cycling Unit (2 panels)Master Programmer (2 panels)

Page 21: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

Functional Diagram of the ENIAC

cc

cM

M

• Accumulator× Multiplier÷ Divider/Square Rooterc Constant TransmitterM Master Programmer

Page 22: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

The Accumulators

Page 23: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

The Accumulator …

… could store a signed 10 decimal digit number.When it received a control pulse it could1. Receive a 10 digit signed number or 2. Transmit additively or subtractively its

contents over data lines3. Repeat the above a fixed number of times

depending on the setting of a console switch4. Send a control pulse (CCP) when it was doneAccumulators could be daisy chained together to

perform sequence of calculations

Page 24: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

View of ENIAC accumulators. Standing: Ester Gerston;crouching: Gloria Ruth Gorden. (US Army Photo; http://ftp.arl.army.

mil/ftp/historic-computers/png/eniac4.png.)

• http://www.library.upenn.edu/exhibits/rbm/mauchly/img/eniac4.jpg

Page 25: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

A Sample Calculation

Example taken from The Electronic Numerical Integrator and Computer (ENIAC) by H.H. Goldstine and Adele Goldstine; MTAC 1946; Reprinted in IEEE Annals of the History of Computing, Vol 18, No. 1 1996, pp. 10 - 16

Page 26: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

An Sample Calculation

Program a sequence of operations that calculate values of n, n2 and n3 for integers between 1 and 1400 printing every 7th set.

Note: (n+1)2 = n2 + 2n + 1(n + 1)3 = n3 + 3n2 + 3n + 1

Example taken from The Electronic Numerical Integrator and Computer (ENIAC) by H.H. Goldstine and Adele Goldstine; MTAC 1946; Reprinted in IEEE Annals of the History of Computing, Vol 18, No. 1 1996, pp. 10 - 16

Page 27: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

Sample Calculation: Assume AC18 = n; AC19 = n2; AC20 = n3

n 3n2n 1

Page 28: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

Sample Calculation: A1: AC19 transmits 3X; AC20 receives 3X AC18 = n; AC19 = n2; AC20 = n3 + 3n2

A1

n 3 23n n2n

Page 29: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

A2: AC18 transmits 3X; AC19 & AC20 receive 3X AC18 = n; AC19 = n2 + 2n; AC20 = n3+3n2+3n

A2

n 2 2n n 3 23 3n n n

Page 30: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

A3: CT transmits 1; AC18, AC19,AC20 receive 1XAC18 = n + 1; AC19 = n2+2n+1; AC20 = n3+3n2+3n+1

A3

3 23 3 1n n n 2 2 1n n 1n

Page 31: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

The Master Programmer

Four panels of ENIAC, with Betty Jennings and Frances Bilas (right) arranging the program settings on the master programmer, 1946 http://www.library.upenn.edu/exhibits/rbm/mauchly/img/7pansen.jpg

Page 32: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

The Master Programmer consisted of 10 units each consisting of ten decade counters and five 6-stage stepper-countersIt coordinated the 20 accumulators (and other units) providing sequencing and loop control. It could emit a control pulse to initiate a sequence of accumulator operations counting the number of times that sequence occurred. When the count was reached it could initiate the next sequence of accumulator operationsThere was a work-around for conditional branching

Page 33: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

Sample Calculation: The Initial Step – A1

A1

Page 34: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

Sample Calculation: CT -> A5

Page 35: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

Sample Calculation: Decision – Print or Continue? A1

A1

Page 36: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

Sample Calculation: A4 - At 200 end else continue

Page 37: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

Sample Calculation

Page 38: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

Epilog : 1946 – 1955and beyond

Page 39: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

The ENIAC was completed too late to produce ballistic tables for the Army in WWII

It’s first real test was a secret and complex calculation for a Los Alamos labs group working on the hydrogen bomb (late 1945? – rumored to require 1,000,000 punch cards)

The ENIAC was announced to the public on 2/14/46On 11/9/46 it was shut down and transferred to the Army’s BRL at

Aberdeen MD. It was restarted 7/29/47While at the BRL the ENIAC was redesigned so that it could be

programmed via its function tables; its initial 60 instruction set (A Logical Coding System Applied to the ENIAC - 1947) was later increased to 100 instructions.

In 1949 it computed π to 2000+ digits a record that held for 5 years! It was finally turned off on 10/2/55Units of the ENIAC can be seen at UMich, UPenn, and the

Smithsonian

Page 40: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

John von Neumann 1903 - 1957

Page 41: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

How von Neumann became interested in the ENIAC and in computers in general is interesting. In August 1944 while waiting at a R.R. station H.H. Goldstine introduced himself to von Neumann. He writes“I was waiting for a train to Pennsylvania on the railroad platform at Aberdeen when along came von Neumann. Prior to that time I had never met this great mathematician but I knew much about him of course and had heard him lecture on several occasions. It was therefore with considerable temerity that I approached this world famous figure, introduced myself, and started talking.”

Page 42: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

“Fortunately for me von Neumann was a warm, friendly person who did his best to make people feel relaxed in his presence. The conversation soon turned to my work. When it became clear to von Neumann that I was concerned with the development of an electronic computer capable of 333 multiplications per second, the whole atmosphere of our conversation changed from one of relaxed good humor to one more like the oral examination of the doctor’s degree in mathematics”

Page 43: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

Von Neumann had no direct impact on the design of the ENIACIn 1945 he wrote “First Draft of a Report in the EDVAC” – a paper

on stored program computers. Today it is understood that the ideas and proposals for the EDVAC (Electronic Discrete Variable Automatic Computer)represent the collective thinking of the ENIAC team.

During the summer of 1946 the “Moore School Lectures “(7/8/46 – 8/30/46) disseminated information on the EDVAC design. As a result ….

Cambridge University’s EDSAC (Electronic Delay Storage Automatic Computer) computer went operational 1949

The EDVAC was finally completed in 1952 In 1946 along with A. Burks and H.H. Goldstine , vonNeumann

authored “Preliminary discussion of the logical design of an electronic computing instrument”

Page 44: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

Von Neumann and IAS Machine - 1951

Unlike the EDVAC type machines the IAS machine was parallel using Williams tube memory instead of the EDVAC acoustic delay line memory

Page 45: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

Eckert & Mauchy

John Mauchy and J. Presper Eckhart foresaw the commercial potential for the electronic computer

In 1946 both left the Moore School and formed the Eckert-Mauchly Computer Corporation to build an EDVAC type computer (UNIVAC-I)

EMCC was bought out by Remington Rand in 1950, which merged with Sperry Corp -> Sperry Rand Corp. which today is Unisys.

The first UNIVAC was delivered to the US Census Bureau in 1951

In 1973 the ENIAC patent was voided (Honeywell Inc vs. Sperry-Rand Corp.)

Page 46: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

Women of the ENIACAdele Katz (Goldstine) -> authored Report on the ENIAC (1946)Ruth Rauschenberger (Ammlung)Lila Todd (Butler)Kathleen McNulty Mauchly AntonelliFrances Elizabeth (Betty) Snyder (Holberton)Betty Jean Jennings (Bartik)Marlyn Wescoff (Meltzer)Frances Bilas (Spence)Homé McAllister (Reitwiesner)Marie Bierstein (Malone)Willa Wyatt SigmundRuth Lichtermann (Teitelbaum)

Source: “The Women of ENIAC” by W. Barkley Fritz, IEEE Annals of the History of Computing, Vol. 18, No. 3 1996

Page 47: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

ENIAC at BRL: (left to right) Homé McAllister, Winifred (Wink) Smith, George Reitwiesner, and Ruth Lichterman

Page 48: The Architecture of the ENIAC The Electronic Numerical Integrator and Computer Brian J. Shelburne Dept. of Math and Comp Sci

Sources & Referenceshttp://www.library.upenn.edu/exhibits/rbm/mauchly/jwmintro.html

The Computer from Pascal to von Neumann by H.H. Goldstine; Princeton University Press, 1972.

From ENIAC to UNIVAC: An Appraisal of the Eckert-Mauchly Computers by Nancy Stern; Digital Press, 1981

“The ENIAC: History, Operation and Reconstruction in VLSI” by Jan Van der Spiegel, James F. Tau, Titiimaea F. Ala’ilima, Lin Ping Ang printed in The First Computers History and Architectures edited by Paul Rojas and Ulf Hashagen; MIT Press, 2000

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