teraphy: a chiplet technology for low- power, high ... · results have been estimated or simulated...
TRANSCRIPT
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TeraPHY: A Chiplet Technology for Low-Power, High-Bandwidth In-Package Optical
I/O
HotChips 2019 | Mark Wade | 08/17/19
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Dr. Mark Wade
Erik Anderson
Dr. Shahab Ardalan
Pavan Bhargava
Sidney Buchbinder
Dr. Michael Davenport
Dr. John Fini
Dr. Anatoly Khilo
Roy Meade
Dr. Chandru Ramamurthy
Michael Rust
Dr. Forrest Sedgwick
Dr. Vladimir Stojanovic
Dr. Derek Van Orden
Edward Wang
Dr. Chong Zhang
Dr. Chen Sun
Sergey Shumarayev
Conor O’Keeffe
Tim T. Hoang
David Kehlet
Dr. Ravi V. Mahajan
Allen Chan
Tina Tran
Sponsors:
DARPA CHIPS: Andreas Olofsson
DARPA PIPES: Gordon Keeler
ARPA-E ENLITENED: Mike Haney
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Outline
1) Motivation: why are
we working on this?
2) Intro to integrated
optics and core
technology
3) Putting it all together:
technology demonstrations
5) TeraPHY – the
Terabit/s optical PHY
6) Outlook and conclusions
4) Leveraging the chiplet
ecosystem
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Outline
1) Motivation: why are
we working on this?
2) Intro to integrated
optics and core
technology
3) Putting it all together:
technology demonstrations 6) Outlook and conclusions
5) TeraPHY – the
Terabit/s optical PHY
4) Leveraging the chiplet
ecosystem
![Page 5: TeraPHY: A Chiplet Technology for Low- Power, High ... · Results have been estimated or simulated using internal Intel analysis or architecture simulation or modeling, and provided](https://reader033.vdocuments.us/reader033/viewer/2022041415/5e1b45b499c88356724c71ea/html5/thumbnails/5.jpg)
Long range SerDes ends at 112 Gb/s
A new universal I/O technology is needed
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• Severe bandwidth tradeoff versus distance
• Large penalties for leaving the chip package and the board
• ~4 orders of magnitude difference in FoM from in-package to off board!
• Can integrated optics address this gap?
I/O Bandwidth trends
~4 orders of magnitude!
[G. Keeler, DARPA ERI 2019]
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• Severe bandwidth tradeoff versus distance
• Large penalties for leaving the chip package and the board
• ~4 orders of magnitude difference in FoM from in-package to off board!
• Can integrated optics address this gap?
I/O Bandwidth trends
[G. Keeler, DARPA ERI 2019]
TeraPHY
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Outline
1) Motivation: why are we
working on this?
2) Intro to
integrated optics
and core
technology
6) Outlook and conclusions3) Putting it all together:
technology demonstrations
5) TeraPHY – the
Terabit/s optical PHY
4) Leveraging the chiplet
ecosystem
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Silicon photonics building blocks• Waveguides on chip form photonic circuit building
blocks• waveguides
Silicon
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Silicon photonics building blocks• Waveguides on chip form photonic circuit building
blocks• waveguides• directional couplers
evanescent coupling between waveguides
Mach-Zehnder Interferometer
10
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Silicon photonics building blocks• Waveguides on chip form photonic circuit building blocks
• waveguides• directional couplers• microring resonators
off resonance on resonance
11
IN THRU
DROP
IN
DROP
THRU
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MZI’s versus microrings
Microrings offer:~100x smaller footprint~25-50x higher bandwidth density~50x higher energy efficiency
MicroringResonator
Mach-ZehnderInterferometer
25 Gbps – 100 Gbps
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Getting light on and off the chip: vertical grating couplers
cross-sectional view
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Getting light on and off the chip: vertical grating couplers
cross-sectional view
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Getting light on and off the chip: vertical grating couplers
cross-sectional view
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Getting light on and off the chip: vertical grating couplers
cross-sectional view
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Silicon waveguide
Microring modulator/detector
(source: IBM)
Vertical grating couplers
MOSFETs
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Outline
1) Motivation: why are we
working on this?
2) Intro to integrated
optics and core
technology
6) Outlook and conclusions
3) Putting it all
together: technology
demonstrations
5) TeraPHY – the
Terabit/s optical PHY
4) Leveraging the chiplet
ecosystem
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Microring-based WDM Optical Architecture
• Off-chip light source produces continuous wave (CW) laser
• Light is coupled from fiber-to-chip through vertical grating couplers
• Microring modulator converts data from electrical domain to optical domain
• Microring detector converts data from optical domain to electrical domain
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Microring-based WDM Optical Architecture
• Microring modulators act as both a modulator and a wavelength multiplexer
• Microring detectors act as both a detector and wavelength demultiplexer
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Microring-based WDM Optical Architecture
• Cascaded microrings along same waveguide increases data per fiber
• Each microring acts as an independent communications channel
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Microring-based WDM Optical Architecture
• Cascaded microrings along same waveguide increases data per fiber
• Each microring acts as an independent communications channel
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Microring-based WDM Optical Architecture
• Cascaded microrings along same waveguide increases data per fiber
• Each microring acts as an independent communications channel
• Scalable architecture up to ~64 microrings
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Building WDM Systems
• Monolithic integration allows for clocking, drivers, TIAs, and control circuitry to be integrated on same chip as optical devices
• Small size of microring devices monolithically integrated with CMOS transistors leads to large bandwidth density and energy efficiency
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Putting it together: First CPU with optical I/O
C. Sun, M. Wade, et al., Nature 2015
• Single SOI CMOS CPU
chip with optical I/O
• 70M transistors
• ~1,000 optical devices
• Microring based WDM
Enabled by the DARPA POEM project
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Putting it together: First CPU with optical I/O
C. Sun, M. Wade, et al., Nature 2015Enabled by the DARPA POEM project
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Ayar Labs optical I/O architecture
CPU/GPU/
ASIC/
FPGA
TeraPHY CMOS
Optical I/O chiplet
Up to 2km
reach
optical links
via SM fiber
SuperNova
multi-wavelength
optical power supply
Light supply via SM fiber to
multiple TeraPHY chiplets
Organic package/interposer
Electrical I/O
• Monolithic integration allows flexible electrical I/O interface to host SoC
• Wide parallel or high-speed serial
• Silicon interposer or organic substrate
• Remote laser source simplifies packaging
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TeraPHY technology test chip• Includes all electronics and photonics for
optical I/O (except laser)• Transmitter: 2.0 Tbps (5 x 400Gbps)
• 16 x 25Gbps• Digital backend• SerDes• High-speed clocking, distribution• Closed-loop thermal control• Built-in self test (BERT, debug, etc.)
• Receiver: 1.2 Tbps (3 x 400Gbps)• 16 x 25Gbps• Digital backend• SerDes• PD, TIA, equalization, CDR, clocking
[M. Wade et al., OFC/ECOC 2018]
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TeraPHY Technology demonstrations: WDM Tx Macro
• 16 x 25 Gbps• 1 Tbps/mm
• 1 Tbps/mm2
• 0.8 pJ/bit
400G DWDM Optical Tx Macro
Tx SliceTx SliceTx SliceTx Slice
SerializerMod
Driver
Ring
ModPRBS
[M. Wade et al., ECOC 2018]
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TeraPHY Technology demonstrations: WDM Rx Macro
• 1 Tbps/mm
• 500 Gbps/mm2
• 2.5 pJ/bit
Rx Eye Monitor Sweep
0.35UI at 25Gbps
Optical Rx BER Measurement
[M. Wade et al., ECOC 2018]
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TeraPHY Performance
• >500 Gbps/mm2, >1 Tbps/mm bandwidth density• <5 pJ/bit energy efficiency (all-inclusive of optics and
circuits)• Support high-performance SoC’s escaping many
terabits/second
40Gbps NRZ 50Gbps PAM4 100Gbps PAM4
Monolithic electronic-photonic integration in GlobalFoundries 45nm process
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Outline
1) Motivation: why are we
working on this?
2) Intro to integrated
optics and core
technology
6) Outlook and conclusions
3) Putting it all together:
technology demonstrations
5) TeraPHY – the
Terabit/s optical PHY
4) Leveraging the
chiplet ecosystem
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Industry Adoption of System-in-Package Integration
• Examples:
• Intel® Agilex™ FPGAs
• Nvidi Tesla T100
• Intel® Xeon® Scalable Processor Kaby Lake G
• AMD Radeon R9 Fury X
• Mix die function• GPU, CPU, memory, I/O, etc.
• Diverse processes & nodes• E.g. 16nm, 10nm, DRAM, etc.
• Manage yield
• For optics to use ecosystem, must be like electronics!
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Embedded Multi-die Interconnect Bridge (EMIB)
Microbump pitch 55um
Flip-Chip Pitch
> 100um
Intel® Embedded Multi-Die Interconnect Bridge (EMIB)
• EMIB packaging technology supports mixed bump pitch on the same die
• Embedded silicon bridge is used for dense die-to-die connectivity
• Organic substrate is used for off-package connections (power, I/O, etc.)
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Die-to-die interface: Serial vs Parallel
Metric Value
Bandwidth density ~1 Tb/s/mm
Energy ~2 pJ/bit
Design complexity high
Package complexity low
Metric Value
Bandwidth density ~1 Tb/s/mm
Energy ~0.5 pJ/bit
Design complexity low
Package complexity moderate
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Advanced Interconnect Bus (AIB)
AIB is open source
• Parallel in-package (2Gbps/IO)
• At ~3ns latency
• Over 1st gen EMIB (500 IOs/mm)
• At 0.85pJ/bit (for 55um ubump)
FOM=(2Gbpsx500/mm)/(0.85pJ/bit)=1176
AIB Configurable IO Cell
SDR→DDR DATA MUX Tri-StateDriver
DDR→SDR
ESD
S. Shumarayev, DARPA CHIPS, 2019
• AIB interface offers a suitable parallel interface and is compatible with both current (Intel® Stratix10™) and next-gen (Intel® AgileX™) FPGAs
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Bringing it all together: TeraPHY + EMIB + AIB +FPGA
Chiplet Integration Platform
Intel® FPGA die
Ayar Labs TeraPHY
Optical connections
Lid
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Outline
1) Motivation: why are we
working on this?
2) Intro to integrated
optics and core
technology
6) Outlook and conclusions
3) Putting it all together:
technology demonstrations
5) TeraPHY – the
Terabit/s optical PHY
4) Leveraging the chiplet
ecosystem
![Page 39: TeraPHY: A Chiplet Technology for Low- Power, High ... · Results have been estimated or simulated using internal Intel analysis or architecture simulation or modeling, and provided](https://reader033.vdocuments.us/reader033/viewer/2022041415/5e1b45b499c88356724c71ea/html5/thumbnails/39.jpg)
TeraPHY: Main features
• 24 Channels of AIB (960 Gbps total data bandwidth)
• 10 photonics Tx/Rx macro pairs
• Configurable to 128 – 256 Gb/s per macro (1.28-2.56 Tb/s per chip)
• NRZ modulation format on the optical channel – no FEC required!
• <10 ns (AIB -> TeraPHY -> AIB) + 5 ns/m latency
• Configurable cross-bar to map AIB channels to optical channels
• Reach: Up to 2km
• Estimated energy efficiency: <5 pJ/bit (all-inclusive)
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TeraPHY: Main features
Physical Implementation
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TeraPHY: Physical layout
AIB interface
AIB-to-TeraPHYmacro crossbar
TeraPHY macros
Optical input/output
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AIB
-to
-Te
raP
HY
Mac
ro
Cro
ssb
ar
Tera
PH
YTX
/RX
Mac
ros
AIB
Fib
er
Arr
ay
PLL-U
Clock Distribution
PLL-D PI
PI
RX
TX
TRX
Slic
e
TRX
Slic
e
Tx/Rx Macro
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AIB
Fib
er
Arr
ay
RXTIA, EQ
Clock Distribution
I/Q Gen. ILO
3 X PI
3 X PI I/Q Gen. ILO
TXEye MonitorHeat Driver
Tx/Rx SliceA
IB-t
o-T
era
PH
YM
acro
C
ross
bar
Tera
PH
YTX
/RX
Mac
ros
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EMIB Substrate
TeraPHY Location
EMIB Link between TeraPHY and FPGA
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SoC package assembly
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• TeraPHY based optical fabric creates new opportunities to build high bandwidth, low latency connectivity straight from the package
• Enables shelf, rack, and row system scale out
Logically connected, physically distributed
GPU GPU GPU GPU CPU CPU CPU CPU
FPGA FPGA FPGA FPGA ASIC ASIC ASIC ASIC
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• Chip-to-chip communications requires photonics to overcome I/O bottleneck
• Emerging chiplet ecosystem offers opportunity for in-package optics
• In-package optics fundamentally breaks the traditional bandwidth-distance trade-off and supports new high-performance computer architectures
Conclusions
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• Results have been estimated or simulated using internal Intel analysis or architecture simulation or modeling, and provided to you for informational purposes. Any differences in your system hardware, software or configuration may affect your actual performance.
• Intel does not control or audit third-party data. You should review this content, consult other sources, and confirm whether referenced data are accurate.
• All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps.
• No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document.
• Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.
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