deliverable 3.1 - design and realization of 8x8 tft array ...€¦ · both lay-outs, the following...

Collaborative project

Small or medium-scale focused research project

THEME FP7-ICT-2009-4

Deliverable 3.1 - Design and realization of 8x8

TFT array on foil

Contract no.: 248092

Project acronym: MOMA

Project full title: Embedded Organic Memory Arrays

Project website: http://www.moma-project.eu

Coordinator contact details: Gerwin Gelinck ([email protected])

TNO / Holst Centre

High tech Campus 31

PO Box 8550

5605KN Eindhoven

The Netherlands

Tel: +31 40 277 4098

Fax: +31 40 274 6400

MOMA Deliverable 3.1 Design and realization of 8x8 TFT array on foil

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Document revision history Version Date Author Summary of main changes

1 15-06-2011 Albert van Breemen Outline

2 10-07-2011 Sarah Schols First draft including imec results

3 15-07-2011 Albert van Breemen TNO results included

4 10-08-2011 Gerwin Gelinck Third version sent to partners for

approval

15-08-2011 Gerwin Gelinck Final version sent to Commission


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Table of Contents:

Document revision history.......................................................................................................................................... 2

1. Introduction ........................................................................................................................................................... 4

2. Design of arrays ................................................................................................................................................. 5

2.1 Bottom gate FeFET arrays ...................................................................................................................... 5

2.2 Top gate FeFET arrays............................................................................................................................... 7

2.3 Ferroelectric diode arrays ....................................................................................................................... 8

3. Realization of arrays ........................................................................................................................................ 9

3.1 Bottom gate FeFET arrays .................................................................................................................... 10

3.1.1 Discrete FeFETs using crosslinked P(VDF-TrFE) .......................................................... 10

3.1.2 FeFETs on flexible substrates ................................................................................................... 12

3.1.3 Photolithographical definition of source-drain contacts on top of P(VDF-

TrFE) 13

3.2 Top gate FeFET arrays............................................................................................................................. 17

3.2.1 Processing of thin layers of P(VDF-TrFE) on GIZO..................................................... 17

3.2.2 Deposition of top gate electrode ............................................................................................ 19

3.2.3 Process development on flexible substrates................................................................... 20

4. Conclusions .......................................................................................................................................................... 25


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1. Introduction

The demonstrators foreseen for M18 consist of a series of small memory transistor arrays on

flexible foils (up to 8x8 bits) and will be used to measure the electronic performance that will

be described in D5.4 (M24). Based on these scientific data, guidelines to improve the

performance of high density memory elements (1 kbit) as well as guidelines for addressing

schemes will be developed and implemented in 2012. The M6 memory arrays will be driven

using external, off-board micro-electronics. Table 1 summarizes the important design

parameters that were used as input for the designs described in more detail in chapter 2.

Table 1: key design parameters required in the readout electronics to fit with specification of

the device and array architectures (including diodes in a crossbar like array).

In chapter 3 the progress toward both flexible bottom gate and top gate FeFET arrays is

presented.


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2. Design of arrays

As explained in deliverable 5.1 we start with so-called passive matrix designs (Figure 1).

Figure 1: Different lay-outs of passive matrix arrays. The ‘AND’ and ‘NAND’ will

be used in this project. The third lay-out is new. Wiring of this lay-out makes it

technologically more complex, however.

These memory array circuits utilize a single ferroelectric memory field effect transistor cell

structure, i.e. the smallest footprint achievable. Important aspects will be to study crosstalk,

i.e. the influence of programming or reading on non-addressed bits. It is known that the use of

the common Vpp/2 and Vpp/3 rules for programming a non-volatile memory array circuits

utilizing a single ferroelectric memory field effect transistor may cause the loss of stored

information in adjacent memory cells due to disturb pulses. This is seen as one of the major

obstacles for commercialization of inorganic ferroelectric-based FeFETs. Although patent

literature suggests that for P(VDF-TrFE) this issue is not severe as for other ferroelectric

materials1, it has not been confirmed, simply because no-one has made these functional arrays

yet.

If a passive matrix can indeed be used then this is highly advantageous because of the lower

production costs and the reduced surface area per bit. Active-matrix arrays will be studied only

when it is clear that the passive matrix arrays cannot meet the requirements.

2.1 Bottom gate FeFET arrays

Figure 2 gives an overview of the FE ARRAY1.0 ORGANIC 150 mm design that was used to

fabricate bottom gate FeFETs and FeFET arrays based on pentacene as a semiconductor.

1 H. Gudesen, P. Nordal, G. Leistad, WO 99/12170, 1999; M. Thompson, R. Womack, G. Gustafsson, WO 02/25665, 2002

NAND AND


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Figure 2: FE ARRAY1.0 ORGANIC 150 mm design used to fabricate bottom gate FeFETs and

FeFET arrays

The design includes 13 ‘chiplets’ in which the I/O’s on every chiplet are kept constant, so that

the final test structures can be contacted using the Yokowo connector2 (Figure 3).

Figure 3: Schematic and picture of Yokowo connector

2 http://www.yokowods.co.jp/ev/cc/connectors/connectors_05-47.html


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Two different lay-outs of passive matrix arrays have been designed, parallel and serial. For

both lay-outs, the following three chiplet designs were made:

1. 16x16 + 2x (8x8) matrices (W/L: 1000/5 µm)

2. 2x (1x8 + 1x4 + 4x4 (W/L: 1000/5 µm) + 6 FeFETs (W/L: 1000/10 + 1000/5 + 1000/3

µm))

3. 2x (6x (1x4) (W/L: 1000/10 + 1000/5 + 1000/3 µm) + 3 FeFETS (W/L: 1000/5 µm))

2.2 Top gate FeFET arrays

Figure 4 gives an overview of the FE ARRAY1.0 GIZO 150 mm design that was used to fabricate

top gate FeFETs and FeFET arrays based on GIZO as a semiconductor.

Figure 4: FE ARRAY1.0 GIZO 150 mm design used to fabricate top gate FeFETs and FeFET

arrays

Similarly as in the FE ARRAY1.0 ORGANIC design, the GIZO design includes 13 ‘chiplets’ in

which the I/O’s on every chiplet are kept constant, so that the final test structures can be

contacted using the Yokowo connector.

Two different lay-outs of passive matrix arrays have been designed, parallel and serial. For

both lay-outs, the following three chiplet designs were made. The designs are similar to the ones of FE ARRAY1.0 ORGANIC, with differences being 1) different W/L ratios and 2)

rectangular S/D electrodes instead of a finger structure:

1. 16x16 + 2x (8x8) matrices (W/L: 80/5 µm)


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2. 1x8 + 1x4 + 4x4 (W/L: 80/5 µm) + 6 FeFETs (W/L: 80/20 + 80/10 + 80/5 + 40/20 +

40/10 + 40/5 µm)

3. 6x (1x4) (W/L: 80/5 µm) + 3 FeFETS (W/L: 80/5 µm)

2.3 Ferroelectric diode arrays

Figure 5 gives an overview of the FE DIODE1.0 150 mm design that is intended to be used to

fabricate Fe diodes and Fe diode arrays.

Figure 5: FE DIODE1.0 150 mm design used to fabricate Fe diodes and Fe diode arrays

Similarly as for the FeFET array designs, the FE DIODE design includes 16 ‘chiplets’ in which

the I/O’s on every chiplet are kept constant, so that the final test structures can be contacted

using the Yokowo connector. The following five chiplet designs were made:

1. 32x32 matrix 120x120 µm (2 chiplets)

2. 32x32 matrix 50x50 µm + 14 discretes 50x50 µm (2 chiplets)

3. 16x16 matrix 120x120 µm + 16x16 matrix 50x50 µm + 14 discretes (3 chiplets)

4. 2x (4x4) matrices 120x120, 120x50, 50x120, 50x50 µm + 14 discretes (3 chiplets)

5. 23 discretes 120x120 µm, 23 discretes 50x50 µm (6 chiplets)


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3. Realization of arrays

Transistor-based memories – The memory elements are preferably made with the same, or

similar, technology that is used to make the logic transistors. Here, we use our background in

high-performance transistors, more specifically a 150-mm wafer process to realize bottom-

gate, bottom-contact transistors using either pentacene or GIZO as semiconductor. All layers

are patterned using photolithography. This transistor technology was developed outside the

MOMA project, and will be used as a basis for integration of memory elements. Starting from a

flexible substrate, the stack of layers that needs to be integrated to arrive at a circuit with

embedded memory array is schematically represented in Figure 6.

Figure 6: Schematic overview of layer stack to be integrated for embedded memory. Not

indicated in this figure are the interconnects and via’s.

We have worked in parallel on:

A. Bottom-gate FeFETs based on pentacene. Because many of the layers of the logic and

memory transistor can be defined using the same mask step, this offers a route to low-mask

count. Key steps to be developed are

1. discrete FeFETS in combination with crosslinked P(VDF-TrFE)

2. process development on flexible substrates

3. photolithographic process to define the source-drain contacts.

a. Option a: on top of the P(VDF-TrFE) layer (bottom-gate bottom-contact).

b. Option b. on top of the pentacene film (bottom-gate top-contact).

B. Top-gate FeFETs based on GIZO. In this case the P(VDF-TrFE) film and gate electrodes of

the ferroelectric transistors are (in the case of the embedded memory demonstrator) made on

top of a substrate containing already the fully processed (and functional) logic circuits. Key

steps to be developed are:

4. thin and pinhole free P(VDF-TrFE) film on top of GIZO by spincoating

5. a top gate electrode (preferably inkjet printed, evaporated metal as contingency,

perhaps for comparative studies).

6. process development on flexible substrates

In Figure 7 below, one can find the serialized timeline of the activities. Each activity ends with a

decision point.


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with litho bottom contactOr: litho top contact

Arrays withbottom contact

jan feb march april may june

1.

2.

3.

4.

5.

6.

FeFET on X-linked

D1

D1 Yes/no crosslinking

A TNO supplies imec with flexible foils

AAll processing done on flexible foil

Proof of concept: FeFETD3

D3 Continue yes/no bottom contacts

Robust spincoat process to make

Discrete FeFETs with IJP top gate

Lower max process temperature to 150ºC, then processing done on flexible foil

GIZO arrays/ IJPtop gate

D4

D4

Continue yes/no with IJP Ag top gate

2011

Or: with shadowmask top gate

FeFET with Vprog <20V

that meet specifications

A (1-3): bottom gate FeFETs; B (4-6): top gate FeFETs

A

B

FeFET on foil

D2

Yes/no crosslinked FeFET on foilD2

P(VDF-TrFE)

Figure 7: timeline of activities and decision points toward M6 demonstrators

C. Diode-based memories – Although promising results are obtained, the main issue

presently is the low yield. This low yield is related to the rough morphology of the blend. We

have decided to work on discrete devices on rigid substrates, and only when the yield issue is

solved and a robust technology is developed we plan on developing arrays on foil.

3.1 Bottom gate FeFET arrays

3.1.1 Discrete FeFETs using crosslinked P(VDF-TrFE)

Bottom-gate top-contact ferroelectric transistors comprising crosslinked P(VDF-TrFE) as the

dielectric layer have been developed. A cross-section of the device architecture is depicted in

Figure 8. A Ti/Au gate electrode was first photolithographically patterned by lift-off on a glass

substrate. Then, a 160 nm thick film of P(VDF-TrFE) (77 wt% VDF, Solvay Solexis) was spin-

coated from a 3 wt.% cyclopentanone solution. To this solution the crosslinker was added,

using a P(VDF-TrFE):crosslinker ratio of 20:1 by weight. Subsequently, the spincoated sample

was annealed for 5 min at 55°C and exposed to UV-light. Afterwards, the sample was annealed

on a hotplate at 126°C for 1 hour in N2 atmosphere. On top of the P(VDF-TrFE) layer, 30 nm

pentacene was deposited by thermal vacuum evaporation through a shadow mask. The

memory structure was completed by metallic top-contact (100 nm Au) evaporation on the

pentacene layer through a shadow mask. As a reference, similar device was fabricated using

non-crosslinked P(VDF-TrFE). To obtain the same dielectric layer thickness of 160 nm, P(VDF-

TrFE) was spin-coated from a 4.5 wt.% cyclopentanone solution in this case.


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Figure 8: Cross-sectional view of the bottom-gate top-contact pentacene FeFET architecture

Figure 9 shows the transfer characteristics of both FeFET devices, measured under identical

conditions. The full line indicates the characteristics of the FeFET with non-crosslinked P(VDF-

TrFE), while the dotted lines represent the gate and drain current of the ferroelectric transistor

with crosslinked P(VDF-TrFE). As can be seen, both devices behave similar, indicating that the

ferroelectric properties of P(VDF-TrFE) are well preserved after crosslinking.

Figure 9: Transfer characteristics of bottom-gate top-contact pentacene FeFETs using (full

line) crosslinked P(VDF-TrFE) and (dotted line) non-crosslinked P(VDF-TrFE) as the dielectric

layer. In both cases the dielectric layer was 160 nm thick

In the above case, the crosslinked sample was not patterned, i.e. the whole sample was

illuminated with UV-light. To pattern the P(VDF-TrFE), one needs to illuminate through a

lithographic mask, and subsequently remove the non-illuminated parts with a developer

(methyl isobutyl ketone).

To investigate the influence of P(VDF-TrFE) patterning on the FeFET performance, the transfer

characteristics of a FeFET with crosslinked but non-patterned dielectric layer were compared to

the transfer curves of a FeFET with patterned P(VDF-TrFE). For both samples, pentacene and

Au top-contact deposition were done in the same run to eliminate run to run variation. The

results are summarized in

Figure 10. No clear difference could be observed between both devices. Only a slightly higher

gate current (at negative VG) was measured for the FeFET with patterned dielectric layer, but

this is due to processing issues.


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Figure 10: Transfer characteristics of bottom-gate top-contact pentacene FeFETs. The full lines

represent the characteristics of a FeFET with crosslinked but non-patterned P(VDF-TrFE), while

de dotted lines correspond to the characteristics of a FeFET with patterned P(VDF-TrFE).

3.1.2 FeFETs on flexible substrates

PEN foil covered with SU-8 was selected to realize bottom-gate top-contact pentacene FeFETs

on flexible substrates. During processing, the foil was glued on a rigid carrier, which can be

removed afterwards. Processing of the FeFET device itself was similar as described in section

3.1.1. A 160 nm thick film of crosslinked P(VDF-TrFE) was used as the dielectric layer. On top

of this, 30 nm pentacene and 100 nm Au top contacts were deposited by thermal vacuum

evaporation through a shadow mask. The transfer characteristics of the device are depicted in

Figure 11. The device showed normal FeFET behavior, however, the yield was much lower

compared to FeFET fabrication on glass. Further optimization is necessary to solve these yield

issues.

Figure 11: (left) Transfer characteristics of a pentacene FeFET processed on PEN foil, (right)

Image of the PEN foil with FeFET devices after delamination of the carrier.


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3.1.3 Photolithographical definition of source-drain contacts on top of P(VDF-TrFE)

Two different routes can be investigated to realize source-drain contacts by photolithography:

a) Bottom-gate bottom-contact FeFETs

b) Bottom-gate top-contact FeFETs whereby the top-contacts are photolithographically

patterned.

The first integration route is maximal compatible with the current p-type pentacene technology

available for logic. However, it brings along new challenges such as patterning of contact paths

on top of P(VDF-TrFE). The second integration route, on the other hand, requires the

development of a technology to photolithographically pattern metal on top of an organic

semiconductor.

Option a: source-drain contacts on top of P(VDF-TrFE) (bottom-gate bottom-contact).

A prerequisite to achieve bottom-gate bottom-contact FeFET devices, is the development of a

process that allows patterning of Au on top of P(VDF-TrFE). Wet-etching of Au on top of

crosslinked P(VDF-TrFE) could be achieved using the Au etchant TFA. After etching, the AZ6612

resist was removed by immersing the sample 5 hours in hot IPA. A photograph depicting Au

patterns on top of P(VDF-TrFE) is shown in

Figure 12.

Figure 12: Photograph depicting Au patterns on top of crosslinked P(VDF-TrFE)

The involved solvents (Au etchant and hot IPA) do not significantly influence the ferroelectric

behaviour of P(VDF-TrFE). Capacitors with P(VDF-TrFE), which was dipped into the solvents

before the evaporation of the top-contact, only show a slight reduction of the remnant

polarization; the coercive field stays unaffected (see

Figure 13, left panel). An AFM image of crosslinked P(VDF-TrFE) after immersion in Au etchant

and 5h IPA is depicted in the right panel of

Figure 13. A slightly reduced grain size of the P(VDF-TrFE) domains could be observed; an

RMS-roughness of 3.63 nm was measured.


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Figure 13: (left) Sawyer-Tower measurements performed on P(VDF-TrFE) capacitors. The

crosslinked P(VDF-TrFE) layer was dipped into the solvents (Au etchant and hot IPA) before the

evaporation of the top-contact; (right) AFM image of crosslinked P(VDF-TrFE) which was

immersed 15 sec in Au etchant and 5h in hot IPA.

Using the above described Au wet-etching process, bottom-gate bottom-contact pentacene

FeFETs were realized. The dielectric layer P(VDF-TrFE) had a thickness of 160 nm, whereas the

Au contacts and pentacene were both 50 nm thick. Pentacene was patterned by deposition

through a shadow mask.

Figure 14 shows the transfer curves of the FeFET devices. A schematic of the device

architecture is depicted as inset in the figure. As can be seen from

Figure 14, a significant smaller memory window was measured compared to bottom-gate top-

contact pentacene FeFETs. The obtained results were stable and reproducible.

Figure 14: Typical transfer characteristics of a bottom-gate bottom-contact pentacene FeFET

device. The bottom-contacts were photolithographically patterned, whereas the pentacene was

deposited through a shadow mask.

Different experiments were performed to find out the origin of the smaller memory window.

Bottom-gate bottom-contact devices fabricated using only shadow masking show a large

memory window, indicating that the problem relies on the lithographic process itself. However,

the Au etchant, the hot IPA nor the Au deposition give rise to a reduction in the memory

window. Further investigation is needed to clarify this issue.


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Figure 15 shows retention and switching speed measurements performed on the bottom-gate

bottom-contact pentacene FeFETs. Switching from the off-state to the on-state is fast (< 1ms);

switching from on to off, on the other hand, needs about 1s. Retention was measured up to 3

hours without significant reduction of the performance.

Figure 15: (left) Switching and (right) retention measurements performed on pentacene

FeFETs with lithographically patterned bottom-contacts.

Endurance measurements on pentacene FeFETs with lithographically patterned bottom-contacts

are shown in

Figure 16. After 10³ cycles the Ion/Ioff ratio was reduced to 15.

Figure 16: Endurance measurements performed on pentacene FeFETs with lithographically

patterned bottom-contacts.

In order to realize arrays based on pentacene FeFETs an additional step, which is not indicated

in the timeline of Figure 7, is needed, namely, the photolithographical patterning of pentacene

on top of P(VDF-TrFE). Pentacene patterning using orthogonal resist and developer has been

demonstrated for standard pentacene TFTs. A typical transfer curve of such a transistor is

shown in

Figure 17. Patterning of pentacene on top of P(VDF-TrFE), on the other hand, is still under

investigation. Only if the development of this process is successful, and hence, all layers of a


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pentacene FeFET can be photolithographically patterned, the technology is ready for the

realization of pentacene arrays.

Figure 17: Transfer characteristic of a standard pentacene TFT. Pentacene was patterned

using orthogonal resist and developer.

Option b: source-drain contacts on top of pentacene (bottom-gate top-contact).

A second option to realize a fully litho pentacene FeFET is to photolithographically pattern the

source-drain contacts on top of pentacene. This process is currently being optimized for

standard pentacene TFTs. Wet-etching of Ag top-contacts on pentacene is successful, however,

the electrical properties of the device are only maintained when pentacene is not patterned.

This can be clearly seen when comparing

Figure 18 and Figure 19.

Figure 18 shows the transfer characteristics of unpatterned pentacene TFTs. The transfer

curves of patterned pentacene TFTs are depicted in Figure 19. Further optimization is ongoing.

As soon as good TFT characteristics can be obtained on patterned pentacene layers, the

process will be transferred to FeFETs.

Figure 18: Transfer characteristics of a pentacene TFT with Ag top-contacts, which were

photolithographically patterned. The pentacene layer was not patterned in this case.


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Figure 19: Transfer characteristics of a pentacene TFT with Ag top-contacts, which were

photolithographically patterned. The pentacene layer was patterned in this case.

3.2 Top gate FeFET arrays

3.2.1 Processing of thin layers of P(VDF-TrFE) on GIZO

Our background in high-performance transistors, more specifically a 150-mm wafer process to

realize bottom-gate, bottom-contact transistors using GIZO as semiconductor was used as a

basis for integration of FeFETs and FeFET arrays.

The source-drain layers and interconnect lines were deposited by e-beam evaporation of gold

on n++ silicon wafers capped with a 200 nm thermal silicon oxide layer. The semiconductor

layer was formed by a 30 nm thick GIZO layer deposited using rf-sputtering. GIZO was

deposited from a target with 2:2:1 atomic ratio for Ga:In:Zn. Partial pressure of oxygen inside

the sputtering chamber was kept low (<3%) in order to achieve TFTs operating at low

processing temperatures. After GIZO deposition an anneal step of 4 min at 150 °C in air was

performed. All layers were patterned using standard photolithographic techniques. A cross-

section of the device architecture is depicted in

Figure 20.

GIZOAu

Al2O3

P(VDF-TrFE)Au

SiO2

Si

GIZOAu

Al2O3

P(VDF-TrFE)Au

SiO2

Si

Figure 20: Cross-sectional view of the GIZO dual gate FeFET architecture

Optimisation of P(VDF-TrFE) anneal conditions in GIZO FeFETs.

P(VDF-TrFE) (77 wt% VDF, Solvay Solexis) was spin-coated from a 8 wt.% cyclopentanone

solution at 2000 rpm. Spincoated samples were annealed on a hotplate at 135°C for 2, 5, 10

and 60 minutes in air which resulted in a layer thickness of 450 nm. Top gate FeFETs were

completed by metallic top-contact (100 nm Au) evaporation through a shadow mask. Figure

21A shows bottom gate (BG, dashed curves) and top gate (TG, solid curves) transfer

characteristics of GIZO FeFETs using different P(VDF-TrFE) anneal times. In the bottom gate

configuration SiO2 is the gate dielectric, whereas in the top gate configuration P(VDF-TrFE) is

the ferroelectric gate dielectric. Annealing times of up to 10 minutes give identical BG

characteristics. Extending the anneal time to 60 minutes gives a negative Vth shift of about


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30V. Top gate FeFET characteristics again show similar behaviour up to 10 minutes anneal

time.

In order to monitor the evolution of the remnant polarization at different P(VDF-TrFE) anneal

times, capacitors were processed on the same substrates. Figure 21B shows hysteresis loops of

capacitors using P(VDF-TrFE) anneal times of 2 and 60 minutes. The saturated loops are

symmetric with a remnant polarization of + or - 70 mC/m2. The coercive voltage (Vc), i.e.

where D is 0, is found at |32| V, which corresponds to a coercive field (Ec) of ca. 75 MV/m. The

hysteresis loop of the film annealed for 2 minutes is indistinguishable from the one annealed

for 60 minutes. Apparently, an anneal time of 2 minutes is sufficient to maximise the

ferroelectric response. Combining the results shown in Figure 21 led us to the conclusion that

an anneal time of 2 minutes at 135 ºC is sufficient to obtain GIZO FeFETs with a high ON/OFF

ratio, ION/IOFF of >105.

-40 -30 -20 -10 0 10 20 30 4010

-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

I D [A

]

VBG

/VTG

[V]

2 Min BG

2 Min TG

5 Min BG

5 Min TG

10 Min BG

10 Min TG

60 Min BG

60 Min TG

A

-100 -80 -60 -40 -20 0 20 40 60 80 100

-150

-100

-50

0

50

100

150 B

D [m

C/m

2]

V [V]

2 min @ 135ºC

60 min @ 135ºC

device area 0.16 mm2

hysteresis freq. 100 Hz

P(VDF-TrFE) ~ 450 nm

Figure 21: A.Bottom gate (dashed curves) and top gate (solid curves) transfer characteristics

of GIZO FeFETs using different P(VDF-TrFE) anneal times. B: Hysteresis loops of capacitors

using different P(VDF-TrFE) anneal times measured on the same substrates.

Figure 22 shows transfer characteristics of top-gate GIZO FeFETs using P(VDF-TrFE) layer

thicknesses ranging from 450 down to 175 nm. The applied gate field was identical for all samples (-90 MV/m → + 90 MV/m → - 90 MV/m) at VSD of 50 mV. The drain current, ID is

plotted as function of the field, E.

-100 -75 -50 -25 0 25 50 75 10010

-14

10-12

10-10

10-8

10-6

175 nm

190 nm

275 nm

450 nm

I D [A

]

E [MV/m]


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Figure 22: Transfer characteristics of top-gate GIZO FeFETs using P(VDF-TrFE) layer

thicknesses of 175 – 450 nm.

3.2.2 Deposition of top gate electrode

Two methods for top gate electrode deposition were used, inkjet printing of silver and

shadowmask evaporation of gold.

Inkjet printing of Ag

Inkjet printing of silver was done using a Dimatix printer in combination with a commercial

Suntronic silver ink (U5603). A 10 pL cartridge and 20 µm drop spacing was used throughout

all experiments. Wet layers were sintered in an oven for 30 minutes at 120ºC.

Figure 23 shows a microscopy picture of a typical example of printed Ag lines after sintering at

120ºC for 30 minutes. In this case, a bitmap with lines and spaces of 100 and 140 µm resulted

in Ag lines of ~120µm and spaces of ~120 µm. Other bitmap lines and spaces gave a similar

deviation of about ± 20 µm. Using these experimental conditions, the designed line width has

to be 20 µm smaller than the target line width.

Figure 23: microscopy picture of printed Ag lines on P(VDF-TrFE) after sintering for 30 min. at

120ºC.

Evaporation of Au

Evaporation of gold was done by thermal evaporation through a shadowmask. For the array

demonstrators, a 150 mm shadowmask was made based on the FE ARRAY1.0 GIZO design

shown in Figure 4.

Optimised printing parameters were used to benchmark printed Ag top electrodes in capacitors.

Figure 24 shows a comparison of capacitors in which the top electrode was varied. Printed Ag

and evaporated Ag and Au were used. In all cases the bottom electrode was patterned Au on

which a 450 nm P(VDF-TrFE) was spincoated. All saturated loops are symmetric and square

with in case of evaporated top electrodes a remnant polarization of + or - 75 mC/m2. The

coercive voltage (Vc), i.e. where D is 0, is found at |33| V. Capacitors with printed Ag top

electrode show similar loops albeit with a slight decrease in Pr and Vc of about 5 and 10 %

respectively.


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-100 -75 -50 -25 0 25 50 75 100-100

-75

-50

-25

0

25

50

75

100

Printed Ag

Evaporated Ag

Evaporated Au

D [m

C/m

2]

V [V]

device area 0.46 mm2

hysteresis freq. 100 Hz

Vc (V) Pr (mC/m2)

Printed Ag 30 72

Evaporated Ag 33 76

Evaporated Au 33 75

Figure 24: D-V hysteris loops of capacitors with printed Ag and evaporated Ag and Au top

electrodes. Bottom electrode was in all cases Au.

3.2.3 Process development on flexible substrates

Because the maximum process temperature was limited to 150 °C the devices were made on

25 µm thick heat stabilized PEN substrates. The foils were glued to a rigid carrier support

during fabrication, the so-called foil on carrier process (PEN-FOC). After processing, the foils

could be detached from the carrier, resulting in a highly flexible plastic foil containing FeFET

arrays. The source-drain layers and interconnect lines were deposited by e-beam evaporation

of gold. The semiconductor layer was formed by a 30 nm thick GIZO layer deposited using rf-

sputtering. GIZO was deposited from a target with 2:2:1 atomic ratio for Ga:In:Zn. Partial

pressure of oxygen inside the sputtering chamber was kept low (<3%) in order to achieve TFTs

operating at low processing temperatures. After GIZO deposition a short anneal step of 4 min

at 150 °C in air was performed. All layers were patterned using standard photolithographic

techniques. The technology was upscaled to 150 mm laminated foils. Top gate electrodes were

applied by inkjet printing of Ag as described in 3.2.2 or shadowmask evaporation of Au.

Figure 25 shows the thermal processing steps of FOC FeFETs with either a printed Ag or

evaporated Au top gate. Temperatures are chosen to be foil compatible, i.e. maximum 150 ºC.

In case of FeFETs with a printed top gate, an extra anneal step for 30 minutes at 120 ºC is

performed in order to sinter the Ag-ink.

GIZO anneal

150 ºC

P(VDF-TrFE) anneal

135 ºC

Sintering Ag ink

120 ºC

GIZOAu

Al2O3

P(VDF-TrFE)

SU-8

Ag

PEN-FOC

GIZOAu

Al2O3

P(VDF-TrFE)

SU-8

Ag

PEN-FOC

GIZOAu

Al2O3

P(VDF-TrFE)

Au

PEN-FOC

GIZOAu

Al2O3

P(VDF-TrFE)

Au

PEN-FOC Figure 25: processing steps for FeFETs on flexible substrates with either printed or evaporated

top electrodes.


21/25

The technology developed and optimized in sections 3.2.1 and 3.2.2 was combined and used

on the FOC substrates described above. In all cases, the top gate was inkjet printed Ag. A

typical example of a top gate FeFET processed on a FOC substrate is presented in Figure 26.

V+ and V- are the voltages extracted at ID = 10-7 A for the two memory states. Subtraction of

V+ and V- directly results in the memory window at the same drain current. Vswitch+ and

Vswitch- are the voltages extracted from the maximum of the switching peaks in the IG-VG

curve.

-20 -15 -10 -5 0 5 10 15 20

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

Vswitch-

Vswitch+V+

I G [nA

]

I D [A

]

VG [V]

W/L 80/5 µµµµm

VSD

50 mV

V-

-3

-2

-1

0

1

2

3

Figure 26: Left: ID-VG (black) and IG-VG (red) characteristics of a typical top gate FeFET

processed on a FOC substrate. V+ and V- are the voltages extracted at ID = 10-7 A for the two

memory states respectively. Subtraction of V+ and V- directly results in the memory window at

the same drain current. Vswitch+ and Vswitch- are the voltages extracted from the maximum

of the switching peaks in the IG-VG curve. Right: 150 mm laminated foil being detached from

the carrier, resulting in a highly flexible plastic foil containing FeFETs and FeFET arrays.

Table 2 shows the overview of extracted parameters of top gate FeFETs processed both on rigid

and FOC substrates using different P(VDF-TrFE) layer thicknesses.

Layer thickness

(nm)

Yield

(%) V+ (V) V- (V)

Memory

window

Vswitch+

(V)

Vswitch-

(V)

175 25 3.5 (0.1) -0.8 (0.1) 4.8 (0.4)

190 75 4.9 (0.24) -5.5 (0.25) 5.5 (0.7) 9.7 (0.7) -9.2 (0.4)

275 92 7.1 (1.6) -0.2 (4.1) 7.2 (1.6) 15.2 (2.9) -13.4 (2.1)

R

I

G

I

D 450 100 11.3 (2.2) -0.3 (3.6) 11.7 (1.8) 21.5 (2.9) -19.8 (0.7)

175 33 3.8 (1.0) 1.2 (0.8) 2.6 (0.4) 8.1 (0.2) -8.1 (0.3)

190 92 3.5 (0.5) -1.1 (0.6) 4.5 (0.2) 9.5 (0.2) 9.5 (0.1)

275 100 4.0 (0.9) -2.0 (0.7) 6.0 (0.3) 13.6 (0.4) 12.2 (0.5)

F

O

C 450 92 7.5 (1.3) 0.3 (1.1) 7.2 (0.8) 22.0 (0.3) 19.9 (0.7)

Table 2: Overview of extracted parameters for FeFETs processed on rigid and foil on carrier

(FOC) substrates using P(VDF-TrFE) layer thicknesses in the range of 175 to 450 nm. VD = 50

mV. Standard deviations of extracted parameters are given in parentheses.

Up to a P(VDF-TrFE) layer thickness of 190 nm the yield of FeFETs on FOC substrates is close

to unity. These FeFETs can be programmed below 20V and hence meet the MOMA specification


22/25

as presented in Table 1. At the moment, a P(VDF-TrFE) layer thickness of 190 nm is used by

default.

Figure 27 displays the transfer characteristics of a FeFET before and after delamination from

the rigid carrier. The characteristics are well preserved after delamination and are still close to

identical.

-20 -15 -10 -5 0 5 10 15 2010

-13

10-11

10-9

10-7

10-5

Before delamination

After delamination

and bending

I G [nA

]

I D [A

]

VG [V]

-1.0

-0.5

0.0

0.5

1.0

L = 10 µµµµm

W = 40 µµµµm

VD = 50 mV

FG053A4010

Figure 27: Transfer characteristics of FOC FeFETs before and after delamination from rigid

carrier.

Scaling of channel length (L) and channel width (W) was investigated as well. Figure 28

presents normalized transfer curves of FOC FeFETs with different W/L ratios that clearly follow

the trend as expected from theory.

Figure 28: Scaling of W/L for FOC FeFETs with printed Ag top gate. Transfer curves are

normalized to W/L = 1.

Figure 29 shows retention and switching speed measurements performed on the top-gate GIZO

FOC FeFETs. Both switching from the off-state to the on-state and from on to off needs about

-20 -15 -10 -5 0 5 10 15 2010

-15

10-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

W40L05

W40L20

W80L05

W80L10

W40L05

W40L10

W40L20

W80L05

W80L20

I D [A

]

VG [V]

Sample: FG019

Layer Thickness: 191 nm

Normalized W/L: 1/1


23/25

1s and is clearly out of spec. This issue will be investigated in more detail in the next period.

Retention was measured up to about 300 hours without significant reduction of the

performance.

10-3

10-2

10-1

100

101

10-11

10-10

10-9

10-8

10-7

10-6

Off to On

On to Off

W/L 80/20 µµµµm (FG065A8020)

VREAD

-3V

I D [A

]

t prog

[s]

100

101

102

103

104

105

106

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

I D [A

]Time (s)

ID on

ID off

L = 5 µm

W = 10 mm

Figure 29: (left) Switching and (right) retention measurements performed on GIZO top gate

FOC FeFETs.

Endurance measurements on GIZO FOC FeFETs are shown in Figure 30. After 10³ cycles the

Ion/Ioff ratio is still about 105. Prolonged cycling results in a steep decrease of the on-current

and finally device failure after about 104 cycles.

1 10 100 1000 1000010

-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

L = 20 µm

W = 10 mm

I D [A

]

No of Cyles

ID on

ID off

Figure 30: Endurance measurements performed on GIZO FOC FeFETs.

The technology described in section 3.2.3 has led to the realization of a series of FeFET arrays.

Figure 31 presents one of the chiplets of the FE ARRAY1.0 GIZO 150 mm design described in

section 2.2 containing containing two 8x8 and one 16x16 FeFET array.


24/25

Figure 31: Picture of a chiplet containing two 8x8 and one 16x16 FeFET array on a flexible

substrate. Top gate electrodes were made by inkjet printed silver.

In Figure 32 an example of the characterisation of the first flexible 1x4 GIZO FeFET array with

parallel architecture is presented. Firstly all 4 FeFETs in the array were programmed in the “0’’

state (Figure 32 left). Then the gate electrodes of 3 unselected FeFETs were connected and set

at a VG unselect of 0V. Of the remaining select FeFET an IV sweep (shown in red) was recorded

at a VD of 100 mV. Similarly IV sweeps were recorded at a VG unselect of -2.5 (shown in green)

and -5V (shown in blue). It can be seen that a VG unselect of -5V is needed to read out the

select FeFET. The measurement protocol was repeated by first programming the FeFETs in the

“1’’ state (Figure 32 right). Again a VG unselect of -5V is needed to read out the select FeFET.

-20 -10 0 10 2010

-14

10-12

10-10

10-8

10-6

10-4

VG unselect = 0V

VG unselect = -2.5V

VG unselect = -5V

I D [A

]

VG, select

[V]

VD = 0.1V

Unselected cells in “0” state

-20 -10 0 10 2010

-14

10-12

10-10

10-8

10-6

10-4

VG unselect = 0V

VG unselect = -2.5V

VG unselect = -5V

VD = 0.1V

I D [A

]

VG, select

[V]

Unselected cells in “1” state

Figure 32: Transfer curves of a 1x4 FeFET array with parallel architecture using a VG unselect

of 0, -2.5 and -5V. VD = 100 mV. Left: unselected cells were first programmed in “0’’ state.

Right: unselected cells were first programmed in “1’’ state.

A more detailed evaluation of FeFET arrays will be described in deliverable 5.4 (M24).


25/25

4. Conclusions

Progress towards bottom-gate pentacene FeFET arrays has been made. Pentacene FeFETs

using crosslinked P(VDF-TrFE) as well as pentacene FeFETs on flexible PEN substrates were

demonstrated. In addition, pentacene FeFETs with photolithographically patterned bottom-

contacts were realized and characterized. Currently, pentacene patterning on top of P(VDF-

TrFE) is under investigation. As soon as this technology has been developed, it should be

possible to fabricate fully litho pentacene FeFET devices and pentacene memory arrays.

Low temperature processing of thin layers of P(VDF-TrFE) on GIZO has been opmized to realize

GIZO FeFETs that can be programmed below 20V with a yield close to unity. Inkjet printing of

silver top gate electrodes on top of P(VDF-TrFE) has been shown and was benchmarked in

ferroelectric capacitors. Remnant polarization and coercive voltage are similar to evaporated

top electrodes. Combination of low temperature process technologies has led to fully flexible

GIZO FeFETs and FeFET arrays. Switching speeds are slow and typically about 1s. This issue

will be subject of a more detailed investigation. As an example, the characterization of a

functional 1x4 flexible FeFET array was shown. By careful tuning of the VG unselect, the select

FeFET can be read correctly independent of the initial programming state.

deliverable 3.1 - design and realization of 8x8 tft array ...€¦ · both lay-outs, the following...

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