techniques of synthesizing carbon nanotube fets for integrated circuits gao, feng s.i.d 20219798

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TECHNIQUES OF SYNTHESIZING CARBON NANOTUBE FETS FOR INTEGRATED CIRCUITS GAO, Feng S.I.D 20219798

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Page 1: TECHNIQUES OF SYNTHESIZING CARBON NANOTUBE FETS FOR INTEGRATED CIRCUITS GAO, Feng S.I.D 20219798

TECHNIQUES OF SYNTHESIZING CARBON

NANOTUBE FETS FOR INTEGRATED CIRCUITS

GAO, FengS.I.D 20219798

Page 2: TECHNIQUES OF SYNTHESIZING CARBON NANOTUBE FETS FOR INTEGRATED CIRCUITS GAO, Feng S.I.D 20219798

PART I. NANOTUBE PLACEMENT

PART II. COMPLEMENTARY DEVICES

PART III. IMPERFECTION REMEDY

Page 3: TECHNIQUES OF SYNTHESIZING CARBON NANOTUBE FETS FOR INTEGRATED CIRCUITS GAO, Feng S.I.D 20219798

2. Deposit NMPI (Self Aligned)

1. Pattern SiO2 /HfO substrate

4. Ion exchange reaction

3. Aqueous CNT solutions preparation

Self-Assembly Approach[1,2]

NANOTUBE PLACEMENT

[1] Park, Hongsik, et al. "High-density integration of carbon nanotubes via chemical self-assembly." Nature nanotechnology 7.12 (2012): 787-791.[2] Wu, Justin, et al. "Top‐Down Patterning and Self‐Assembly for Regular Arrays of Semiconducting Single‐Walled Carbon Nanotubes." Advanced Materials 26.35 (2014): 6151-6156.

Page 4: TECHNIQUES OF SYNTHESIZING CARBON NANOTUBE FETS FOR INTEGRATED CIRCUITS GAO, Feng S.I.D 20219798

Dielectrophoresis[3]

NANOTUBE PLACEMENT

[3] Shekhar, Shashank, Paul Stokes, and Saiful I. Khondaker. "Ultrahigh density alignment of carbon nanotube arrays by dielectrophoresis." ACS nano 5.3 (2011): 1739-1746.

CNT density controlled by solution concentration ranges from 0.5 – 30 SWNT/μm

1. Pre-pattern electrodes

2. Oxygen plasma cleaning

3. DEP with DC 5 Vpp at 300kHz for 30s

4. Blown dry by N2 gas

Page 5: TECHNIQUES OF SYNTHESIZING CARBON NANOTUBE FETS FOR INTEGRATED CIRCUITS GAO, Feng S.I.D 20219798

NANOTUBE PLACEMENTTransfer Approach (Langmuir–Schaefer Method)[4]

• Semiconductor CNT purity: 99%

• CNT density: 500 tubes/μm (full converage)

[4] Cao, Qing, et al. "Arrays of single-walled carbon nanotubes with full surface coverage for high - performance electronics." Nature nanotechnology 8. 3 (2013): 180 - 186.

Page 6: TECHNIQUES OF SYNTHESIZING CARBON NANOTUBE FETS FOR INTEGRATED CIRCUITS GAO, Feng S.I.D 20219798

Controlled Growth[5]

NANOTUBE PLACEMENT

[5] Papadopoulos, Chris, and Badr Omrane. "Nanometer‐scale Catalyst Patterning for Controlled Growth of Individual Single‐walled Carbon Nanotubes." Advanced Materials 20.7 (2008): 1344-1347.

1. Pattern catalyst

2. Grow CNT3. Fabricate electrodes and gates

Page 7: TECHNIQUES OF SYNTHESIZING CARBON NANOTUBE FETS FOR INTEGRATED CIRCUITS GAO, Feng S.I.D 20219798

COMPLEMENTARY DEVICES1. Contact Controlled Devices Type[6]

High Work Function Metal

(Pd, Au)

Femi Level Near to

Valence Band

p-FET

Low Work Function Metal

(Sc, Y, Er)

Femi Level Near to

Conduction Band

n-FET

• Problem: Low work function metals are readily oxidized• Solution: Cover with inert metal and passivation layer

[6] Han, S-J., et al. "Carbon nanotube complementary logic based on erbium contacts and self-assembled high purity solution tubes." IEEE Int. Electron Dev. Meet 19 (2013): 1-19.

Page 8: TECHNIQUES OF SYNTHESIZING CARBON NANOTUBE FETS FOR INTEGRATED CIRCUITS GAO, Feng S.I.D 20219798

COMPLEMENTARY DEVICES

2. Dielectric Controlled Device Type[7]

3. Chemical Doping for n-FET[8]n-FETp-FET

[7] Franklin, Aaron D., et al. "Carbon nanotube complementary wrap-gate transistors." Nano letters 13.6 (2013): 2490-2495.[8] Javey, Ali, et al. "High performance n-type carbon nanotube field-effect transistors with chemically doped contacts." Nano letters 5.2 (2005): 345-348.

Potassium (K) Doping, Introduce electron carriers

Page 9: TECHNIQUES OF SYNTHESIZING CARBON NANOTUBE FETS FOR INTEGRATED CIRCUITS GAO, Feng S.I.D 20219798

REMEDY FOR IMPERFECTION

1. Cleaning metallic CNTs[9]

G

D

S

G

D

SApply high voltage

Breakdown voltage of semiconductor CNT is larger than metallic CNT

[9] Kim, Sunkook, et al. "Current on/off ratio enhancement through the electrical burning process in ambient with/without oxygen for the generation of high-performance aligned single-walled carbon nanotube field effect transistors." Applied Physics Letters 97.17 (2010): 173102.

m-CNT s-CNT

Page 10: TECHNIQUES OF SYNTHESIZING CARBON NANOTUBE FETS FOR INTEGRATED CIRCUITS GAO, Feng S.I.D 20219798

REMEDY FOR IMPERFECTION

2. Mis-positioned CNT Immune Design[10]

[10] Zhang, Jie, et al. "Robust digital VLSI using carbon nanotubes." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31.4 (2012): 453-471.

Etched Regions

Mis-positioned caused error After etch Mispositioned CNT-

immune

Layout for SOP form

Page 11: TECHNIQUES OF SYNTHESIZING CARBON NANOTUBE FETS FOR INTEGRATED CIRCUITS GAO, Feng S.I.D 20219798

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