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Technical Data Reference Guide netX 10

next Generation of Communication Controllers

Language: English

netX10 Technical Data Reference Guide - Preliminary • 2

Hilscher Gesellschaft für Systemautomation mbH – Rheinstr. 15 – D 65795 Hattersheim Edition 0.9 – Technical Data Reference Guide:netX10#EN – 2010/12

TECHNICAL DATA REFERENCE GUIDE 1

1 INTRODUCTION 4

2 FUNCTIONAL OVERVIEW 6 2.1 Processors 6

2.1.1 ARM CPU 6 2.1.2 xPEC/xMAC 6 2.1.3 xPIC 6

2.2 Oscillator 7 2.3 System LED and Boot Options 8 2.4 Extended System Information 9 2.5 Reset 10

2.5.1 Sources 10 2.5.2 Power On Configuration Option 11

2.6 Watchdog 11 2.7 Internal Memory 12 2.8 External Memory 12

2.8.1 SRAM / FLASH Interface 12 2.8.2 SDRAM Interface 21

2.9 Dual-Port memory interface 27 2.9.1 Introduction 27 2.9.2 Parallel DPM interface modes 30 2.9.3 Serial (SPI) DPM interface mode 35 2.9.4 DPM Signal Timing 36 2.9.5 DPM Interrupt Signals 49

2.10 Timer 50 2.11 IEEE 1588 System Time 51 2.12 JTAG Debug Interface 52

2.12.1 Standard JTAG connector 52 2.12.2 Boundary Scan mode 53 2.12.3 Embedded Trace Macrocell ETM 54

2.13 Vectored Interrupt Controller (ARM) 55 2.13.1 Interrupt generation 57 2.13.2 Interrupt priority logic 58 2.13.3 Interrupt flow sequence 58

2.14 Vectored Interrupt Controller (XPIC) 59 2.15 DMA Controller 60 2.16 Multiplex Matrix 61 2.17 IO-Link Interface 62 2.18 UART 63 2.19 USB 66 2.20 I2C Interface 67

2.20.1 Overview 67 2.20.2 Functional Description 68

2.21 SPI / SQI 72 2.21.1 Overview 72 2.21.2 Functional description 73

2.22 GPIO 76 2.23 PIO 77 2.24 Ethernet Interface 78 2.25 Fieldbus Interface 80

2.25.1 AS interface Master 81

netX10 Technical Data Reference Guide - Preliminary Introduction • 3


2.25.2 CANopen Interface 82 2.25.3 CC-Link Interface 83 2.25.4 DeviceNet Interface 84 2.25.5 PROFIBUS Interface 85

3 ELECTRICAL SPECIFICATIONS 86 3.1 Absolute Maximum Ratings 86 3.2 Power Up Sequencing 87 3.3 Power Consumption / Power Dissipation 89 3.4 AC / DC Specifications 90

3.4.1 DC Parameters 90 3.4.2 System Oscillator / PLL 92 3.4.3 Power On Reset / Reset Input 93 3.4.4 MMIOs 94 3.4.5 USB 95 3.4.6 PHY 96 3.4.7 SDRAM 97 3.4.8 SRAM / FLASH 102 3.4.9 SPI 106 3.4.10 I2C 112 3.4.11 UART 113 3.4.12 Dual-port Memory Signal Timing 114

Serial Mode IO Timing 124 3.4.13 JTAG 127

3.5 Failure Rate (FIT) 128 4 PACKAGE AND SIGNAL INFORMATION 129 4.1 Thermal Package Specification 129 4.2 Soldering Conditions 130

4.2.1 Infrared Reflow Soldering Characterization 130 4.2.2 Vapour Phase Reflow Soldering (VPS) Characterization 131

4.3 General storage conditions 131 4.4 Signal Definitions 133

4.4.1 Schematic View of netX Pad Types: 137 4.5 Multiplex Matrix Signals 138 4.6 Pin Table Sorted By Pin Numbers 140 4.7 Pin Table Sorted By Signals 142 4.8 Pin overview 146

4.8.1 Overview 1 146 4.8.2 Overview 2 (b/w) 147

4.9 Mechanical Dimensions / Physical Dimensions 148 4.10 Material composition 149

4.10.1 Solder balls 149 4.11 Ordering Information 149 5 PRINTED CIRCUIT BOARD DESIGN 150 5.1 Routing hints 150 5.2 Vcc Pin Requirements / Decoupling Capacitors 150 6 REFERENCE PCB LAYOUT DESIGN 150

7 REFERENCE SCHEMATICS 150

8 REVISION HISTORY 151

9 CONTACTS 152



1 Introduction

Product Features

• Powerful 100 MIPS ARM 966 CPU, providing ARMv5TE technology with enhanced DSP capability • Optimized 3 channel CPU bus connection ( replaces Tightly Coupled Memory ) • High performance data switch allowing parallel access, thus avoiding bottle necks • xPEC/xMAC channel for communication protocols, either operating as fieldbus interface (supporting

AS interface, CAN, CC-Link, PROFIBUS) or as 10/100MBit/s Ethernet Channel with integrated PHY, supporting Real-time Ethernet Protocols Ethernet/IP, ModbusTCP

• Time stamping and synchronization according to IEEE 1588 • User programmable xPIC core for various applications • Separate peripheral bus and environment for xPIC and ARM like Vectored Int. Controllers, Watch-

dogs and Timers • 296 KByte internal RAM (no external RAM required for most applications) • 6 separate RAM segments (4*64K, 1*32K, 1*8K) for parallel memory access • 32Kbyte local memory for xPEC and xPIC • 64 KByte ROM • Dedicated UARTs providing a 4 channel IO-Link Master Controller (along with xPIC) • Enhanced 8/16 Bit Memory Controller, supporting SDRAM, FLASH (page/burst mode) and READY

signal input for external wait state generation • Configurable Dual Port Memory Interface (8/16 Bit or fast SPI Slave (80MHz)) • Fast SQI Controller (nibble SPI) working as standard SPI or 4-Bit SQI with up to 200Mbit/s through-

put and xiP (Execute in place) functionality (no need for parallel flash) • Enhanced PWM Unit (2,5 ns resolution, 8 channels, dual time base, sync and IRQ support) • Two enhanced Encoder Units (with filter, capture, sync, IRQ and additional support for precise ve-

locity measurement) • 2 Integrated 10-bit ADCs with 8 input channels each, 1 MS/s, programmable sequencer unit with

trigger and interrupts for enhanced synchronization • Enhanced Interrupt/Synchronization support for PWM, Encoder and ADC units • CORDIC based MATH function accelerator accessible by all internal processors, primarily used for

converting polar to Cartesian coordinates with motor control applications. • USB interface, device (upstream), full speed (12 Mbit), USB 1.1 • 2 UARTs, 16550 compatible • SPI (up to 50MHz), Master and Slave • I2C Interface (up to 3.4 Mbit/s) • 8 x GPIO with enhanced capture and PWM capabilities • 24 Line Multiplex Matrix for flexible pin function switching with PIO functionality • Up to 47 additional PIOs (unused pins of host / memory interface) • JTAG Debug Interface • ARM Embedded Trace Macrocell for real time tracing • Small 13mm * 13mm BGA package • Extended temperature range (-40°C to +85°C) • Well proven NEC 150 nm technology • Guaranteed 10 years life time • Boot option via parallel or serial FLASH, serial EEPROM, MMC, DPM, UART or Ethernet Typical Applications • Communication Interfaces for PLC, Drives, HMIs and all types of Sensors or Actuators • Standalone Application for I/Os, Identification Devices or Gateways



The netX10 network controller combines the communication power of netX core technology with highly integrated control peripherals in a small package to allow sophisticated single chip solutions for next generation networked devices in all kinds of sensor/actuator industrial applications.

Fig. 1 Block diagram netX10.

The basic functionality of netX10 is derived from the netX50 network controller architecture. The netX10 controller provides a single programmable communication channel supporting all kinds of fieldbus inter-faces, an IEEE1588 Time unit as well as an integrated PHY to support a variety of non-switched Ethernet networks. As all members of the netX controller family, the netX10 benefits from the already well-proven xMAC/xPEC communication channel technology, where the Medium-Access-Controller (xMAC) sends and receives the serial data streams according to the respective bus access process and converts them from Bit to Byte streams, while the Protocol Execution Controller (xPEC) compiles the bytes delivered by the xMAC into data packets and controls the telegram traffic. This allows the implementation of the most varied protocols which can be synchronized independently of the Host CPU response time. A large number of additional functional units have been integrated to provide high flexibility for different applications. In order to support applications like fast IO or fast and precise sensor or actuator inter-faces, a dedicated, user programmable xPIC processor, highly optimized for fast response and high calculation power, has been added. Along with the high resolution PWM and Encoder Units and a dedi-cated MATH Function Accelerator, advanced motion control or signal processing applications can easily be realized with a single netX10 chip.

netX10 Technical Data Reference Guide - Preliminary Functional Overview • 6


2 Functional Overview

The following chapters provide an overview of the Key Function Units within the netX 10.

2.1 Processors

2.1.1 ARM CPU

The main processor of the netX10 is an ARM966 core running on 100MHz clock, a well known standard CPU for general purpose and embedded applications. The connection of the ARM966 core to the data switch has a total of three ports in order to achieve higher data throughput and lower wait states (1.5 x performance of netX50 ARM, though half the system clock frequency). The two additional ports make the classic TCM (tightly coupled memory) obsolete by accessing two internal RAM segments as needed instead of using dedicated TCM which would increase chip size and cost. The ARM core in netX10 is mainly used for processing of higher levels of communication protocols, while still leaving processing power for user specific applications.

2.1.2 xPEC/xMAC The xMAC core together with the xPEC core represent one xC channel (communication channel), opti-mized for lower levels of communication protocols, allowing fast and deterministic response to real-time events and combining the flexibility and performance of FPGA based solutions with the reliability and low unit cost of an ASIC design. With the xC cores running protocol specific microcode on assembler language level, virtually any serial communication protocol can be realized with an xC channel. The instructions for the RPU (Receive Processing Unit) and TPU (Transmit Processing Unit) are 64 Bit wide and include up to eight commands per instruction, being all executed simultaneously. Theoretically this yields a computing performance of 1700 MIPS. With common applications, RPU and TPU programs utilize two to three commands per instructions on average, resulting in a performance of ca. 600 MIPS. xPEC/xMAC technology is already well proven by the netX100/500 and netX50 controllers and has been further enhanced in the netX10.

2.1.3 xPIC The xPIC is a flexible Peripheral Interface Controller designed especially for user applications. The xPIC is a general purpose 32-bit RISC CPU with an instruction set optimized (DSP extensions) for fast and deterministic data processing as needed in many real industrial applications. The xPIC can be used as a fast CPU to filter, analyse, collect, convert and process sensor data, ranging from simple IOs to com-plex encoders and sensors with an analog front-end. Another range of applications is the control of any actuators ranging from simple digital and analog IOs, pumps, valves, or switches to the control of virtu-ally any type of electric motor. Along with the integrated encoder, PWM and CORDIC units, the xPIC can be used to realize many kinds of control applications in the motion or process control field and may, along with 4 dedicated UARTs, be used as a four channel IO-Link Mastercontroller



2.2 Oscillator

All internal clock signals of the netX are generated by a PLL which is driven from an internal oscillator that requires an external 25 MHz crystal. Alternatively, an external oscillator can be used. In this case the clock signal has to be connected to OSC_XTI, while OSC_XTO is left unconnected. Fig. 2 Oscillator schematic for the 25 MHz clock.

netX

OSC-XTOOSC-XTI

25 MHz

22 pF22 pF

OSC-VDDCOSC-VDDIO

1.5V3.3V

OSC-VSS GND



2.3 System LED and Boot Options

The general status of a netX based system is displayed by the System LED(s). It is recommended to use a dual LED here, but two single LEDs can also be used. The general definition of this LED is RDY yellow the netX with operating system is running RUN green the user application is running without errors However, after booting a firmware, the LEDs are firmware controlled and their behavior is hence com-pletely application- or firmware specific. The RDY and RUN signals are also used as inputs after a reset to select the boot mode. Applying cer-tain logic levels to these pins during and shortly after reset, results in a pre-selection of the several available boot options and hence determines, where the ROM boot loader looks for executable program code. Further, these pins are used to connect a secure EEPROM to the netX10, containing licenses and other application specific information like MAC addresses or SDRAM parameter as well as the de-sired bootmode and boot options. In applications, where no secure EEPROM is connected, the desired boot mode is selected according to the following schematic: Fig. 3 RDY/RUN circuit.



In applications, where a secure EEPROM is used (mandatory for master applications), the desired boot mode is selected by a parameter, stored in the EEPROM. In that case, boot jumpers can’t be used, as the EPPROM will not be accessed unless a high level is applied to both pins, RDY and RUN. The use of a boot mode button, forcing the serial boot mode, is however possible and recommended. The following schematic shows the proper circuit for attaching the SYS LED, a boot mode button and a secure EEPROM to the netX10:

Fig. 4 RDY/RUN circuit with Secure EEPROM.

Please note, that the above circuit is different from the corresponding circuit for the netX50.

2.4 Extended System Information The two LEDs 'RDY' and 'RUN' described in chapter 'System LED and Boot Options' are controlled by the netX via a special system status configuration register, containing information about the system status of the netX. This status information (DPM_HOST_SYS_STAT) is set by the netX boot software or firmware. The definition of each status bit and status code is software specific. Further, there are four host status flags which can only be controlled by an external host system connected to the DPM inter-face of the netX10. When a write access to the netX status flags is performed by the netX, an interrupt request can be generated, to notify the host about the changes. For a detailed description of the register bits see the 'netX10 Program Reference Guide'



2.5 Reset

2.5.1 Sources

The netX offers five reset sources which can generate a system reset of the chip. One of them is an external input, while the others are generated by different internal function blocks. PORn Power on reset, input pin (Schmitt trigger)

This (active low) signal shall be connected to the output of a voltage supervisor chip, which checks the power supply voltages and pulls the power on reset pin low, when-ever the voltages are below the minimum specified netX system operating voltages. The power on reset signal causes an asynchronous reset of the netX chip and initial-izes all internal registers and signals to their power on reset state. Reset timing is specified in chapter 3.4.3.

WDG_RES If the internal watchdog counter expires, this reset is generated. It is also possible to

generate an interrupt before the watchdog resets the chip. For more details see chap-ter 2.6 (netX system watchdog).

HOST_RES This reset is initiated by the host system interface by writing a special sequence into

a host interface register. The reset will occur 1 ms after starting the write cycle allow-ing the host to finish the access and prepare for the netX chip reset.

FIRMW_RES This reset can be activated by a software command. XPEC_RES This reset is generated by the xPEC controller. The following figure shows an overview of the netX10 reset circuit block. Fig. 5 Block diagram of the Reset Controller.

PORn

Reset

FIRMW_RES

XPEC_RES

CLR

>1

1CLK

&xPEC DIS_XPEC_RES

WDG_RESWDG

HOST_RESDPM

CLK

All otherinternal

Modules

xPECReset

WDG_RES

XPEC_RES

HOST_RESFIRMW_RES

RES_CR

RES_CR

1

CLR

CLRCLK

FIRMW_FLG0

RES_CR

FIRMW_FLG1FIRMW_FLG2FIRMW_FLG3

CLRCLK

RES_CR

DIS_XPEC_RES

>1



2.5.2 Power On Configuration Option

Shortly after the rising edge of the power on reset signal, the signal states of 27 DPM / Memory inter-face pins (D15-D0, A10-A0) and 5 SQI pins (SPI0_CLK, SPIO0_MISO, SPI0_MOSI, SPI0_SIO2, SPI0_SIO3) are stored in a 32 Bit register (SAMPLE_AT_NRES) located in the Asic Control Area. By attaching (switchable) external pull-ups or pull-downs to these signals and evaluating the corre-sponding register, a hardware based configuration functionality may be implemented by appropriate firmware. Notes: 1) Only the 27 DPM / Memory Interface signals should be used for appropriate user applications, since

the state of the SQI signals is also evaluated by the ROM boot loader to enable certain hardware option during the boot sequence.

2.6 Watchdog

For system supervision, the netX is equipped with an internal 2-stage watchdog counter. Once the watchdog is active, the timeout counter has to be triggered continuously. The watchdog works in two stages: When the IRQ timeout counter has reached zero, an Interrupt is generated, to indicate that the watchdog will soon perform a reset and needs attention. When the reset timeout counter reaches zero as well, the netX will be reset by the watchdog. The timeout register values are reloaded to the watchdog timer whenever the watchdog is triggered, which is done by setting the watchdog trigger bit. This will also clear an active interrupt request flag (timeout, stage 1 was reached). Writing to the timeout register is only possible when the write enable timeout flag is set. This prevents undesired access to the timeout registers.

Fig. 6 Internal structure of watchdog logic.

Notes: 1) While the netX10 system watchdog is almost identical to the system watchdog of netX50/100/500,

the netX10 watchdog does not provide a watchdog active signal (WDG_ACT), indicating if the watchdog has been armed or has run into the timeout state.



2.7 Internal Memory

The netX10 contains 296 KByte static RAM, 64 KByte of Boot ROM and 32 KByte local RAM for the xPEC and xPIC processors (16Kbytes each). The 296 KByte RAM is divided into six separate blocks (four blocks of 64K, one block of 32K and one block of 8 K), with each block having its own interface to the data switch, allowing simultaneous data transfers to all six memory blocks.

2.8 External Memory The netX10 is equipped with an Enhanced Memory Controller can drive static RAM or FLASH and SDRAM (8- or 16 Bit devices) without any additional glue logic. SRAM / FLASH and SDRAM Interface share the address and data lines and most of the control signals in a way that provides minimum signal count while still allowing parallel use of both interfaces. The memory controller further supports a Ready or Busy signal, allowing to attach memory devices that do not have a deterministic access time and it provides Asynchronous Page-Mode access if supported by the parallel FLASH component. The memory controller shares its signals with the netX10 DPM interface, hence external memory can only be connected when the DPM interface is not used (the only exeception is when using the DPM interface in serial (SPI) mode, which alllows to operate 8 Bit memory devices at the same time). Note: Since the signal buffers of the netX10 memory interface are more or less designed for single memory component, the allowed maximum load capacity has to be considered, when connecting more tan one memory component, to ensure stable operation throughout the whole temperature and operating volt-age range!

2.8.1 SRAM / FLASH Interface The SRAM / FLASH Interface provides a total of four memory areas, which provide their own chip select signals and independent configuration registers, allowing to set bus width and wait state parameters separately for each area. As one of these chip selects (MEMSR_CS1n) is shared with the SDRAM chip select signal, this chip select area is not available for SRAM / FLASH if SDRAM is connected. The parameters allow bus width configurations of 8 and 16 Bit, wait states of up to 63 clock cycles and enabling or disabling the Ready/Busy signal. The Ready signal parameters (polartiy, etc.) are commonly set for all chip select areas and there is also a single configuration register for the parameters related to the APM (Asynchronous Page Mode), which is only supported by chip select area 0. Unlike with other netX controllers (netX50/100/500), address lines A23:0 always represent the byte address, regardless of the bus width of the connected component. To allow single byte access in 16Bit mode, two Byte Lane signals (MEMSR_DQM0 = MEM_A00 and MEM_DQM1) are provided. The maximum of adressable external SRAM / FLASH memory is 32MB each, in chip select area 0 and 1, which is reduced to 16MB if Chip Select Area 2 is used (requires signal MEMSR_CS2n which is shared with address line 23) and to 8MB if Chip Select Areal 3 is used (requires signal MEMSR_CS3n which is shared with address line 22: Setup using Maximum addressable SRAM / FLASH memoryChip Select 0 only (e.g. SDRAM used) 32MB

Chip Select 0 and 1 64MB (2 * 32MB)

Chip Select 0, 1 and 2 48MB (3 * 16MB)

Chip Select 0, 1, 2, and 3 32MB (4 * 8MB)

Table 1: SRAM/FLASH, adressable memory



2.8.1.1 SRAM / FLASH Access Timing SRAM access timing is widely configurable for each chip-select individually. Chip Select Area 0 can be additionally configured for Asynchronous Page Mode (APM). The following wait state parameters can be set: Pause Comment

pre-pause 0 to 3 cycles

Access setup phase: This phase can be used to match setup timing requirements of connected device. Read-enable and write-enable signal will be inactive during this phase. They will be changed to active state when changing to wait-state-phase or access cycle. All other netX driven signals are active and valid during this phase.

wait-states 0 to 63 cycles (can be extended by ready signal)

Device access time wait phase: During read access this is read-enable--signal active low phase. During write access this is write-enable-signal active low phase. All netX driven signals are active and valid during this phase.

access-cycle 1 cycle

Read data is sampled during this cycle and must be valid. Read-enable and write-enable signal will become inactive at the end of this cycle when followed by a post-pause.

post-pause 0 to 3 cycles

Access hold phase: This phase can be used to match hold (for write) or output disable (for read) timing require-ments of connected device. Read-enable and write-enable signal will be inactive, while all other netX driven signals are active and valid during this phase. For write accesses at least 1 cycle post will always be inserted to generate positive edge on write-enable signal.

Table 2: SRAM/FLASH wait state parameters

Single Access: Fig. 7 Single read and write access.

Read-Enable

Write-Enable

Address

Data

pre-p.0..3

Chip-select

Byte-Enable

valid address

rdata

ws-p.0..63

ac1

post-p.0..3

valid

Read-Enable

Write-Enable

Address

Data

pre-p.0..3

Chip-select

Byte-Enable

valid address

write data

ws-p.0..63

ac1

post-p.1..3

valid



Sequential Access: By default, the configured pre and post pause cycles are also inserted between the single steps of a sequential access, resulting in a read or write signal that toggles after each step, while the chip select signal will always be asserted througout the whole sequential access: Fig. 8 Sequential read with intermediate pre and post pause not disabled (default, like

netX50/100/500)

To allow Burst type accesses, the configured pre and post pause cycles may be skipped between the single steps of a sequential access by setting corresponding parameters (no_p_pre_seq_rd and no_p_post_seq_rd). As with write accesses, the write signal necessarily needs to toggle after each ac-cess step, the programmed pre and post pause cycles will never be skipped and if the pre and post pause cycles are programmed to 0, one post pause cycle will automatically be inserted during sequen-tial writes, making sure the write signal will become inactive for at least one system clock cycle after each step of the sequential access: Fig. 9 Sequential read with intermediate pre and post pause disabled.

Read-Enable

Write-Enable

Address

Data

pre-p.0..3

Chip-select

Byte-Enable

Address

rdata

ws-p.0..63

ac1

post-p.0..3

valid

pre-p.0..3

Address

rdata

ws-p.0..63

ac1

post-p.0..3

valid

rdata

ac1

post-p.0..3

pre-p.0..3

Addr

valid valid

Addr

ws-p.0..63

ws-p.0..63

Read-Enable

Write-Enable

Address

Data

pre-p.0..3

Chip-select

Byte-Enable

Address

rdata

ws-p.0..63

ac1

valid

Address

rdata

ws-p.0..63

ac1

valid

rdata

ac1

post-p.0..3

Addr

valid valid

Addr

ws-p.0..63

ws-p.0..63



Fig. 10 Sequential write.

When data direction is changed (read after write or write after read access) at least one pre-pause cycle will always be inserted. The following example (assuming pre and post pause parameters set to 0) shows this case and also demonstrates the automatically inserted post pause cycle between two steps of a sequential write: Fig. 11 Sequential write followed by sequential read with pre and post pause set to 0.

write data n write data n+1 wD n+2 wD n+m

Read-Enable

Write-Enable

Address

Data

pre-p.0..3

Chip-select

Byte-Enable

Address

ws-p.0..63

ac1

post-p.1..3

valid

pre-p.0..3

Address

ws-p.0..63

ac1

post-p.1..3

valid

ac1

post-p.1..3

pre-p.0..3

Addr

valid valid

Addr

ws-p.0..63

ws-p.0..63

write data

Read-Enable

Write-Enable

Address

Data

Chip-select

Byte-Enable

write Address

ws-p.0..63

ac1

valid

ac1

valid

read Addr

ws-p.0..63

ws-p.0..631

write data

write Address

ws-p.0..63

ac1

valid

1 1

read Address

ws-p.0..63

ac1

valid

read Addr

valid

rdata rdata

always at least 1 cyclepost-pause after write

always at least 1 cycle pre-pause atread after write or write after read



In the unlikely event of a chip select change during a sequential access (can only occur when different netX masters (DPM, XC, xPIC, ARM, DMA)try to access different external memory devices simultane-ously or when a single master is performing burst access exceeding chip-select address area border), a pre pause cycle will automatically be inserted if necessary (if pre or post pause parameters are not set to 0, automatic pre pause is not required and will not be inserted): Fig. 12 Automatic insertion of pre and post pause cycles at chip select change (pre and post pause

cycles set to 0).

The following example shows a scenario where:

• Chip-select A is configured for 3 cycle pre-pause, 2 cycle post-pause and disabled pauses during sequential reads.

• Chip-select B is configured for 2 cycle pre-pause, 1 cycle post-pause. Note: Since most memory devices will not require intermediate pre and post pause cycles and since the memory controller inserts them automatically where absolutely necessary, it is recommended to set the corresponding bits that will disable the intermediate pause cycles to achieve best performance.

write data

Read-Enable

Write-Enable

Address

Data

Chip-select B

Byte-Enable

write Address

ws-p.0..63

ac1

valid

ac1

valid

read Addr

ws-p.0..63

ws-p.0..631

write data

write Address

ws-p.0..63

ac1

valid

1 1

read Address

ws-p.0..63

ac1

valid

read Addr

valid

rdata rdata

always at least 1 cyclepost-pause after write

always at least 1 cycle pre-pause atread after write or write after read

Chip-select A

1 1

always at least 1 cyclepre-pause at chip-select change

write data

Read-Enable

Write-Enable

Address

Data

Chip-select B

Byte-Enable

write Address

ws-p.0..63

ac1

valid

ac1

valid

read Addr

ws-p.0..63

ws-p.0..63

post-p.2

write data

write Address

ws-p.0..63

ac1

valid

pre-p.3

read Address

ws-p.0..63

ac1

valid

read A

valid

rdata rdata

Chip-select A

always at least 1 cycleno chip-select active

pre-p.2

1

post-p.1

1

post-p.2

config. ofchip-select A

config. ofchip-select B

config. ofchip-select A



APM (Asynchronous Page Mode) Burst Access: As mentioned earlier in this chapter, chip select area 0 is able to perform APM read burst accesses, which consist of a longer initial access followed by shorter accesses to data located within the current memory page. The burst is restarted with the initial access after chip-select was inactive, after write or when address changes to a different memory page. Memory pages are addressed by higher address lines, data words within a page by lower address lines. Page boundary can be configured to 4, 8, 16, 32, 64 or 128 for 8 bit devices and to 2, 4, 8, 16, 32 or 64 for 16 bit devices. The timing for the initial access is defined by the standard pre-, post pause and wait state parameters of the chip select 0 area, while the timing for the consecutive accesses within the same memory page is determined by the wait state parameter (0 to 15 cycles) for APM accesses. Notes: 1) APM is generally only available for read access.

2) When using APM, set the corresponding disable bits for pre and post pause cycles

(no_p_pre_seq_rd and no_p_post_seq_rd), to ensure the output enable (read) signal will re-main active throughout the whole access.

Read-Enable

Write-Enable

Page-Address

Data

pre-p.0..3

Chip-select

Byte-Enable

Page A

rdata

ws-p.0..63

ac1

valid

rdata

apmws-p.0..15

ac1

valid

rdata

ac1

post-p.0..3

valid

Page B

Word-Address Word A Word B Addr

rdata

ac1

valid

Word C

ws-p.0..63

Page B

rdata

ac1

valid

rdata

apmws-p.0..15

ac1

valid

Word A Word B

apmws-p.0..15

apmws-p.0..15



External Wait State Generation – Ready Signal: Another new feature of the Enhanced Memory Controller is the support of external wait state generation by a configurable Ready/Busy signal, that allows to connect memory (or memory-like) devices that do not have a deterministic access time. Ready signal support is configurable separately for each chip select area, whereas the configuration of the Ready signal applies to all chip select areas. The configurable parameters of the Ready signal in-clude signal polarity (active low, active high), timeout and timeout IRQ and signal filter (off, 2, 3 or 4 cycles). By default the filter is turned off and it should only be used in electrically noisy environments, as using the filter necessarily increases the time required to detect the external wait state request, which again requires to increase the fixed (programmed) wait states. The timeout feature avoids that an internal netX master would hang when accessing an external device that won’t release the Ready/Busy signal. If the timeout is enabled, any access will be aborted after 1024 system clock cycles (10µs). To allow proper handling of such an incident, an IRQ can be gener-ated on netX side when a timeout occurs. Further, the corresponding chip select signal and address of the access that resulted in a timeout can be logged to a register. When enabled, the Ready/Busy signal must be asserted to wait-state before configured fixed wait time ends. The access cycle will be finished when ready-state was detected however not before complete programmed wait phase passed. Depending on ready filter setting, Ready state detection may take up to 6 system clock cycles. Fig. 13 Read access with externally generated wait states.

Fig. 14 Write access with externally generated wait states.

Read-Enable

Write-Enable

Address

Ready

pre-p.0..3

Chip-select

Byte-Enable

valid address

rdata

ws-p.0..63

ac1

post-p.0..3

valid

Data

ready wait

ext. generated wait-phase0..1024

sample/filter2..6

ready

write data

Read-Enable

Write-Enable

Address

Ready

pre-p.0..3

Chip-select

Byte-Enable

valid address

ws-p.0..63

ac1

post-p.0..3

valid

Data

ready wait

ext. generated wait-phase0..1024

sample/filter2..6

ready



2.8.1.2 Connecting parallel FLASH The correct way to hook up a parallel FLASH to the netX10 depends on the addressing scheme of the FLASH component. While some components use their address line A0 for Low- High Byte selection when operating in 8 Bit mode and don’t use this address line at all when operating in 16 Bit mode, other components expect A0 to represent the least significant address Bit of a 16 Bit Adress and provide an-other signal for Low High Byte selection in 8 Bit mode (if supported by the component at all). While it is, due to lower performance, generally not recommended to use FLASH components with 8 Bit data bus, the 8 Bit mode may still be an option with the netX10, as it allows the parallel use of the DPM interface in SPI mode. Since 16 Bit FLASH devices are more common than 8 Bit devices, it should also be considered to use 16 Bit devices that support Byte mode instead of pure 8 Bit components. The following schematics show the proper wiring in 8 Bit and 16 Bit mode for two 128 MBit FLASH com-ponent types with different addressing scheme: Fig. 15 Parallel FLASH (e.g. Spansion ™) on netX10 in 8 Bit and 16 Bit configuration

Fig. 16 Parallel FLASH (e.g. INTEL ™) on netX10 in 8 Bit and 16 Bit configuration

MEMSR_WEn

MEMSR_CSinMEMSR_OEn

MEM_D15-0

MEM_A23-1

CSOEWEBYTE

RESETWP

+3.3V

D15-0

+3.3V

FLASH 8Mx16

MEMSR_WEn

MEMSR_CSinMEMSR_OEn

MEM_D7-0

MEM_A23-1 A22-0

CSOEWEBYTE

RESETWP

D7-0

+3.3V

FLASH 8Mx16

D15/A-1

PORn

MEM_A0A22-0

PORn

MEM_A0

(e.g. S29GL128) (e.g. S29GL128)

D14-8

netX10 netX10

MEMSR_WEn

MEMSR_CSinMEMSR_OEn

MEM_D15-0

MEM_A23-1

CSOEWEBYTE

RPVPEN

+3.3V

D15-0

+3.3V

FLASH 8Mx16

MEMSR_WEn

MEMSR_CSinMEMSR_OEn

MEM_D7-0

MEM_A23-0 A23-0

CSOEWEBYTE

RPVPEN

D7-0

+3.3V

FLASH 8Mx16

PORn

A22-1

PORn

MEM_A0

(e.g. TE28F128J3) (e.g. TE28F128J3)

A0

D15-8

netX10 netX10



2.8.1.3 Connecting SRAM Standard SRAM components usually either work with Byte addresses, with address line A0 used for Low- High Byte selection (8 Bit devices) or with 16 Bit addresses and two Byte Enable signals for Low and High Byte selection (16 Bit devices). The following schematics show the proper wiring for each of these component types: Fig. 17 8-Bit SRAM on netX10

Fig. 18 16-Bit SRAM on netX10

netX 10 SRAM

Chip Select

Read Control

Write Control

Ready/Wait***

Data[7:0]

*MEMSR_CSin

MEMSR_OEn

MEMSR_WEn

***HIF_RDY

MEM_D[7:0]

***

***

: i = 0,1,2,3: may be smaller: optional

Address[23:0]****MEM_A[23:0]

netX 10 SRAM

Chip Select

Read Control

Write Control

Ready/Wait***

Data[15:0]

*MEMSR_CSin

MEMSR_OEn

MEMSR_WEn

MEMSR_RDY

MEM_D[15:0]

***

***

: i = 0,1,2,3: may be smaller: optional

Address[22:0]****MEM_A[23:1]

MEM_A0 Low-Byte Enable

High-Byte EnableMEM_DQM1



2.8.2 SDRAM Interface

2.8.2.1 Basics and Performance Considerations SDRAM is an acronym for Synchronous Dynamic Random Access Memory and defines memory com-ponents with a parallel and separate address and data bus, where all signals are always related to a clock signal (-> synchronous) provided by the SDRAM controller. SDRAMs are organized in banks, rows and columns, whereas row and column addressing happens in separate steps using the same address lines and seperate control signals for row (RASn = Row Address Strobe) and column (CASn = Column Address Strobe) addressing. All memory locations with the same row address are referred to as an SDRAM page which, depending on the components capacity, has a size of 256 to 2K (2048) data words, with the data word size being identical to the components data bus width (4, 8, 16 or 32 Bit). Typically SDRAM components provide four banks, while two banks are also possible. To access a certain data word of an SDRAM, the corresponding memory page needs to be opended first, which is done by an ACTIVATE command. Once the page has been opened, data within this page may be accessed by READ or WRITE commands, while READ data will always be provided by the SDRAM after a fixed number of SDRAM clock cycles (100 MHz with netX) determined by the “CAS-Latency” (CL) of the SDRAM component which typically has a value of either 2 or 3. To reduce the overhead of SDRAM accesses and improve data throughput, SDRAM components sup-port burst accesses that always transfer a predefined number of consecutive data words with the maximum possible speed of one data word per clock cycle. Depending on the data bus width of the SDRAMS (8 or 16 Bit), the netX10 memory controller always works with a burst length of 8 (8 Bit) or 4 (16 Bit) data words: Fig. 19 Consecutive read accesses within same memory page

When two consecutive accesses are directed to memory locations in different pages, the active page needs to be closed by a PRECHARGE command, followed by an ACTIVATE command to open the new page, which significantly increases the resulting data access time: Fig. 20 Consecutive read accesses to different memory pages

SDRAM Clock

Command

Bank addr

Row/Col addr

Data

pre

ba

nop activ read nop

ba ba

ra caA

dA0

nop nop nop nop

ba

caB

read nop

CAS latency 2 read data A

nop nop

dA1 dA2 dA3 dB0 dB1 dB2 dB3

nop

CAS latency 2 read data B

nopnop

SDRAM Clock

Command

Bank addr

Row/Col addr

Data

pre pre

ba ba

nop activ nop read activnop nop

ba ba ba

raA caA raB

dA0

nop nop nop nop

ba

caB

read nop

CAS latency 2

nop nop nop nop

dA1 dA2 dA3

nop

dB0 dB1 dB2 dB3

nop

read data A read data BCAS latency 2



While it is desirable to mostly keep consecutive accesses within the same memory page, this is of course not always feasible. However, page changes can be reduced by making use of the different banks of an SDRAM, since a page of a different bank can already be opened by the memory controller while the current access is still in progress by sort of interleaving the accesses: Fig. 21 Consecutive read accesses to different memory banks

SDRAM Clock

Command

Bank addr

Row/Col addr

Data

pre

baA

nop activ read nop

baA baA

raA caA

dA0

nop nop nop nop

baB

caB

read nop

CAS latency 2 read data A

nop nop

dA1 dA2 dA3 dB0 dB1 dB2 dB3

nopactiv

baB

raB

pre

baB

CAS latency 2 read data B



2.8.2.2 Controller Features The SDRAM controller can drive all SDRAM Single Data Rate Types from 16 MBit to 512 MBit, provid-ing a (not completely used) 1 GByte address space from 0x80000000 to 0xBFFFFFFF. The SDRAM controller is equipped with 8 Byte read and write caches which are always active. The following parameters can be set: • Number of banks 2, 4 • Number of rows 2k, 4k, 8k, 16k • Number of columns 256, 512, 1k, 2k, 4k • Data bus width 16 or 8 Bit • Refresh-mode fixed or collect up to 8, 16 or 2047 refresh cycles • Power save mode SDRAM-Self-refresh-Mode with disabled clock

switch on / off SDRAM Controller The SDRAM data bus width can be either 8 or 16 Bit. In order to achieve maximum memory perform-ance, the use of 16 Bit is recommended. However, when DPM in serial mode (SPI) is used, only 8 Bit memory may be connected. The following table shows some supported memory combinations up to 128 MBytes total memory.

SDRAM Memory Size

Organization Number of Chips Configuration Total Memory Size

16 Mbit 1 Mbit x 16 1 1 x 16 2 MB

64 MBit 8 Mbit x 8 1 1 x 8 8 MB

8 MBit x 8 2 2 x 8 16 MB 4 MBit x 16 1 1 x 16 8 MB

128 MBit 16 Mbit x 8 1 1 x 8 16 MB 16 Mbit x 8 2 2 x 8 32 MB 8 MBit x 16 1 1 x 16 16 MB

256 MBit 32 MBit x 8 1 1 x 8 32 MB 32 MBit x 8 2 2 x 8 64 MB 16 MBit x 16 1 1 x 16 32 MB

512 MBit 64 MBit x 8 1 1 x 8 64 MB 64 MBit x 8 2 2 x 8 128 MB 32 MBit x 16 1 1 x 16 64 MB

Table 3: SDRAM setups

Notes: 1) If more than one memory device is connected (e.g two 8 Bit SDRAMs instead of one 16 Bit compo-

nent or SDRAM and parallel FLASH or SRAM), the allowed maximum load capacity (data signals: max. 15 pF, control signals max. 10 pF) has to be considered, to ensure stable operation through-out the whole temperature and operating voltage range!

2) Although the SDRAM controller basically supports 4-chip configurations (using 4-Bit SDRAMs),

such configurations will most likely exceed the maximum allowed load capacity on the address- and control signals and are hence not listed here.

3) 1 MB corresponds to 1024 * 1024 Bytes = 1048576 Bytes



2.8.2.3 SDRAM Parameters The SDRAM Controller runs with the 100 MHz system clock. There are a few parameters which have to be configured, according to the SDRAM components used. These are listed in the following table:

Parameter Description Value Dimension Trcd ACTIVE to READ or WRITE delay / RAS to CAS delay

1-3 CYC

Twr WRITE recovery time

1-3 CYC

Trp PRECHARGE command period time

1-3 CYC

Tras ACTIVE to PRECHARGE command time

3-10 CYC

Trfc REFRESH to command time / AUTO REFRESH period

4-19 CYC

Trefi Average periodic refresh interval 3.9 7.8 15.6 31.2

µs

CAS Latency CAS Latency 2-3 CYC

Table 4: SDRAM timing parameters

For details on the SDRAM configuration registers, please consult the “netX10 Program Reference Guide”. Further timing information on the SDRAM interface can be found in chapter 3.4.7 of this docu-ment.



2.8.2.4 SDRAM Timing The following diagrams demonstrate the SDRAM parameters:

Fig. 22 SDRAM read cycle

Fig. 23 SDRAM write cycle



2.8.2.5 Connecting SDRAM The following schematics show how to connect SDRAM to the netX10 memory interface. Fig. 24 8-Bit SDRAM on netX10 16-Bit SDRAM on netX10

Fig. 25 2 x 8-Bit SDRAM on netX10

netX10

MEMDR_CSnMEMDR_WEn

MEMDR_CKEMEMDR_CLK

MEMDR_RASnMEMDR_CASn

MEMDR_DQM0

MEM_D7-0

MEM_A12-0MEMSR_A14MEMSR_A15

MEM_DQM1

A12-0BA0BA1

RASCASCSWEDQM

CLKCKE

D7-0

netX10

MEMDR_CSnMEMDR_WEn

MEMDR_CKEMEMDR_CLK


MEMDR_DQM0

MEM_D15-0


MEM_DQM1 DQMH

A12-0BA0BA1

RASCASCSWEDQML

CLKCKE

D15-0

SDRAM 64Mx8 SDRAM 32Mx16

MEM_D15-8

netX10

MEMDR_CSnMEMDR_WEn

MEMDR_CKEMEMDR_CLK


MEMDR_DQM0

MEM_D7-0


MEM_DQM1

A12-0BA0BA1

RASCASCSWEDQM

CLKCKE

D7-0

DQM

A12-0BA0BA1RASCASCSWE

CLKCKE

D7-0



2.9 Dual-Port memory interface

2.9.1 Introduction

The Dual-Port Memory (DPM) interface allows data transfer between the netX chip and an external host system. Unlike standard DPM components, the netX DPM is rather a virtual Dual-Port memory, which appears as a linear memory to the host side, while accesses to the DPM are redirected to one or up to four different memory areas, located anywhere within the complete netX memory map, including also register areas, which allows a completely programmable and hence fully firmware specific Dual-port memory structure. The DPM memory size is configurable and the interface can either operate as a par-allel DPM interface based on standard SRAM access protocol or a high speed serial DPM interface based on standard Motorola SPI. In parallel mode, up to 41 signals are used for data bus, address bus and control signals, including an optional and widely configurable Ready/Busy/Wait/Acknowledge signal and two IRQ signals. The following list provides an overview of the Dual-port memory features. • Programmable DPM size (2/8/16/32/64/128 K) with a relocatable 256 Byte control and configuration

block maintaining host-software compatibility to existing netX50/100/500 products. • Up to four configurable (size and location) DPM memory areas, that can be mapped to different

areas of netX memory space. • Support for 8- or 16 bit parallel mode (SRAM like interface) and serial mode (SPI). • Support for multiplexed or non-multiplexed data bus (16 Bit only). • Configurable and optional Ready/Busy/Acknowledge signal to minimize parallel access time. • Optional input signal filter (tolerates hazards <10ns). • Configurable Read Data Setup time (n * 10ns; n =0..7). • Configurable endianess (little endian or 16 Bit big endian) • Up to sixteen handshake register pairs with programmable register width of 8 or 16 bit. • Access to DPM interface configuration paramters from host side • Configurable Write-Byte-collect functionality to minimize netX internal bus load and provide access

to only 32bit accessible memory areas (e.g certain registers). • Configurable Read-ahead functionality to speed up accesses to consecutive addresses. • Enhanced Read Burst detection (host may change address without toogling Chip Select and Read

singals). • Two independent IRQ signals (netX to host) Note: Like all other digital I/Os of the netX10, the DPM interface uses 3.3V signaling voltage and can NOT be made 5V tolerant (like netX500/100)!



Fig. 26 netX10 DPM interface block diagram

DPM

AHBmasterchannelto netXlogic

DPM_A

DPM_DQMN

DPM_CSN

DPM_RDN

DPM_WRN

DPM_D

DPM_RDY

DPM_SIRQ

DPM_DIRQ

access startdetection

DPM_MODE

DPM_MODEaddress

andcontrol

data

DPM_MODE

access start

access start

IRQsfrom netXinternallogic

netxversion

data

address

control

readygeneration

serial DPM to parallel DPM protocol converter

Address windowmapping

high speed Serial Port Interface (SPI) slave

IO inputsampling

and outputgeneration

parallel DPMbyte enablegeneration

Byte collectingEndianess datamapping

access errordetection

asyn

chro

nous

IO s

harin

g an

d sw

itchi

ng

IRQ generation

DPM configuration andstatus registers read ahead

accessgeneration

AHBaccess

generationto netXlogic

Addresswindow

detection

unlock

firmwarestatus

alternativeWindowmappingfrom Triple-Buffer-Manager



The netX10 DPM interface supports 3 different parallel modes and a high speed serial mode based on standard Motorola SPI. Selection of either serial or parallel DPM (default is parallel) is done through register HIF_IO_CFG, located in the netX10 HIF_IO_CTRL memory area. All further interface parameters like parallel mode data width, data endianness, address mapping, signal timing, interrupt handling and PIO control can be accessed by the host processor. By default, all DPM configuration registers are mapped to the first 256 bytes (address 0x00 to 0xFF) of the external DPM address range. The default bus width is 8 Bit and all basic configuration registers only use the Least Significant Byte which allows host processors with 8-Bit interface as well as pure 16-Bit (no Byte access possible) hosts to access the DPM configuration and adapt the interface to their needs (e.g bus width, RDY/BUSY signal modes, endianness, etc.) without the need for pre-configuration by firmware or sec-ond stage loader (which is still possible though). For netX50 compatibility this configuration area can be relocated to the end of the external address range (last 256 bytes) or completely switched off. Depending on DPM mode, bus width and address range, there are almost always a number of host interface signals which are not used by the host and can be used as Programmable IOs (PIO). Unsurprisingly the serial DPM mode provides the most available PIOs, hence the serial mode should be considered for applications requiring a large number of I/Os or external memory or where the host proc-essor signal count is limited. The serial mode does not necessarily provide lower performance than a parallel mode and may even be faster than a slow parallel interface (8Bit, no RDY/BUSY signal sup-port). Supported DPM modes are:

DPM mode Comment PIOs

8bit SRAM Standard 8bit SRAM interface with active low control signals. 16 1) 2) 3)

16bit SRAM Standard 16bit SRAM/Intel interface with 2 byte enables. 7 1) 2) 3) 4)

16bit muxed 16 bit mode with multiplexed address-data-bus to connect netX10 to hosts like TI OMAP family.

23 1) 2) 3)

serial (SPI) Motorola Serial Port Interface (CPOL=0,1; CPHASE=0,1) 41 1)

Table 5: DPM modes

Notes: 1. One (two) further PIO can be used if only one (no) interrupt signal DPM_DIRQ

(DPM_DIRQ and DPM_SIRQ) is used (Fehler! Verweisquelle konnte nicht gefun-den werden.).

2. One additional PIO can be used if no ready signal DPM_RDY is used.

3. In parallel modes additional PIOs are available if smaller external address range is configured.

4. 16 bit mode providing 16 bit addresses and 2 byte-enable signals is similar to 16 bit mode providing byte addresses and byte-high-enable (sometimes named as Intel-mode). Byte address bit 0 is equal to low-byte enable then.



2.9.2 Parallel DPM interface modes

All netX10 DPM interface modes based on standard SRAM type access provide a data bus (8 or 16 Bit), an address bus (up to 17 Bit) and active low control signals for read, write, chip-select and byte enable. Additionally there is one widely configurable Ready/Busy/Wait/Acknowledge signal. Further, a multiplexed address-data mode is supported to connect netX10 to TI OMAP or related hosts. The netX10 DPM interface provides many error detection and correction features, which include:

• Detection of illegal signal states: • write signal becomes active during read access. • read signal becomes active during write access. • unstable address signals during address sample phase.

• Detection of access errors: • accesses that were terminated by the host before the netX10 DPM was ready. • timeouts (DPM can’t execute access and runs into timeout).

• Correction of design or environment related issues: • noisy signal lines

(acomplished by activating a signal filter -> increases access time). • unstable address signals at beginning of access

(acomplished by delaying the address sample point by 10, 20 or 30ns. -> increases setup time) • cross-talk problems (level change on data lines due to read access influences address signals).

acomplished by delaying output driver activation (10ns after address sampling) during read ac-cesses (feature is always enabled)

When read access errors are detected, the associated DPM address is logged to a register to allow further investigation of the problem. Further, an IRQ can be generated.



2.9.2.1 8 Bit Standard SRAM DPM mode Interface Signal netX10 signal Comment

Address DPM_A16..0 depending on DPM size, some upper address lines may be unused

Chip-select DPM_CSn active low

Read Control DPM_RDn active low

Write Control DPM_WRn active low

Ready DPM_RDY optional in most applications but always recommended

Data lines DPM_D7..0

Initial Config. Access Byte access to 0x0

Table 6: 8 Bit DPM mode signals

Fig. 27 Connecting Host CPU in 8 Bit standard SRAM mode

Host CPU netX10

Address[16:0]

Chip Select

Read Control

Write Control

Ready/Busy/Wait

Data[7:0]

DPM_A[16:0]

DPM_CSN

DPM_RDN

DPM_WRN

DPM_RDY

DPM_D[7:0]

DPM_DIRQ

DPM_SIRQ

PIO

MEM_A[23:17]

DPM_D[15:8]

PIO



2.9.2.2 16 Bit Standard SRAM DPM mode Interface Signal netX10 signal Comment

Address DPM_A16..0 Byte addresses.depending on DPM size, some upper ad-dress lines may be unused




High Byte Enable DPM_BHEn active low


Data lines DPM_D15..0

Initial Config. Access Byte or 16bit access to 0x0

Table 7: 16 Bit DPM mode signals (INTEL™style host CPU)

Fig. 28 Connecting host CPU (Intel™type interface) in 16 Bit standard SRAM mode

Host CPU netX10

Address[16:0]

Chip Select

Read Control

Write Control

Ready/Busy/Wait

Data[15:0]

DPM_A[16:0]

DPM_CSn

DPM_RDn

DPM_WRn

DPM_RDY

DPM_D[15:0]

DPM_DIRQ

DPM_SIRQ

MEM_A[23:17]PIO

Byte High Enable DPM_BHEn



Host processors may have a slightly different interface, using word (16 Bit) adresses and two Byte En-able Signals for Low- and High Byte selection. This is functionally identical to the Intel™ type interface while simply using a different signal naming scheme: Interface Signal netX10 signal Comment

Address DPM_A15..1 Word (16 Bit) addresses.depending on DPM size, some upper address lines may be unused

Chip-select DPM_CSn active lowRead Control DPM_RDn active lowWrite Control DPM_WRn active lowLow Byte Enable DPM_A0 active lowHigh Byte Enable DPM_BHEn active lowReady DPM_RDY optional in most applications but always recommendedData lines DPM_D15..0 Initial Config. Access Byte or 16bit access to 0x0

Table 8: 16 Bit DPM mode signals

Fig. 29 Connecting host CPU in 16 Bit standard SRAM mode

The following table provides an example, explaining the addressing schemes, assuming that the first Dword of the internal memory mapped to the beginning of the DPM contains the data: 0xDDCCBBAA. External DPM address,

A(16:0) Access width BHEn signal - Data

0x0000 Byte Access 1 - 0xAA 0x0001 Byte Access 0 - 0xBB 0x0000 Word Access 0 - 0xBBAA 0x0002 Word Access 0 - 0xDDCC

External DPM address,

A(16:1) Access width BHEn

(Byte Enable 1) A0

(Byte Enable 0) Data

0x0000 Byte Access 1 0 0xAA 0x0000 Byte Access 0 1 0xBB 0x0000 Word Access 0 0 0xBBAA 0x0001 Word Access 0 0 0xDDCC

Table 9: 16 Bit DPM mode addressing

Host CPU netX10

Address[15:0] / [16:1]

Chip Select

Read Control

Write Control

Ready/Busy/Wait

Data[15:0]

DPM_A[16:1]

DPM_CSn

DPM_RDn

DPM_WRn

DPM_RDY

DPM_D[15:0]

DPM_DIRQ

DPM_SIRQ

MEM_A[23:17]PIO

Byte Enable 1 DPM_BHEn

DPM_A0Byte Enable 0



2.9.2.3 16 Bit Multiplexed DPM mode The netX10 DPM interface also supports a 16 Bit Multiplexed Mode, using the data bus (D15-0) alter-natingly for address and data. Though this mode was designed to connect host processors with a GPMC (Texas Intruments™) interface (e.g. OMAP 35xx) other processors with a similar interface may be used as well. This mode expects Word (16 Bit) adresses on D15-0, while the DPM interface inter-nally routes the address Bit on D0 to A1, D1 to A2, etc. Low / High Byte selection is done through DPM_A0 and BHEn like with the other 16 Bit modes. Interface Signal netX10 signal Comment

Multplexed address A16-1 / data D15-0

DPM_D15..0

nADV DPM_A1 Low: valid address on D15-0. High: D15-0 used as Data bus




Low Byte Enable DPM_A0 active low

High Byte Enable DPM_BHEn active low


Initial Config. Access Byte or 16bit access to 0x0

Table 10: 16 Bit DPM multiplexed mode signals

Fig. 30 Connecting host CPU in 16 Bit multiplexed mode

Host CPU netX10

Chip Select

Read ControlWrite Control

Ready/Busy/Wait

Addr[16:1] / Data[15:0]

DPM_CSn

DPM_RDn

DPM_WRn

DPM_RDY

DPM_D[15:0]

Low Byte enable DPM_A[0]

nADV DPM_A[1]

High Byte enable DPM_BHEn

optional

DPM_DIRQ

DPM_SIRQ

MEM_A[23:17]PIO

DPM_A[16:2]PIO



2.9.3 Serial (SPI) DPM interface mode

Beneath the three parallel modes, the netX10 DPM also provides a serial mode where the DPM inter-face behaves like a Standard SPI slave device and directly translates the external serial accesses to internal parallel accesses. The serial mode should always be considered when the host processor has limited I/O ressources and could only provide an 8 Bit parallel host interface (while working with 32 or 16 Bit internally) or when additional external memory is to be connected to the netX10, since the serial mode ist the only DPM mode that allows parallel use of the DPM and the memory interface (8 Bit only). Applications requiring a large number of I/O signals on the netX10 would also benefit from using the serial mode, since it provides a total of at least 41 PIO signals. In serial mode, the two IRQ signals are internally routed to other DPM signals than in the parallel modes, to allow the parallel use of the external memory controller. Interface Signal netX10 signal Comment

SPI Clock DPM_D11 DPM_SPI_CLK

SPI Chip Select DPM_D10 DPM_SPI_CSn

SPI Master Out / Slave In DPM_D9 DPM_SPI_MOSI

SPI Master In / Slave Out DPM_D8 DPM_SPI_MISO

Interrupt DPM_D12 DPM_SPI_DIRQ

Interrupt DPM_D13 DPM_SPI_SIRQ

Table 11: Serial DPM mode signals

Fig. 31 Connecting host CPU in serial mode

Host CPU

netX10

Chip Select

SPI MISO

SPI MOSI

DPM_SPI_CSN / D10

DPM_SPI_MISO / D8

DPM_SPI_MOSI / D9

DPM_SPI_DIRQ / D12

Serial Clock DPM_SPI_CLK / D11

DPM_SPI_SIRQ / D13



2.9.4 DPM Signal Timing The following subchapters describe the functional timing of the DPM interface signals without regarding signal input and output delays. For rough estimation, input signal delay can be set at 2ns and output delay at 5ns (at 30pF capacitive signal load). Please check the appropriate subchapters in the Electrical Specification section of this document for detailled timing information.

2.9.4.1 Non multiplexed parallel modes Write Access Like with typical SRAM, a DPM write access is triggered at cycle end by the positive edge of DPM write enable signal. For relaxed requirements concerning device implementation on PCB and ASIC synthe-sis, all write access related signals (data, address byte-enables and chip-select) must be valid and stable 1.0 system clock cycle before the positive edge of the write enable signal (address, data and chip-select setup time). No signal multi-cycle-hold-times related to the positive edge of write enable signal are required. Fig. 32 Parallel DPM write cycles

Notes: This example does not apply when using the write-byte-collect feature.

During the first write access (A0) in the example shown above, the DPM is internally idle. Hence Ready signal remains in Ready-State and the access can be finished by the host device by releasing write-enable signal WRn. The second write access (A1) immediately following A0, finds the netX DPM Inter-face internally busy, still running the first write access. Hence DPM Ready signal is set to busy state. It is released to ready state when the DPM has finished the internal write access and is ready to handle the next external access.

Ready

WRn

Address, BEn

Data

CSn

minnWR time:

1 sysclk

internal system clock

DPM internal currentaccess related cycles

A0

Systemrequest cycle

(write)

Address mapcycle

Ready gen.cycle (write)

Address mapcycle

netX internal busy:stretched write cycle

RDn

idle

0.5 to 1.5 sysclks sampling window

idle

D0 AHB Datacycle (0 WS)

netX internal systemaccess (AHB) cycles

A0 AHB req.cycle (write)

Systemrequest cycle

(write)



A1 AHB req.cycle (write)idle idleidle idle idle

idle

idle

ready busy ready

D0

minidle time:1 sysclk

A1

D1

idle



Sampling and detecting the positive edge of write-enable signal requires 1.5 to 2.5 system clock cycles. Due to address setup time address-map-cycle is already done while write-enable edge detection is run-ning. After detection of a positive write-enable edge internal AHB access generation is started, which always takes at least one system clock cycle when the access goes to INTRAM areas (AHB cycle may be extended, when accessing other, non-zero-waitstate areas). Externally, the time between ending the first write access and findign the DPM Ready again, is 3.5 to 4.5 system, clock cycles in that case. The signal timing shown in the example above is the fastest possible timing for write accesses. The following conditions will extend the accesses by additional system clock cycles:

• Prior access targets internal non-zero-waitstate address areas and is still active. • Programmable Signal filtering is activated. • Programmable Address-Setup timing parameter tosa is not 0.

Read Access A standard DPM read access is initiated when both, chip-select (CSn) and read-enable (RDn) signals are driven low by the host device and takes 1.5 to 2.5 system clock cycles to be detected. On detection of a read access, address mapping is already done and an internal AHB read access, consisting of AHB request cycle and AHB data cycle, follows immediately. On each external DPM access, the internal AHB cycle always fetches the complete corresponding Dword (32 Bit), which speeds up any following read accesses to the other Bytes of this Dword (8 Bit access) or the other word of this Dword (16 Bit access), reduces internal bus load and provides data consistency when reading 32 Bit Registers or data fields. The latched bytes are discarded, when:

• the following access is a write access • the address of the following read access is outside the current Dword Boundary • a latched byte or word is read twice (access to the same address as one of the previous reads)

This Read-Data-Latching feature can not be disabled and must be regarded when accessing the DPM interface, to avoid reading data that is possibly outdated.

Note: Though the following examples that show the effect of the Read-Data-Latching are all based on accesses to consecutive addresses, this is not a precondition for Read-Data-Latching. The order in which single Bytes or Words of a latched Dword are read by the host is actually not relevant for the effect of this feature.



Fig. 33 Parallel DPM read cycles

Note: This example does not apply to sequential accesses (Byte or Word) within the same Dword boundary or to consecutive Dword addresses when using read-ahead feature!

The following figure shows sequential 16 Bit read accesses to consecutive addresses where the effect of the Read-Data-Latching feature automatically comes into play: Fig. 34 Parallel DPM 16 Bit read cycles (read-data-latching)

By enabling the Read-Ahead feature, consecutive accesses can be further accelerated: Fig. 35 Parallel DPM 16 Bit read cycles (read-data-latching and read-ahead)

Ready

WRn

Address, BEn

Data

CSn, RDn

min access time no read ahead or read ahead mismatchto 0 wait state netX address: 4.5 sysclks


additional address setup timetOSA programmable

additional read data setuptime tRDS programmable



idle idle idle

D0

rd

A0


idle

idle

Systemrequest cycle

(read)

Address mapcycle

Ready gen.cycle (read)


A0 AHB req.cycle (read)idle

busy ready busy

Systemrequest cycle

(read)

Address mapcycle



A0 AHB req.cycle (read)idleidle

idle idle idleidle

ready

D1

A1

idle

idle

Ready

WEn

Address

Data

CSn, OEn

current access

A0

D.A0

idle

A1=A0+2

external DPM interface

netX internal cycles

idleAHBaddrcycle

signalsampl.

addrmap

AHBdatacycle

signalsampl.

addrmap

D.A1

A2=A0+4

D.A2

idleAHBaddrcycle

signalsampl.

addrmap

AHBdatacycle

Ready

WEn

Address

Data

CSn, OEn

A0

D.A0

A1=A0+2

D.A1


A2=A1+2

D.A2



Burst Read Access The netX10 DPM interface also supports read bursts, which are sequential read accesses (not neces-sarily to consecutive addresse) where CSn and RDn signals remain active while the address changes with each new access. Address change detection requires 1.5 to 2.5 system clock cycles. After detect-ing address change, the DPM interface waits for new address being stable for 1 clock cycle before address change is treated as start of new access. During the access-start-cycle within a read burst the following tasks are performed: address-mapping, read-ahead-match-detection and appropriate ready-generation. DPM_RDY remains in ready-state when requested data is already available. Otherwise it is set to busy-state (e.g. read-ahead-mismatch oc-curred or prior internal access is not finished yet due to wait-states). The following figure shows sequential 8 Bit burst read accesses to consecutive addresses where the effect of the Read-Data-Latching feature automatically comes into play: Fig. 36 Parallel DPM 8 Bit burst read cycles (read-data-latching)

Of course, also burst accesses may benefit from the Read-Ahead feature. In the example above, the pause between D.A3 and D.A4 would disappear when Read-Ahead was enabled.

WEn

Address

Data

CSn, OEn

current access

A0 A1=A0+1


netX internal cycles

AHBaddrcycle

signalsampl.

addrmap

AHBdatacycle

signalsampl.

addrmapidle

D.A0

A2=A0+2

signalsampl.

addrmapidle

A3=A0+3

signalsampl.

addrmapidle idle

AHBaddrcycle

signalsampl.

addrmap

AHBdatacycle

D.A1 D.A2

A4

D.A3 D.A4

A5

signalsampl.



2.9.4.2 Multiplexed parallel mode In multiplexed mode, an access consists of an address phase (where data lines DPM_D15-0 are used to transmit the 16-Bit address), followed by a data phase. During the address phase, an active ADVn signal indicates there is a valid address on the data bus which is sampled by the DPM interface. Adress data must be stable for at least one system clock cycle before ADVn becomes inactive. When the ADVn signal has become inactive, the bus is used for read- or write-data and the rest of the access is now similar to the non-multiplexed mode. Write Access Fig. 37 Multiplexed mode DPM write cycles

The signal timing shown in the example above is the fastest possible timing for multplexed mode write accesses. The following conditions will extend the accesses by additional system clock cycles:

• Prior access targets internal non-zero-waitstate address areas and is still active. • Programmable Signal filtering is activated. • Programmable Address-Setup timing parameter tosa is not 0.

Ready

nWR

nBE, A0

Address/Data

nCS

minnADV time:

1 sysclk



netX internal busy:stretched write cycle

nRD


nADV

minnWR time:1 sysclk


Systemrequest cycle

(write)

Address mapcycle

A0[16:1]


Address mapcycleidle idle


A0 AHB req.cycle (write)

Systemrequest cycle

(write)


A1 AHB req.cycle (write)idle idleidle idle idle

idle idle

ready busy ready

D0

valid

D1A1[16:1]

valid

idle

idle


idle

idle



Read Access Fig. 38 Multiplexed mode DPM read cycles

The signal timing shown in the example above is the fastest possible timing for write accesses. The following conditions will extend the accesses by additional system clock cycles:

• Prior access targets internal non-zero-waitstate address areas and is still active. • Programmable Signal filtering is activated. • Programmable Address-Setup timing parameter tosa is not 0. • Programmable Read-Data-Setup timing parameter trds is not 0.

Ready

nWR

nBE, A0

Address/Data

nCS

min access time no read ahead or read ahead mismatchto 0 wait state netX address: 5.5 sysclks




idle idle idle

D0

ready

valid


idle

idle

Systemrequest cycle

(read)

Address mapcycle



A0 AHB req.cycle (read)idle

busy ready

Address mapcycle

idleidle

idle idle idleidle

busy

valid

Sysreq.

A1req

AHB

nRD

nADV

A0[16:1]

idle

idle

idle

idle

min nADV time: 1 sysclk


A0[16:1]

idle

idle



2.9.4.3 Ready / Busy signal The DPM_RDY signal allows the netX to extend the current DPM access cycle until the requested data is available (read) or write data has been accepted (signal is only available in parallel DPM modes). The signal mode and polarity, as well as the drive mode, are programmable: Signal modes: • WAIT/BUSY mode, active low • WAIT/BUSY mode, active high • READY/ACK mode, active low • READY/ACK mode, active high Drive modes: • High Impedance output • Push-Pull output • Sustained Tri-state output • Open Drain / Open Source (depends on the configured polarity) After power up, the DPM_RDY pin will be configured as PIO input (high impedance state) until config-ured otherwise. In push-pull mode, the signal is always driven. In Open Drain / Open Source mode the signal will be driven only during its active state, hence it is necessary to use external pull-up or pull-down resistors for maintaining a valid inactive signal level when the DPM_RDY is not active. The sus-tained tri-state output mode works similar to the Open Drain / Open Source output mode, however the signal remains being driven when entering the inactive state for one cycle before entering the high im-pedance state. This provides a faster signal edge than it could be achieved by a pull-down or pull-up resistor, while the signal may still be shared with other components. In WAIT/BUSY mode, an active signal means, that the netX DPM is not yet ready and the host needs to extend the access. In READY mode an active signal means that the netX DPM is ready and the host may terminate the access. However, the READY mode is not just a negation of the WAIT mode (see the following diagram for the difference between WAIT/BUSY and READY) When in WAIT/BUSY mode, the DPM_RDY signal will always become active on a read access, while single write accesses are usually accepted without activating the signal. Further, the signal will be acti-vated asynchronously. In READY mode, the signal will be activated on any access. An internal counter ensures, that the access time will not exceed 20.48 µs (2048 clock cycles), which would occur if an access from host side is mapped into external netX memory which will be always sig-naling not ready (e.g. unconfigured or powered down SDRAM). In such cases, the current access will be aborted after 20.48µs, allowing the host processor to end the cycle, which prevents system lock up conditions at the host side. Such a timeout event will be logged in the access error register and can generate an IRQ to the host processor.



The following diagrams provide an overview on the different DPM_RDY signal and drive modes:

Fig. 39 Comparison of different modes of DPM_RDY signal

Fig. 40 DPM_RDn controlled read access and ready generation

DPM_A, DPM_DQM

DPM_D

DPM_RDY (wait/busy mode selected)

DPM_RDn

open drain, active low

push/pull and sust.tri-state, active low

A0

DPM_CSn

DPM_WRn

Data.A0

data phase

wait phase

access cycle

t_rds*10ns

DPM_RDY (ready/ack mode selected)slow release by pull up/downresistor (RC transition)

fast release by activedriven signal

push/pull and sust.tri-state, active highopen src, active low

open drain, active low

push/pull and sust.tri-state, active low

push/pull and sust.tri-state, active highopen src, active low

DPM_A, DPM_DQM

DPM_D

DPM_RDn

push/pull

high-Z

sust. tri-state

A0

DPM_CSn

DPM_WRn

open drain /src

drive inactive

Data.A0

drive inactivedrive active

high Z

high Z drive active

10ns

data phase

wait phase

access cycle

high Z

drive inactive drive active

high Z

drive inactive

t_rds*10ns

high Z drive active high Z

DPM_RDY (ready/ack mode selected)

10ns

drive inactivehigh Z drive active high Z

drive activehigh Z high Zdrive inactive


push/pull

high-Z

sust. tri-state

open drain /src



Fig. 41 DPM_CSn controlled read access and ready generation

Fig. 42 DPM_A (address change) controlled read access and ready generation

DPM_A, DPM_DQM

DPM_D

DPM_RDn

A0

DPM_CSn

DPM_WRn

drive inactive

Data.A0


high Z

high Z drive active

10ns

data phase

wait phase

access cycle

high Z


high Z

drive inactive

t_rds*10ns


10ns



push/pull

high-Z

sust. tri-state

open drain /src



push/pull

high-Z

sust. tri-state

open drain /src

DPM_A, DPM_DQM

DPM_D

DPM_RDn

A1

DPM_CSn

DPM_WRn

Data.A1


high Z

high Z drive active

10ns

data phase

wait phase

access cycle n+1

high Z

t_rds*10nst_ACD

Data.A0

A0

access cycle n

drive inactive


high Z

drive inactive


drive active

drive active

10ns

drive inactive

10ns


drive activehigh Z high Zdrive inactivedrive active drive inactive

push/pull

high-Z

sust. tri-state

open drain /src



push/pull

high-Z

sust. tri-state

open drain /src



Note: t_ACD: Address Change Detection Time: min 5ns, max 15ns Fig. 43 DPM_WRn controlled write access and ready generation

DPM_A, DPM_DQM

DPM_D

DPM_RDn

A0

DPM_CSn

DPM_WRn

drive inactive drive inactivedrive active

high Z

high Z drive active

10ns

wait phase

access cycle

high Z


high Z

drive inactive


10ns

Data.A0

datavalid

phase(10ns)



push/pull

high-Z

sust. tri-state

open drain /src



push/pull

high-Z

sust. tri-state

open drain /src



2.9.4.4 Serial mode In serial mode, the DPM interface can be accessed like a standard SPI slave component according to the SPI standard invented by Motorola™, while all four standard SPI frame formats are supported (SPI clock polarity 0 or 1, SPI clock phase 0 or 1). For a general introduction to the SPI protocol and the frame formats, see chapter xxx Since the serial DPM mode allows direct access to the DPM memory area without any software interac-tion on netX side (e.g. moving data to and from Send and Receive FIFOs), an access protocol had to be defined which is described following. Serial data is always transferred MSB first. Each transfer starts with a transfer-header and is followed by at least one data Byte to be exchanged between host device and netX. Transfer header length is 3-byte or 4-byte depending on programmed external address range (<= 64K: 3-Byte, 128K: 4-Byte). The chip select signal (SPI_CSn) is used by the DPM interface as asynchronous reset of receive and transmit logic, hence SPI_CSn must remain active throughout the complete transfer and must become inactive between sequential transfers. Serial transfers are mapped inside netX DPM interface to standard 8-bit parallel DPM accesses. Hence each transfer must provide the address to be accessed and the access type (read or write) as transfer-header information. Even using small external address range, this information takes at least 3 bytes. To avoid a huge transfer overhead by transmitting the header before each single data byte, the header is followed by a data byte stream. With each data byte, the related address is automatically incremented by one. Using external address range (DPM size) of 128K requires 4-byte instead of 3-byte header. Header size is derived form the value programmed in external address range configuration register. Default after reset is smallest supported external address range. Hence after netX10 reset always 3-byte header must be used. If external address range is configured to 128K, all headers after configuration access to external address range configuration register must be 4-byte headers. The following table shows transfer header structure depending on programmed external address range:

Address range

Byte 0 Byte 1 Byte 2 Byte 3 Byte 4

64K or less Addr. [MSB..8] Addr. [7..0] nW/R, length Data 0 (Data 1)

128K Addr [MSB..16] Addr. [15..8] Addr. [7..0] nW/R, length Data 0

The header is always generated by host device SPI interface. First 2 bytes (3 for external address range of 128K) contains address information (MSB first). These bytes are always followed by a control byte. Control byte MSB defines data transfer direction. If this bit is set, the current transfer reads data from netX, otherwise data is written to the netX. The lower 7 bits of the control byte contain transfer length information (number of bytes to be read). Read accesses through the serial DPM interface, internally always result in read ahead accesses, as otherwise it would not be possible to deliver serial read data on SPI_MISO without data polling or some kind of ready handshake mechanism. To avoid problems with access sensitive address areas (e.g. FI-FOs), the number of bytes to be read can be specified in the header, allowing to stop the read-ahead before reaching an access sensitive area. If the transfer length is set to 0, internal consecutive read accesses are done until the transfer is ended by the host by setting SPI_CSn to high level, while there will be always one internal read access beyond the last byte that was actually transferred. The length parameter is ignored for write accesses, as the number of bytes to be written simply arises from the number of bytes transferred by the host before ending the transfer.



Fig. 44 SPI DPM Read transfer, 3 byte header, undefined length (ext. address range 64K or less)

Fig. 45 SPI DPM Read transfer, 3 byte header, length=n (ext. address range 64K or less)

Fig. 46 SPI DPM Write transfer, 3 byte header (ext. address range 64K or less)

SPI_CS_N

SPI_MOSI

SPI_MISO

3 byte header

Address A0MSB to Bit 8

Address A0Bit 7 to Bit 0 1, 0000000

read databyte 0

read databyte n-2

netX internalstate idle read

byte 0

n byte data

readbyte 1

read databyte n-1

idle idle idle readbyte n-1 idle read

byte n idle

no read access length specified read ahead access to not requested address

SPI_CS_N

SPI_MOSI

SPI_MISO

3 byte header


Address A0Bit 7 to Bit 0 1, n

read databyte 0

read databyte n-2


byte 0

n byte data

readbyte 1

read databyte n-1

idle idle idle readbyte n-1 idle

read access length specified no read ahead access to not requested address

SPI_CS_N

SPI_MOSI

SPI_MISO

3 byte header


Address A0Bit 7 to Bit 0 0, xxxxxxx write data

byte 0write databyte n-1

netX internalstate idle

write databyte 1

writebyte 0 idleidle

n byte data

writebyte n-2 idle write

byte n-1



The following figure shows the general, functional timing of a read access in serial DPM mode without regarding signal input and output delays. Please check the appropriate subchapter in the Electrical Specification section of this document for detailled timing information. Fig. 47 Serial DPM read cycles

SPI-clock to system clock synchronisation takes 0.5 to 1.5 system clock cycles (2-stage synchronisa-tion) and an additional system clock cycle is required for address map cycle. Internal AHB read access takes 2 system clocks. AHB data cycle may be extended by additional wait-states depending on netX internal address area, however this is not relevant for standard DPM layout which only uses zero-wait-state areas (internal RAM and handshake-cells). Timing related path delays (i.e.: SPI clock tree and sample delay (1), SPI clock to system clock domain crossing paths (2) and SPI MISO output path (3)) take approximately 15ns (worst case conditions, i.e. 1.5 system clock cycles).

Note: Programmable timing parameters (like tosa or trds with parallel DPM) are not applicable to serial DPM and are hence not available.

SPI_CS_N

SPI_MOSI

SPI_MISO

3 byte header


Address A0Bit 7 to Bit 0 1, n

read databyte 0

read databyte n-2


byte 0

n byte data

readbyte 1

read databyte n-1

idle idle idle readbyte n-1 idle

SPI_CLK

SPI_MOSI

SPI_MISO

netX internalstate

A0bit 0

1(nW/R)

lengthbit 6

lengthbit 5

lengthbit 4

lengthbit 3

lengthbit 2

lengthbit 1

lengthbit 0

7 0last byte of header

1 2 3 4 5 6 7 0first byte of read data

system clock

idle rd.sy.2nd

read detect bySPI_CLK

read sync1st stage

Addr. mapcycle

AHB req.cycle

AHB datacycle

1

rd. databit 7

rd. databit 6

idle

1

3

2first byte data access time

insert pause tomatch first byte

data access timeif neccesary

0 1 2 3 4 5



2.9.5 DPM Interrupt Signals



2.10 Timer

The netX provides two 32-Bit Counters which can be configured to: • count from zero to a maximum value and backward (symmetric Mode) • count from zero to a maximum value and set back to zero (asymmetric Mode) • single shot or count continuously • generate an interrupt if it reaches zero • count external events • set back to zero by an external event • capture the timer value by an external event • generate a PWM signal by comparing the timer value with a threshold value As external events, any GPIO can be assigned. This can be a rising or falling edge respectively a high or low level at the GPIO by setting the inverting bit at the GPIO configuration register. The counter value can be read and overwritten any time. Fig. 48 Timer block diagram



2.11 IEEE 1588 System Time

The precision System Time derives from a counter, clocked with the 100 MHz system clock and has a resolution of 10 ns from the view of the application. Due to drift, aging or failure of the crystal this time can differ from a system wide master clock which is very often needed in Real-time Ethernet system. The System Time is not realized by a standard counter but uses an adder which increases the current time value by a programmable number (nominally10) every clock period. If the 100 MHz clock has a deviation to the master clock then the added value will slightly differ of 10 with a resolution of 2-28 ns to compensate the deviation. This can be calculated based on the protocol of IEEE 1588 or other Real-time Ethernet functions. The System Time is provided in two 32-Bit registers. One register represents the seconds and the other represents the nanoseconds from time zero. The application has to read the seconds value first, be-cause this will freeze the nanoseconds register to get a consistent System Time. Calculation of the System Time The following diagram shows how the time clock compensation works. With a clock period of ∆T =10ns the value ∆CNT = 10 will be added continuously to the System Time CNT1 to reach CNT 2 exactly at T2. If the clock runs to fast CNT2 will be reached after T2fast or if the clock is too slow, CNT2 is reached after T2slow. If ∆CNT is calculated exactly then CNT2 will be reached at T2. The procedure of an ongoing correction prevents the problems of a one step correction resulting in a large step of the System Time.

Ongoing correction of time failure



2.12 JTAG Debug Interface

2.12.1 Standard JTAG connector The netX Debug Interface is based on the Joint Test Action Group (JTAG) IEEE Standard 1149.1 and supports debugging tools, compliant with this standard. It provides two different modes of operation: ARM Debug mode and Boundary Scan mode. By default, the netX JTAG interface operates in ARM Debug mode, passing all JTAG signals to the integrated ARM CPU. See next chapter for information, on how to activate the Boundary Scan mode. The JTAG connector is a 20 pin Insulation Displacement Connector (IDC) keyed box header (2.54 mm male) that matches with IDC sockets mounted on a ribbon cable and provides the following signals:

Pin ARM Signals netX Signals Pin ARM Signals netX Signals 1 VTref +3.3V 2 Vsupply +3.3V 3 nTRST JT_TRSTn 4 GND VSS 5 TDO JT_TDO 6 GND VSS 7 TMS JT_TMS 8 GND VSS 9 TCK JT_TCK 10 GND VSS 11 RTCK Not used 12 GND VSS 13 TDI JT_TDI 14 GND VSS 15 nSRST PORn 16 GND VSS 17 DBGRQ Not used 18 GND VSS 19 DBGACK Not used 20 GND VSS

Two different reset signals are involved when using the JTAG interface of the netX: nSRST Open collector output form the ICE to the target system reset. This is also an input to the ICE so that a reset initiated on the target can be reported to the debugger. nTRST Open collector output from ICE to the reset signal on the netX JTAG port. The target board must include a pull-up resistor on both reset signals.

JTAG Interface with voltage supervisor chip (i.e. MAX 823).



2.12.2 Boundary Scan mode Besides the (default) ARM Debug mode, the netX10 JTAG interface also supports a second mode, allowing the user to run Boundary Scan tests on the netX10, by the use of appropriate (third-party-) tools. To activate the Boundary Scan mode, refer to the following table, indicating the required state of certain netX signals: Signal Pin number State BSCAN_TRSTn G3 High JTAG_TRSTn L4 Low TEST C7 Low BIST_TRSTn M11 Low

The pins of the TEST and BIST_TRSTn signals are equipped with internal pull-down resistors and can hence simply be left unconnected. The same applies to JTAG_TRSTn, however external circuits may provide an external pull-up resistor, so this signal may have to be pulled low by the test system. Since the JTAG interface of the internal ARM CPU and the TAP controller share the same JTAG interface signals, the ARM JTAG interface must be held in reset state (JTAG_TRSTn = low) while using the Boundary Scan feature! Due to the digital nature of Boundary Scan, some (analog-) netX pins can inherently not be controlled by Boundary Scan, while others are involved in the scan mode itself and are hence not accessible ei-ther. This applies to all power pins (VSS, VDDIO, VDDC), as well as all pins of the Ethernet PHY, the USB port, the JTAG port, all test pins (TEST, TMC1, TMC2, BIST_TRSTn), all oscillator-pins and of course the BSCAN_TRSTn signal. For further details please consult the appropriate netX10 BSDL file, which will be available for download from the Hilscher website as soon as published. .



2.12.3 Embedded Trace Macrocell ETM The ETM is a Real-Time trace module capable of instruction and data tracing. The ETM is an integral part of the ARM microcontroller and works with special debug tools like the Hitex Tool chain for ARM. The ETM comprises the following main components: Trace port Output signals that help to understand the operation of the processor. Triggering and filtering facilities An extensible specification enables to control tracing by specifying the exact

set of triggering and filtering resources required for particular application. Re-sources include address comparators and data comparators, counters and sequencers.

The netX contains the ETM9 Rev 2a (ETM Architecture ETMv1.3) in medium configuration. The connector for the ETM is standardized by ARM. Further information is available at www.arm.com. It is highly recommended to implement accordingly otherwise the debug tools will not work correctly. The following table shows the pin assignment of the 38-pol. AMP Mictor connector 2-767004-2 as de-fined by ARM.

Pin ARM Signals netX Signals Pin ARM Signals netX Signals 1 Nc 2 Nc 3 Nc 4 Nc 5 GND VSS 6 TRACECLK ETM_TCLK 7 DBGRQ ETM_DRQ 8 DBGACK ETM_DACK 9 nSRST Not used 10 EXTTRIG 11 TDO JT_TDO 12 VTRef VCCIO 13 RTCK Not used 14 VCC VCCIO 15 TCK JT_TCLK 16 TRACEPKT[7] ETM_TPKT07 17 TMS JT_TMS 18 TRACEPKT[6] ETM_TPKT06 19 TDI JT_TDI 20 TRACEPKT[5] ETM_TPKT05 21 nTRST JT_TRSTn 22 TRACEPKT[4] ETM_TPKT04 23 TRACEPKT[15] ETM_TPKT15 24 TRACEPKT[3] ETM_TPKT03 25 TRACEPKT[14] ETM_TPKT14 26 TRACEPKT[2] ETM_TPKT02 27 TRACEPKT[13] ETM_TPKT13 28 TRACEPKT[1] ETM_TPKT01 29 TRACEPKT[12] ETM_TPKT12 30 TRACEPKT[0] ETM_TPKT00 31 TRACEPKT[11] ETM_TPKT11 32 TRACESYNC ETM_TSYNC 33 TRACEPKT[10] ETM_TPKT10 34 PIPESTAT[2] ETM_PSTAT2 35 TRACEPKT[9] ETM_TPKT09 36 PIPESTAT[1] ETM_PSTAT1 37 TRACEPKT[8] ETM_TPKT08 38 PIPESTAT[0] ETM_PSTAT0

Note: The AMP Mictor connector has four additional through-hole-pins in the center which have to be grounded for proper operation of the trace port! For the PCB layout it is recommended to have the lines for the ETM signals as short as possible (the signal delay should be < 100ps). The length of the lines should be equal to avoid different signal delays. To improve signal quality, matching resistors can be placed in the signal lines (located as close as pos-sible to the chip pins (<10mm)) to match the output impedance of the chip signal driver with the PCB trace impedance.

http://www.arm.com/



2.13 Vectored Interrupt Controller (ARM)

The Vectored Interrupt Controller (VIC) supports 32 interrupt sources, whereas 16 can be vectored. The interrupt priority and the type of interrupt, IRQ or Fast IRQ, are configurable. All Interrupts can be masked. Some of the Interrupts represent the result of a logical OR of several single interrupts of a function block. Hence the Interrupt service routine may have to check further registers to determine the actual source of an interrupt (e.g. resolving the GPIO interrupt to the GPIO input that caused it). The following table shows the different interrupt sources: Interrupt Source Standard Use Remark 0 VIC (Software Interrupt) ARM standard configuration 1 Timer / Counter 0 Real-time operating system timer Timer / counter from ARM_TIMER module 2 Timer / Counter 1 Timer / counter from ARM_TIMER module 3 Timer / Counter 2 Timer / counter interrupt from GPIO module 4 System Time nanoseconds compare Configurable, e.g. ‘1-second-IRQ’ 5 System Time seconds compare Windows CE Configurable, e.g. ‘1-day-IRQ’ 6 GPIO7 External interrupt from GPIO7 7 Watchdog Watchdog or XPIC watchdog expired 8 UART0 general diagnostic port 9 UART1 10 n/a Reserved 11 USB USB Interface 12 SPI0, SPI1 Common Int. for SPI 0 and SPI 1 Interface 13 I2C I2C Interface 14 n/a Reserved 15 HOST Dual port memory 16 GPIO GPIO (6:0) / IO-Link (3:0) 17 XPEC Communication channel / XP_IRQ(11:0) 18 n/a Reserved 19 n/a Reserved 20 XPIC XPIC Debug Interrupt 21 SYNC Synchronization channel / XP_IRQ(15:12) 22 n/a Reserved 23 n/a Reserved 24 VIC (Software Interrupt ) Can be set from XPIC 25 PHY Internal Phy 26 sysstate / extmem_timeout License Check / Memory Controller 27 DMA Controller Common Interrupt for all DMA channels 28 n/a Reserved 29 MPWM Motion PWM unit 30 MENC Motion Encoder unit 31 ADC ADC0 / ADC1 VIC IRQ Table, netX10



The Vectored Interrupt Controller (VIC) provides a software interface to the interrupt system. In an ARM system, two levels of interrupts are available: • Fast Interrupt Request (FIQ) for fast, low latency interrupt handling • Interrupt Request (IRQ) for more general interrupts. Generally, only one single FIQ source is used at a time in a system, to provide a true low-latency inter-rupt. This has the following benefits: • The interrupt service routine can be executed directly without having to determine the source of the

interrupt. • Interrupt latency is reduced. The banked registers available for FIQ interrupts can be used more

efficiently, because a context save is not required. There are 32 interrupt lines. The VIC uses one bit position for each different interrupt source. The soft-ware can control each request line to generate software interrupts. There are 16 vectored interrupts. These interrupts can only generate an IRQ interrupt. The vectored and non-vectored IRQ interrupts provide an address for an Interrupt Service Routine (ISR). Reading from the vector interrupt address register, VICVectAddr, provides the address of the ISR, and updates the interrupt priority hardware that masks out the current and any lower priority interrupt requests. Writ-ing to the VICVectAddr register, indicates to the interrupt priority hardware that the current interrupt is serviced, allowing lower priority interrupts to become active. The FIQ interrupt has the highest priority, followed by interrupt vector 0 to interrupt vector 15. Non-vectored IRQ interrupts have the lowest priority. A programmed interrupt request allows to generate an interrupt under software control. This register is typically used to downgrade an FIQ interrupt to an IRQ interrupt. The block diagram on the following page shows an overview of the VIC. Note: The priority of the FIQ over IRQ is set by the ARM. The VIC can raise both an FIQ and an IRQ at the same time. The VIC is compatible to ARMPrimeCell VIC (PL190), hence appropriate documentation from ARM should also be consulted.



Block diagram of the Vectored Interrupt Controller

2.13.1 Interrupt generation

Interrupt request generation For generation of FIQStatus[31:0] and IRQStatus[31:0], the interrupt requests from the peripherals are received and combined with the software interrupt requests. Then any undesired interrupt requests are masked out and the results are either routed to FIQStatus[31:0] or IRQStatus[31:0] (see block diagram). Non-vectored FIQ interrupt (nVICFIQ) generation By combining FIQStatus[31:0] (see block diagram) the non-vectored FIQ (nVICFIQ) which is connected to the ARM CPU, is generated. Non-vectored IRQ interrupt generation By combining IRQStatus[31:0] (see block diagram) the non-vectored IRQ is generated. This signal is used as input of the Interrupt Priority Logic. Vectored interrupt generation There are 16 vectored interrupt blocks which generate 16 vectored interrupt signals (VectIRQ0-15). The vectored interrupt blocks receive the IRQStatus[31:0] (Interrupt Requests) and set the VectIRQx if the following conditions are met: • the selected interrupt is active • the selected interrupt is currently highest requesting interrupt • the selected interrupt is enabled in the vector control register (VICIntCntl[0-15]) Software interrupts The software can control the source interrupt lines to generate software interrupts. These interrupts are generated before interrupt masking, in the same way as external source interrupts. Software interrupts



are cleared by writing to the software interrupt clear register, VICSoftIntClear (see Software interrupt clear register, VICSoftIntClear). This is normally done at the end of the interrupt service routine.

2.13.2 Interrupt priority logic

The interrupt priority block prioritizes the following requests: • Non-vectored interrupt requests • vectored interrupt requests The highest-priority request generates an IRQ interrupt if the interrupt is not currently being serviced. The FIQ interrupt has the highest priority (outside the Interrupt priority logic), followed by interrupt vector 0 to interrupt vector 15. Non-vectored IRQ interrupts have the lowest priority.

2.13.3 Interrupt flow sequence

Vectored interrupt flow sequence: The following procedure shows the sequence for the vectored interrupt flow: • An interrupt occurs. • The ARM processor branches to either the IRQ or FIQ interrupt vector. • If the interrupt is an IRQ, read the VICVectAddr register and branch to the interrupt service routine.

This can be done using an LDR PC instruction. Reading the VICVectorAddr register updates the hardware priority register of the interrupt controller.

• Stack the workspace so that IRQ interrupts can be re-enabled. • Enable the IRQ interrupts so that a higher priority can be serviced. • Execute the Interrupt Service Routine (ISR). • Clear the requesting interrupt in the peripheral, or write to the VICSoftIntClear register if the request

was generated by a software interrupt. • Disable the interrupts and restore the workspace. • Write to the VICVectAddr register. This clears the respective interrupt in the internal interrupt priority

hardware. • Return from the interrupt. This re-enables the interrupts. Simple interrupt flow: The following procedure shows how you can use the interrupt controller without using vectored inter-rupts or the interrupt priority hardware. For example, you can use it for debugging. • An interrupt occurs. • Branch to IRQ or FIQ interrupt vector. • Branch to the interrupt handler. • Interrogate the VICIRQ Status register to determine which source generated the interrupt, and pri-

oritize the interrupts if there are multiple active interrupt sources. This takes a number of instructions to compute.

• Branch to the correct ISR. • Execute the ISR. • Clear the interrupt. If the request was generated by a software interrupt, the VICSoftIntClear register

must be written to. Check the VICIRQ Status register to ensure that no other interrupt is active. If there is an active request go to Step 4 (Interrogate …).

• Return from the interrupt. Note: If the simple flow is used, you must not read or write to the VICVectorAddr register.



2.14 Vectored Interrupt Controller (XPIC)

The netX10 is equipped with a second Vectored Interrupt Controller, assigned to the XPIC processor. Interrupt Source Standard Use Remark 0 XPIC VIC (Software Interrupt) 1 Timer / Counter 0 Timer / counter from MOTION_TIMER module 2 Timer / Counter 1 Timer / counter from MOTION_TIMER module 3 Timer / counter interrupt from GPIO module 4 Timer / Counter 2 Timer / counter from MOTION_TIMER module 5 System Time seconds compare Windows CE Configurable, e.g. ‘1-day-IRQ’ 6 GPIO7 External interrupt from GPIO7 7 Watchdog XPIC watchdog expired 8 UART0 general diagnostic port 9 UART1 10 n/a Reserved 11 USB USB Interface 12 SPI0, SPI1 Common Int. for SPI 0 and SPI 1 Interface 13 I2C I2C Interface 14 n/a Reserved 15 HOST Dual port memory 16 GPIO GPIO (6:0) / IO-Link (3:0) 17 XPEC Communication channel / XP_IRQ(11:0) 18 n/a Reserved 19 n/a Reserved 20 n/a Reserved 21 SYNC Synchronization channel / XP_IRQ(15:12) 22 n/a Reserved 23 n/a Reserved 24 XPIC VIC (Software Interrupt ) Can be set from ARM 25 PHY Internal Phy 26 sysstate / extmem_timeout License Check / Memory Controller 27 DMA Controller Common Interrupt for all DMA channels 28 n/a Reserved 29 MPWM Motion PWM unit 30 MENC Motion Encoder unit 31 ADC ADC0 / ADC1 XPIC VIC IRQ Table, netX10



2.15 DMA Controller



2.16 Multiplex Matrix

The well approved Multiplex Matrix feature, invented with the netX50, was also implemented in the netX10 to make a large number of peripheral interfaces accessible through a further reduced number of physical pins while providing high flexibility. The matrix connects to the “outside world” via a total of 24 MMIO pins (Mutliplex Matrix Input / Output). On the chip side, a total of 58 signals are connected to the matrix and can be routed to any of the MMIOs by setting the Configuration Registers of the MMIOs ac-cordingly. The following figure provides an overview of the Multiplex Matrix: Fig. 49 Multiplex Matrix

Each MMIO pin has a corresponding configuration register, that allows to map any of the 58 internal signals to this pin. Further, input and output signals can be inverted independently. This also allows to map an internal signal to more than one MMIO pin. If the internal signal is an output signal, then this signal is simply replicated on the mapped MMIO Outputs. If the internal signal is an input signal, then the level of this signal is the result of a logical OR of all MMIOs that are mapped to this signal. A complete list of all MMIO signals can be found in chapter 4.5 , Multiplex Matrix Signals. By default (after reset or power on), all MMIOs are configured for PIO input mode, which is a new fea-ture and allows to directly control (configured as output) or read (configures as input) the signal state of an MMIO signal through appropriate registers. As some interfaces have or may have certain timing requirements that can not be met by the Multiplex matrix, some of the MMIO pins are directly shared with those interfaces and allow a direct signal routing (like with the netX500). This applies to all signal of the PWM unit, the Ethernet PHYs when in Fiber optic mode and some XMAC signals (TX, ECLK and FBCLK).

netX10

Ethernet statusLEDs

Multiplexmatrix

XC channel

PHY status

8x GPIO

2x UART

SPI1

I2C

PositionEncoder

Misc

MMIO 0

MMIO 1

MMIO 2

MMIO 23

serial Flash

I2C

Postion Encoding

MMIOConfiguration

Module

24 MMIOs

58 in

tern

al c

onne

ctio

ns

4x IOLINK

SPI0/SQICSn2,3



2.17 IO-Link Interface



2.18 UART

The netX10 is equipped with two 16550-compatible UARTs providing 16 bytes transmit and receive FIFOs. They can be configured to support speeds up to 3.125 MBaud. The interface supports configura-tions of: • five, six, seven, or eight data-bit transfers • one or two stop bits • even, odd, or no parity • IrDA SIR encoding and decoding The request-to-send (RTS) and clear-to-send (CTS) modem control signals also are available with the interface for hardware flow control. Special features like stick parity and adjustable FIFO trigger level are implemented. UART0 is commonly used as diagnostic port, it is hence not recommended to use this port for other purposes, especially when using loadable firmware from Hilscher. Block diagram of the UART The ARM CPU reads and writes data and control/status information via the peripheral bus interface. The UART module can generate four individually-maskable interrupts which are combined to a single interrupt so that the output is asserted if any of the individual interrupts are asserted and unmasked. If a framing, parity or break error occurs during reception, the appropriate error bit is set, and is stored in the FIFO. If an overrun condition occurs, the overrun register bit is set immediately and FIFO data is prevented from being overwritten. Baud rate generator The baud rate generator contains free-running counters which generate the internal Baud16 or IrLP-Baud16 signal. Baud16 or IrLPBaud16 provide timing information for UART transmit and receive control. Baud16 is a stream of pulses with a width of 10 ns and a frequency of sixteen times the baud rate. Transmit FIFO The transmit FIFO is an 8-bit wide, 16-bit depth, first-in, first-out memory buffer. CPU data written across the bus interface is stored in the FIFO until read out by the transmit logic. The transmit FIFO can be disabled to act as a one-byte holding register.



Receive FIFO The receive FIFO is an 11-bit wide, 16-bit depth, first-in, first-out memory buffer. Received data, and corresponding error bits, are stored in the receive FIFO by the receive logic until read out by the CPU across the bus interface. The FIFO can be disabled to act as a one-byte holding register. Transmitter The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. Con-trol logic outputs the serial bit stream begins with a start bit, data bits, least significant bit (LSB) first, followed by parity bit, and then stop bits according to the programmed configuration in control registers. Receiver The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse has been detected. Parity, frame error checking and line break detection are also performed, and the data with associated parity, framing and break error bits is written to the receive FIFO. Interrupt logic Four individual maskable active HIGH interrupts are generated in the UART module and are combined to one interrupt output. This output is generated as an OR function of the individual interrupt requests. The single combined interrupt is used with the system interrupt controller that provides another level of masking on a per-peripheral basis. This allows use of modular device drivers which will always know where to find the interrupt source control register bits. IrDA SIR Endec The Transmitter and Receiver block contain an IrDA SIR protocol Endec. The SIR protocol Endec can be enabled for serial communication via signals nSIROUT and SIRIN to an infrared transducer instead of using the signals TXD and RXD. The SIR protocol Endec can both receive and transmit, but it is half-duplex only, so it cannot receive while transmitting, or vice versa. The SIR transmit encoder modulates the Non Return-to-Zero (NRZ) transmit bit stream. The IrDA SIR physical layer specifies use of a Return To Zero, Inverted (RZI) modulation scheme which represents logic 0 as an infrared light pulse. The modulated output pulse stream is transmitted to an external output driver and infrared Light Emitting Diode (LED). In normal mode the transmitted pulse width is specified as three times the period of the internal x16 clock (Baud16), that is, 3 / 16 of a bit period. Low-power mode of the transmit infrared pulse is set to 3 times the period of the internal generated IrLPBaud16 signal. The frequency of IrLPBaud16 signal is set by writing the appropriate divisor value to UARTILPR. The active low encoder output is normally LOW for the marking state (no light pulse). The encoder out-puts a high pulse to generate an infrared light pulse representing a logic 0 or spacing state. The SIR receive decoder demodulates the return-to-zero bit stream from the infrared detector and out-puts the received NRZ serial bit stream to the internal logic. The decoder input is normally HIGH (marking state) in the idle state (the transmit encoder output has the opposite polarity to the decoder input). A start bit is detected when the decoder input is LOW. Regardless of being in normal or low-power mode, a start bit is deemed valid if the decoder is still LOW, one period of IrLPBaud16 after the LOW was first detected.



UART communication Data received or transmitted is stored in two 16-byte FIFOs, the receive FIFO has an extra three bits per character for status information. For transmission, data is written into the transmit FIFO. This causes a data frame to start transmitting with the parameters indicated in UARTLCR. Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY signal goes HIGH as soon as data is written to the transmit FIFO (that is, the FIFO is non-empty) and remains asserted HIGH while data is being transmitted. BUSY is ne-gated only when the transmit FIFO is empty, and the last character has been transmitted from the shift register, including the stop bits. BUSY can be asserted HIGH even though the UART module may no longer be enabled. When the receiver is idle (RXD continuously 1, in the marking state) and a LOW is detected on the data input (a start bit has been received), the receive counter, with the clock enabled by Baud16, begins running and data is sampled on the eighth cycle of that counter (half way through a bit period). The start bit is valid if RXD is still LOW on the eighth cycle of Baud16, otherwise a false start bit is de-tected and it is ignored. If the start bit was valid, successive data bits are sampled on every 16th cycle of Baud16 (that is, one bit period later) according to the programmed length of the data characters. The parity bit is then checked if parity mode was enabled. Lastly, a valid stop bit is confirmed if RXD is HIGH, otherwise a framing error has occurred. When a full word has been received, the data is stored in the receive FIFO, with any error bits associated with that word. Error bits The three error bits are stored in bits 10:8 of the receive FIFO, and are associated to a particular char-acter. There is an additional error which indicates an overrun error but it is not associated with a particular character in the receive FIFO. The overrun error is set when the FIFO is full and the next character has been completely received in the shift register. The data in the shift register is overwritten but it is not written into the FIFO. FIFO bits 7:0 : received data FIFO bit 8 : framing error FIFO bit 9 : parity error FIFO bit 10 : break error Disabling the FIFOs Additionally, it is possible to disable the FIFOs. In this case, transmit and receive sides of the UART module have 1-byte holding registers (the bottom entry of the FIFOs). The overrun bit is set when a word has been received and the previous one was not yet read. Note: In order to use the UART signals, they must be routed to MMIOs by using the Multiplex Matrix (see chapter 2.16). For UART 0 a default routing exists, which must be used when the serial boot mode op-tion is implemented (see chapter 4.5 , Multiplex matrix signals).



2.19 USB

The integrated USB V 1.1 interface is fully compliant with the USB specification. It supports both full and low speed transfers and operates as USB device (upstream). The USB unit includes an integrated transceiver and provides eight pipes. Their direction, transfer type and FIFO size can be configured at run-time. The netX10 USB pads are equipped with internal, switchable pull-up resistors, hence external circuit is reduced to serial resistors and ESD protection. The switchable resistors further allow to con-nect and disconnect the netX USB device by software without physically disconnecting the USB cable. All low-level USB operations are realized in hardware. The software only has to manage the enumera-tion process and data transfer from and to the FIFOs. Fig. 50 USB Upstream Port / Device with Receptacle “B”

netX10

USB_DNEG

USB_DPOS 24

24

GND

USB_VSS

USB_VDDC

USB_VDDIO

1.5V

3.3V

D+3

D-2

VBUS1

GND4

Transient Suppressor



2.20 I2C Interface

2.20.1 Overview

The I2C interface is a simple 2-wire interface providing a clock and a data line. Transfers are serial, 8-bit oriented and bidirectional between master and slaves. Each device connected to the I2C interface is addressable by a unique address.

Module Features

The netX10 I2C unit has full master and slave functionality. It provides SCL clock rates from 50 kHz up to 3.4 MHz. For high efficient data exchange, the module includes a standard ARM DMA interface together with a 16-byte master data FIFO and a 16-byte slave data FIFO. It provides interrupts for the most important events like slave selection, FIFO requests and errors, I2C bus collision detection and end-of-transfer. To keep the main processor load low, there is a state machine implemented, which can run complex I2C sequences like acknowledge polling or long data transfers. I2C features like 7- and 10-bit slave addressing and multi master arbitration are supported by this module. An additional feature is the PIO mode, that allows to disconnect the I2C core and control the SCL and SDA signals directly through a corresponding register. This allows to access even I2C like components, that do not or not fully comply with the I2C specification. This mode must however be used carefully, since it also allows to actively drive the signals to high level, which may lead to short-circuit conditions. Note: This unit is not compatible with the netX100/netX500 I2C unit!

Typical Applications

There are many I2C devices on the market today. Typical are low bandwidth devices as: • EEPROMs • display controllers • card readers • various types of sensors • microcontrollers • various types of ICs with I2C configuration channel



2.20.2 Functional Description

For detailed I2C standard description, view Philips I2C-Bus specification (Version 2.1, 01.2001). The following section gives a brief overview. I2C devices are either master only, slave only or master-and-slave devices.The netX10 I2C unit is a master-and-slave device.

2.20.2.1 Block diagram

Fig. 51 I2C module block diagram_



2.20.2.2 I2C signals The I2C interface defines only two signals: • SCL: Serial Clock • SDA: Serial Data • To avoid signal driving conflicts, both signals are never actively driven to high level (high level is real-ized by (internal) pad pull-up resistors.

2.20.2.3 I2C Signal Conditions A transfer is initiated by a master with a start condition (START) or a repeated start condition (rSTART). The start condition is represented by a falling edge of SDA while SCL is high. At the end of a transfer, a stop condition (STOP) must be done by the master. The stop condition is represented by a rising edge of SDA while SCL is high. During data transfers, SDA is valid and must not change, while SCL is high.

Fig. 52 I2C signal condition states_

2.20.2.4 I2C Transfers An I2C transfer always transmits eight bits of data (MSB first) followed by an active low acknowledge bit generated by the receiving device. The first transferred byte after (r)START is always generated by a master. It contains a 7-bit slave ad-dress and an nWrite/Read bit, which indicates the transfer direction (0: write transfer master to slave, 1: read transfer master from slave). Every I2C slave device has its own slave ID. If any ID matches the address generated by the master during the first byte after (r)START, the appropriate slave acknowledges the first byte. For detailed I2C address range specification, see Philips I2C-Bus specification.

Fig. 53 I2C 1 Byte transfer_



2.20.2.5 I2C Acknowledge Handling The low active acknowledge bit is always generated by the receiving device (during write transfers by the slave, during read transfers by the master) after each transferred byte. If a slave did not acknowledge a byte, the master has to generate either (r)START or STOP.

Fig. 54 I2C write transfer_

After the last byte of a read transfer the master (as receiver) must not generate an acknowledge to sign the end of the transfer to the slave. Otherwise the slave will continue sending data and produce a bus error.

Fig. 55 I2C read transfer_

Note: After an acknowledged (r)START with set read bit, at least one byte must be transferred from slave to master. In case of transfer direction change an rSTART condition must be issued.

Fig. 56 I2C transfer with change of direction_



2.20.2.6 I2C 10-bit Addressing The Philips I2C specification describes an extended 10-bit addressing mode that is entered by a 2-byte start sequence. The first byte after (r)START contains a 7-bit address matching the reserved pattern “11110XX”, where “XX” are the both MSB bits of the requested 10-bit address. Note: For detailed I2C address ranges and pattern, view Philips I2C specification. If a 10-bit slave device is on the I2C-bus with appropriate MSB address bits, it will acknowledge the first byte. The master will then transfer the second start byte containing the lower eight address bits.

Fig. 57 I2C 10 Bit addressing_

As the second byte of a 10-bit start sequence is always transferred from master to slave, the read-bit in the first transferred byte must always be 0. A read transfer from a 10-bit addressed slave is initiated by a write start sequence followed by an rSTART and the first start byte containing the 10-bit address pattern, the slave address MSBs and the read-bit set to 1. The second start byte will not be transferred again.

Fig. 58 I2C initializing a read transfer from a 10-bit address slave_

Various types of transfers can be combined as described in Philips I2C specification. E.g. a write data may be inserted before restarting in Fig. 58

2.20.2.7 I2C General Call I2C general call functionality is provided by the reserved 7-bit address pattern “0000000” transferred after START initiating a write transfer (read-bit set to 0). Note: For detailed I2C address ranges and pattern, view Philips I2C specification.



2.21 SPI / SQI

2.21.1 Overview

Beside the I2C, the SPI is the most common serial interface for peripheries and memory components. SPI (Serial Peripheral Interface) is a full-duplex 4-wire interface defined by Motorola. Transfers are se-rial, typically 8-bit oriented and bidirectional between master and slaves. Slave devices are selected by a Chip Select signal. The netX10 provides one basic SPI unit and one SPI/SQI unit. The basic unit provides the following features:

• Full master and slave functionality.

• SPI_CLK clock rates up to:

o 50MHz in master mode

o 33 MHz in slave mode.

• All four Motorola SPI modes supported in master and slave mode:

o Clock polarity high or low

o Clock phase 0 or 1.

• Flexible data frame size from 4 to 16bit data words.

• 16-word deep FIFO for transmit data.

• 16-word deep FIFO for receive data.

• IRQ generation FIFO interaction.

• DMA interface for receive and transmit data to minimize system CPU load.

• Input signal oversampling and filtering for hazard suppression.

• Extended chip select controlling:

o Three individual external chip selects (may be demultiplexed externally to 8 signals)

o Static or dynamic chip select handling configurable.

• netX100 compatibility mode and register set.

Note: While the signals of SPI unit 0 are directly available on dedicated pins (except Chip Select 2), the sig-nals of SPI unit 1 and the CS2 of SPI unit 0 must be routed to MMIOs, using the Multiplex matrix (see chapter 2.16) if unit 1 or CS2 of unit 0 is to be used.



2.21.2 Functional description

2.21.2.1 Block diagram

Block diagram of SPI Unit

2.21.2.2 SPI signals The Motorola SPI interface defines four signals:

• Clock signal (SPI_CLK, SPI_SCK)

• Master transmit, slave receive data signal (SPI_MOSI)

• Master receive, slave transmit data signal (SPI_MISO)

• Low active chip select signal (SPI_FSS, SPI_CS_N)

Data transfers are full duplex bidirectional. Data is always serialized MSB first.



2.21.2.3 SPI Transfer Format SPI data transfer is activated by low active chip select signal. SPI signal generation and sampling states and timing can be selected by programmable SPO and SPH. Note: For more flexibility in master mode, chip select can be dynamically generated by the SPI module state machine or can be static, generated by spi_cr1 register bit fss_static.

SPI Clock Polarity (SPO)

SPI clock polarity is the idle state of SPI clock signal SPI_CLK when no data is transferred.

SPI Clock Phase (SPH)

SPI clock phase controls SPI data generation and sample timing. If SPH 0 is selected, data on SPI_MOSI and SPI_MISO is sampled on the first clock edge of SPI_CLK, if SPH 1 is selected sampling is done on the second edge. Data is generated on edge prior.

SPI Frame Format with SPO=0 and SPH=0

Clock idle state is low and data is sampled on the first (rising) edge of any SPI_CLK period. MSB data is generated when chip select is activated. Slave devices need chip select toggling at start of transfer to generate MSB data bit. SPI transfer, SPO=0 and SPH=0


Clock idle state is low and data is sampled on the second (falling) edge of any SPI_CLK period. MSB data is generated on the first (rising) SPI_CLK edge. Slave devices do not need chip select toggling at start of transfer to generate MSB data bit. SPI transfer, SPO=0 and SPH=1

SPI_CLK

SPI_CS_N

MSBSPI_MOSI

SPI_MISO LSB

LSB

MSB

MSB

LSB

LSB

MSB

4 to 16 bit 4 to 16 bit




Clock idle state is high and data is sampled on the first (falling) edge of any SPI_CLK period. MSB data is generated when chip select is activated. Slave devices need chip select toggling at start of transfer to generate MSB data bit. SPI transfer, SPO=1 and SPH=0


Clock idle state is high and data is sampled on the second (rising) edge of any SPI_CLK period. MSB data is generated on the first (falling) SPI_CLK edge. Slave devices do not need chip select toggling at start of transfer to generate MSB data bit. SPI transfer, SPO=1 and SPH=1

SPI_CLK

SPI_CS_N

MSBSPI_MOSI

SPI_MISO LSB

LSB

MSB

MSB

LSB

LSB

MSB


SPI_CLK

SPI_CS_N

MSBSPI_MOSI

SPI_MISO LSB

LSB

MSB

MSB

LSB

LSB

MSB




2.22 GPIO

The netX10 provides a total of 8 general purpose IOs, which are also used as input or output signal along with the internal timers. The GPIOs are not connected to signal pins directly but are attached to the Multiplex Matrix and can be mapped to any of the MMIO signals as required. The GPIOs provide the following features: • Can be programmed individually as input or output, inverted or non inverted • Outputs can be set by individual registers as well as by a common register • Each GPIO can be assigned to a System Timer, to be used as capture input or PWM output • Each GPIO can generate an interrupt Each GPIO has its own configuration register GPIO_CFGi to configure these functions and to read and write the IO individually. All inputs can be read together in the GPIO_IN register, respectively can be written through the GPIO_OUT register.

Fig. 59 GPIO block diagram



2.23 PIO

Unlike its predecessors, the netX10 does no longer provide dedicated PIO signals, however depending on the application, PIO ressources are available through the PIO mode that can be set separately for each unused DPM / memory interface pin. Further, each MMIO does now also provide a PIO functional-ity that allows to control each MMIO directly if no internal interface signal is mapped to it. For further information please check the corresponding chapters (DPM interface, Multiplex Matrix) of this document.



2.24 Ethernet Interface

The netX10 contains one Ethernet MAC (XMAC/XPEC unit) with integrated PHY, supporting: • 10Base-T / 100Base-TX • 100Base-FX with external drivers • Auto-Negotiation • Auto-Crossover • Auto-Polarity Fig. 60 Basic circuit for netX Ethernet interface (100Base-TX)

netX10

PHY_TXP

PHY_TXN

PHY_RXP

50 50

TXP1

TXN2

RXP3

RXN6

10

10n

50 50 10

10n

GND

1.5V

HX 1888H1102

10n/2kV

PE

12.4k

PHY_RXN

PHY_EXTRES

RJ45

75

75

PHY_ATP

10µ 100n

10µ 100n

1000 Ohm @ 100 MHz, 200 mA

1000 Ohm @ 100 MHz, 200 mAPHY_VDDIOATPHY_VDDIOAC

PHY_VDDCAPPHY_VDDCART

3.3V

PHY_VSS

4

5

7

2

75

75

( All resistors with tolerance of +/- 1 % )



With applications that do not make use of the Ethernet interface, the PHY signals must be con-

nected according to the following schematic (power must be supplied and reference resistor must be connected):

Fig. 61 Circuit when Ethernet interface is not used.

netX10

PHY_TXP

PHY_TXN

PHY_RXP

1.5V

12.4k

PHY_RXN

PHY_EXTRES

PHY_ATP

C5

C7PHY_VDDIOATPHY_VDDIOAC

PHY_VDDCAPPHY_VDDCART

3.3V

PHY_VSSATPHY_VSSACP

PHY_VSSARPHY_VSSAT1PHY_VSSAT2

GND

GND



2.25 Fieldbus Interface

The XMAC/XPEC unit of the netX can operate as a fieldbus controller, for virtually any existing and future fieldbus system, like: • AS interface Master • CANopen Master and / or Slave • CC-Link Slave • DeviceNet Master and / or Slave • PROFIBUS-DP Master and / or Slave The following sub chapters show the typical external circuitry required for the implementation of a cer-tain fieldbus interface with the netX. These schematics are for demonstration only. For detailed hardware design information, please consult the latest revisions of the reference schematics, available through the netX Download section at www.hilscher.com as well as the latest revisions of the appropri-ate fieldbus interface specifications.

http://www.hilscher.com/



2.25.1 AS interface Master

Fig. 62 Basic circuit for netX AS interface Master.

Please note, that the A2SI chip is about to be discontinued! This section will be updated as soon as a substitute has been selected and evaluated!

VDD

GND

ADuM1301

netX

XMi_RX

XMi_TX

XMi_IO0

VDD

GND

Asi+1

Asi-2

-+ Umin

Powerfail

RXD

TXD

USR

+ASi

-ASi

0V

+5VA2SI (Master Mode)

+3.3V

GND

For details, consultA2SI data sheet

UINUOUT

ASI_RX

ASI_TX

ASI_PF



2.25.2 CANopen Interface

Fig. 63 Basic circuit for netX CANopen interface.



2.25.3 CC-Link Interface

Fig. 64 Basic circuit for netX CC-Link interface.



2.25.4 DeviceNet Interface

Fig. 65 Basic circuit for netX DeviceNet interface.



2.25.5 PROFIBUS Interface

Fig. 66 Basic circuit for netX PROFIBUS interface.

netX10 Technical Data Reference Guide - Preliminary Electrical Specifications • 86


3 Electrical Specifications

3.1 Absolute Maximum Ratings

Stresses beyond the following ratings may cause permanent damage to the device. Please note, that these stress ratings do not imply functional operation of the device and that exposure to these ratings for extended periods of time may affect device reliability.

Symbol Parameter Conditions Ratings Unit VDDC Power supply, core voltage -0.5 to 2.0 V VDDIO Power supply, IO voltage -0.5 to 4.6 V USB_VDDC USB power supply, core voltage -0.5 to 2.0 V USB_VDDIO USB power supply, IO voltage -0.5 to 4.6 V OSC_VDDC Oscillator power supply, core voltage -0.5 to 2.0 V PHY_VDDCART PHY power supply -0.5 to 2.0 V PHY_VSSACP PHY power supply -0.5 to 2.0 V PHY_VDDIOAC PHY power supply -0.5 to 4.6 V PHY_VDDIOAT PHY power supply -0.5 to 4.6 V PHY_VDDD PHY digital power supply -0.5 to 2.0 V VI Input voltage VI < VDDIO + 0.5

V -0.5 to 4.6 V

VO Output voltage VO< VDDIO + 0.5 V

-0.5 to 4.6 V

6 mA type ±21 mA 9 mA type ±29 mA

IO Output current

TA Operating ambient temperature Note 1) -40 to +85 °C Tj Junction temperature Note 1) -40 to +125 °C Tstg Storage temperature Note 2) -65 to +150 °C

Notes:

1) See also chapter 4.1.

2) This temperature range has no relation to soldering conditions or solderability of the compo-nents. Please check chapter 4.3 for storage conditions that assure solderability.



3.2 Power Up Sequencing

All power supplies of the netX chip must ramp up or down within 100 ms time. There is no prescribed order in which the supplies must be applied, however all voltages should have reached the 0.9 * VDD condition not later than 100ms after the first supply started to ramp up (time measured from 0.1 * VDD condition). The following figure shows details of powering up and down. Notes:

1) Absolutely all power supply voltage pins have to be connected to the power supplies, even when certain peripheral parts of the netX chip are not used!

2) The above information concerning the arbitrary order of ramping up the supply voltages does

only refer to the fact that there is no required sequence to avoid damage of the chip. However, when ramping up VDDio before VDDc, I/O signals (even those that come up in High-Z state af-ter Reset) may show unpredictable (and undesired) behaviour like actively driving low or high for a short period until the core has initialized completely. To safely avoid these effects, VDDio should ramp up after VDDc supply has reached its minimum level.



3.3 Power Consumption / Power Dissipation

The typical power consumption of the netX10 is approximately 0.7 Watts (integrated PHY in use, only internal RAM used) or 0.5 Watts (PHY turned off).The following tables provide an overview of power consumption of single modules of the chip and some standard applications. Power consumption of netX10 chip:

Symbol Unit Min. Typ. Max. Unit PBASE Ground consumption, chip in idle state 0.2 W PARM ARM CPU 0.01 0.08 0.1 W PSDRAM SDRAM Note 1) 0.02 0.1 0.2 W PHIF DPM interface, 16 Bit Note 2) 3) 0 0.03 0.08 W PXC Communication channel (XMAC and XPEC) Note 2) 0 0.12 0.14 W PPHY Ethernet PHY’s (100Base-TX) Note 4) 0 0.25 W PMAX Max. chip power consumption Note 5) 1 W

All values above assume nominal supply voltages ( VDDC = 1.5V , VDDIO = 3.3V). Increasing the supply voltages to their maximum (1.65V and 3.6V) will increase power consumption by appr. 25% Notes:

1) SDRAM IO power consumption strongly depends on capacitive load, access rate and type of access (write consumes significantly more power than read). Max. value is valid for a single SDRAM component, located close to the (trace length <= 2cm) at stress test condition (maxi-mum possible (write) access rate, which can not be reached in a useful application).

2) Min. values apply when modules are idle (not used). 3) Max. value is at maximum possible access rate (reading) and maximum allowed load capacity

of 50pF on all host interface data signals. 4) Min. value applies when PHY is disabled. 5) At preceding conditions.

netX power consumption at typical setups:

Symbol Parameter Typ. Unit PBOOT Serial boot mode, no external communication 0.2 W PETH-SD Full Duplex Ethernet, SDRAM 0.9 W PETH-INT Full Duplex Ethernet, only internal RAM 0.7 W



3.4 AC / DC Specifications

3.4.1 DC Parameters

The following table describes the standard pad cells of the netX10. The special pad cells for crystal, USB and PHYs are described in the following chapters.

Symbol Parameter Conditions Min. Typ. Max. Unit VDDC Power supply voltage, core 1.425 1.5 1.65 V VDDIO Power supply voltage, IO 3.0 3.3 3.6 V VN Negative trigger voltage 0.6 1.8 V VP Positive trigger voltage 1.2 2.4 V VH Hysteresis voltage 0.3 1.5 V VIL Input voltage, low 0 0.8 V VIH Input voltage, high 3.3 V 2.0 VDDIO V slewri Input rise (normal input) 0.015 V/ns slewfa Input fall time (normal

input) 0.015 V/ns

slewri Input rise (Schmitt input) 0.27 V/ms slewfa Input fall time (Schmitt

input) 0.27 V/ms

IOZ Off-state current VO = VDDIO or GND ±10 µA IOS Output short circuit current -250

Note 1) mA

VI = VDDIO or GND

Normal input

±0.1 ±10 Note 2)

µA

VI = GND pull-up 50 kΩ

-37 -103 -253 µA

ILI Input leakage current

VI = VDDIO pull-down 50 kΩ

26 73 175 µA

VOL = 0.4V 6 mA type 6.0 mA IOL Output current, low 9 mA type 9.0 mA VOH =2.4V 6 mA type -6.0 mA IOH Output current, high 9 mA type -9.0 mA IOL = 0 mA 0.1 V IOL = 6 mA (6 mA type) 0.4 V

VOL Output voltage, low

IOL = 9 mA (9 mA type) 0.4 V IOH = 0 mA VDDIO-

0.1 V VOH Output voltage, high

IOH = 6 mA (6 mA type) 2.4 V CIN Pin capacitance Input buffer 2 4 6 pF CIO Pin capacitance Output and bidirectional

buffer 2 4 6 pF

RPU Resistance of internal 50k pull-up resistor

VDDIO = 3.3 ± 0.3V TA = -40 to +85°C

14.2 31.9 80.7 kΩ

RPD Resistance of internal 50k pull-down resistor

VDDIO = 3.3 ± 0.3V TA = -40 to +85°C

20.6 44.9 116.4 kΩ

Notes: 1) Output short circuit time no longer than one second and only one pin of the chip! 2) This value only applies to (also internally) unconnected standard pad cells. As most netX pins are equipped with internal pull-up or pull-down resistors, please also consider chapter 2.3 (Signal Definitions) to determine actual leakage current of a specific pin!



Symbol definition: VDDC , VDDIO: Indicates the voltage range for normal logic operations that occur when VSS = 0 V. VN : Indicates the input level at which the output level is inverted when the input is changed from the high-level side to the low-level side. VP : Indicates the input level at which the output level is inverted when the input is changed from the low-level side to the high-level side. VH : Indicates the differential between the positive trigger voltage and the negative trigger voltage. VIL : Indicates the voltage which must be applied to the input pins to guarantee a logical low input level. VIH : Indicates the voltage which must be applied to the input pins to guarantee a logical high input level. slewri : slew rate rise time slewfa : slew rate fall time IOZ : Indicates the current that flows from the power supply pins when the rated power supply voltage is applied when a 3-state output has high impedance. IOS : Indicates the current that flows when the output pins are shorted (to GND pins) when output is at high level. The output short circuit must not exceed more than one second and is only for one pin. ILI : Indicates the current that flows via an input pin when a voltage is applied to that pin. IOL : Indicates the current that flows to the output pins when the rated low-level output voltage is being applied. IOH : Indicates the current that flows from the output pins when the rated high-level output voltage is being applied. VOL : Indicates the output voltage at low level and when the output pin is open. VOH : Indicates the output voltage at high level and when the output pin is open.

http://dict.leo.org/se?lp=ende&p=/Mn4k.&search=slew

http://dict.leo.org/se?lp=ende&p=/Mn4k.&search=rate

http://dict.leo.org/se?lp=ende&p=/Mn4k.&search=slew

http://dict.leo.org/se?lp=ende&p=/Mn4k.&search=rate



3.4.2 System Oscillator / PLL

The system oscillator circuit along with the internal PLL, generates all internal clocks of the netX10 chip. For clock generation, either a quartz crystal (oscillation mode: fundamental) with the internal oscillator circuit or a quartz oscillator connected to the clock input pin may be used.

Symbol Parameter Conditions Min. Typ. Max. Unit OSC_VDDC Oscillator power supply core 1.425 1.5 1.65 V VIL Input voltage, low Note 1) 0 0.8 V VIH Input voltage, high Note 1) 2.0 VDDIO + 0.5 V VOL Output voltage, low Note 1) 0.4 V VOH Output voltage, high Note 1) 2.0 3.0 VDDIO V fCLK System clock frequency 25 MHz System clock tolerance -100 +100 ppm System clock duty cycle 40 50 60 % System jitter tolerance 20 ps [RMS] TCYC System clock cycle time 40 ns Thigh System clock high time 14 20 ns Tlow System clock low time 14 20 ns System clock slew rate 0.5 V/ns CIN Pin capacitance input buffer 2.5 3.5 4.5 pF COUT Pin capacitance output buffer 2.7 3.7 4.7 pF OSC_IVDDC Oscillator current 1.5 V 6 mA

Notes:

1) These values are DC parameters, that do not apply to the dynamical system of a crystal circuit. When using crystals, the circuit should be designed in a way that keeps the levels within the absolute maximum ratings (-0,5V to Vddio + 0,5V).



3.4.3 Power On Reset / Reset Input

The netX10 provides one asynchronous reset input with a Schmitt-trigger input cell that is to be used for the mandatory Power On Reset of the chip. The picture and table below show the behavior of the reset system and the timing requirements for the reset input signals.

Parameter Description Value Dimension tOSC Startup time for the internal oscillator system (25 MHz) < 10 ms tPOR Minimum duration of external Power On Reset signal > tosc tPLL Time between deassertion of PORn and start of internal PLL 10,5 ms tIRR Time between deassertion of PORn and release of internal Reset 11,5 ms

Note:

The Oscillator startup time depends on environment temperature and crystal type. The given values are typical values that have been evaluated with a certain crystal and may differ from the values experienced with the user’s application. The external reset signal source (reset genera-tor) may release the PORn signal before the System oscillator has settled completely, however the values for tPLL and tIRR may diverge from the values above in that case, since they derive from counter values and the counters are clocked by the system oscillator.

CLK25

PORn

InternalReset tIRR

CLK100_INT

Vcc

0 V

1.5V / 3.3 V

tPLL

tPOR

tOSC



3.4.4 MMIOs



3.4.5 USB



3.4.6 PHY

The power supplies of the PHY must always be connected, even when it is not used.

Symbol Parameter Conditions Min. Typ. Max. Unit PHY_VDDCART PHY power supply 1.425 1.5 1.65 V PHY_VDDCAP PHY central analog power supply 1.425 1.5 1.65 V PHY_VDDIOAC PHY central analog power supply 3.0 3.3 3.6 V PHY_VDDIOAT PHY analog test power supply 3.0 3.3 3.6 V

1.5 V 60 70 mW P10BT 3.3 V 210 250 mW 1.5 V 115 135 mW P100BT 3.3 V 130 150 mW 1.5 V 50 60 mW P100FX 3.3 V 2.5 3 mW

PHY_REXTRES Reference resistor Must always be connected, 12.4 kΩ / 1% PHY_IVDDC PHY core current,

includes IVDDCART and IVDDCAP 1.5 V 1 75 90 mA

PHY_IVDDIO PHY IO current, includes IVDDIOAC and IVDDIOAT

3.3 V 1 65 75 mA

Max. power and current values apply at max. voltage conditions

100BASE-TX:

Symbol Parameter Conditions Min. Typ. Max. Unit V100OUTH TX Output, High Level

Differential Signal, TXP/TXN 0.95 1.05 V

V100OUTL TX Output, Low Level Differential Signal, TXP/TXN

-0.95 -1.05 V

V100OUTM TX Output, Mid. Level Differential Signal, TXP/TXN

-0.05 +0.05 V

VOVS TX Output, Overshoot Differential Signal, TXP/TXN

0 5 %

V100INTHON RX Input, Turn-on Threshold Level Differential Signal, RXP/RXN

1.0 V

V100INTHOFF RX Input Turn-off Threshold Level Differential Signal, RXP/RXN

0.20 V

tr Rise time, TXP/TXN 3 5 ns tf Fall time, TXP/TXN 3 5 ns Duty cycle distortion, TXP/TXN 0 0.5 ns(pp) Transmit Jitter, TXP/TXN 0 1.4 ns(pp)

These specs are compliant with ANSI/IEEE802.3 Std. 10BASE-T:

Symbol Parameter Conditions Min. Typ. Max. Unit V10OUT TX Output Amplitude

Differential Signal, TXP/TXN 2.2 2.8 V

V10INTH RX Input Threshold Level Differential Signal, RXP/RXN

0.30 0.585 V

These specs are compliant with ANSI/IEEE802.3 Std.



3.4.7 SDRAM

Initialization Auto refresh cycles



Self refresh mode, entry and exit



Write access SDRAM Write Timing, single bank write (MEM_SDCKE is always high and is hence not shown) Read access SDRAM Read Timing, single bank write (MEM_SDCKE is always high and is hence not shown)



All Timings are related to the following SDRAM clock phase settings ( sdram_timing_ctrl register): mem_sdclk_phase: 2 data_sample_phase: 1 Electrical Characteristics of netX50 SDRAM Memory Interface Part (CL MEM_D0..31: 15pF, all other signals 10pF):

Symbol Parameter Min Typ Max Unit

tCP SDRAM Clock (MEM_SDCLK) cycle time 10.0(1) 10.0(1) (1) ns

tCH SDRAM Clock (MEM_SDCLK) high level width 3.5 4.7 ns

tCL SDRAM Clock (MEM_SDCLK) low level width 3.8 4.8 ns

tCKS Clock Enable (MEM_SDCKE) setup time 4.6(2) ns

tCKH Clock Enable (MEM_SDCKE) hold time 1.8(2) ns

tCMS Command setup time MEMDR_CSn MEMDR_WEn MEMDR_RASn MEMDR_CASn

4.5 4.6 4.2 4.4

ns

tCMH Command hold time MEMDR_CSn MEMDR_WEn MEMDR_RASn MEMDR_CASn

1.8 1.8 2.2 2.3

ns

tAS Address (without MEM_A10) setup time 3.7 ns

tAH Address (without MEM_A10) hold time 1.8 ns

tA10S MEM_A10 setup time 4.3 ns

tA10H MEM_A10 hold time 2.1 ns

tDQMS Data Qualifier Mask (MEM_DQM*) setup time 4.0 ns

tDQMH Data Qualifier Mask (MEM_DQM*) hold time 2.0 ns

tDS netX Data-out setup time 3.4 ns

tDH netX Data-out hold time 2.0 ns

tDE netX Data-out enable (Low Z) time 5.6 ns

tDD netX Data-out disable (High Z) time 4.0 ns

tAC SDRAM Access time 6.0 ns

tOH SDRAM Data-out hold time 1.0 ns

tLZ SDRAM Data-out enable (Low Z) time 0.0 ns

tHZ SDRAM Data-out disable (High Z) time 14.4 ns Notes:

1. MEM_SDCLK is always running at the same frequency as netX internal system clock.

2. MEM_SDCKE is only used for SDRAM power down (Self Refresh mode or SDRAM disabled).



Timing Characteristics configurable by sdram_timing_ctrl configuration register.


tRAS ACTIVE to PRECHARGE time 3..10 tCP

tRC ACTIVE to ACTIVE (same bank) time 4..13(1) tCP

tRCDR ACTIVE to READ (same bank) time 1..3(2) tCP

tRCDW ACTIVE to WRITE (same bank) time 2..4(2) tCP

tREFI Average periodic REFRESH interval (Refresh period di-vided by rows to refresh within refresh period)

3.9(3) 7.8(3) 15.6(3)

31.2(3) us

tRFC AUTO REFRESH period 4..19 tCP

tRP PRECHARGE command period 1..3 tCP

tRRD ACTIVE to ACTIVE different bank time 1..3(4) tCP

tWR WRITE recovery time 1..3 tCP

tSR Self Refresh period 1 tCP

tXSRP Self Refresh Clock active to exit period exit 4 tCP

tXSR Self Refresh exit to command period 4..19(5) tCP

tCL CAS Latency 2 3 tCP Notes:

1. Minimum tRC is tRAS + tRP.

2. ACTIVE to WRITE (same bank) time is ACTIVE to READ (same bank) time plus 1 additional cycle form memory controller internal arbitration.

3. At 100MHz system clock.

4. SDRAM Controller uses a common parameter for tRP and tRRD.

5. SDRAM Controller uses a common parameter for tRFC and tXSR.

SDRAM Initialisation and Power Up Timing Characteristics.


tinit Whole SDRAM initialisation time till first ACTIVE 20317 20317 tCP

tinitP SDRAM Power Up time (NOP till first PRECHARGE) 20050 20050 tCP

tinitRP Initialisation PRECHARGE command period 16 16 tCP

tinitRFC Initialisation AUTO REFRESH period 23 32 tCP

tinitMRD Load MR to first command period 4(1) tCP Notes:

1. If longer tinitMRD time is required, software can wait until sdram_ready flag is set in sdram_general_ctrl register before running first SDRAM memory access.



3.4.8 SRAM / FLASH

Fig. 67 Read, pre and pos-pauses enabled for sequential reads (Write-enable always high).

Fig. 68 Read, pre and pos-pauses disabled for sequential reads (Write-enable always high).

Fig. 69 APM Read burst, pre and pos-pauses disabled between sequential reads.

Note: APM read burst access cycles can also be extended by Ready-signal. Timing relations are the same as shown in Fig. 68.



Fig. 70 Write (Read-enable always high).

Note: Byte-Enable signal have address character. They are covered address timing parameters.

Timings of netX 10 SRAM Interface is widely configurable by software. Detailed timings depend on fol-lowing programmable parameters that can be set for each chip-select area individually (exception: Ready Filter time) by software. Symbol Parameter Min Typ Max Unit

tSYS netX system clock cycle time 10.0(1) 10.0(1) ns

tpr programmable pre-pause wait phase (10ns steps) 0.0 n* tSYS 3*tSYS ns

tpo programmable post-pause wait phase (10ns steps) 0.0 n* tSYS 3*tSYS ns

tpw programmable wait-state phase (10ns steps) 0.0 n* tSYS 63*tSYS ns

tpaw(2) programmable APM wait-state phase (10ns steps) 0.0 n* tSYS 15*tSYS ns

trf programmable Ready Filter time 0.0 n* tSYS 3* tSYS ns Notes:

1. Default is 100MHz frequency as netX internal system clock but this could be decreased for power saving.

2. APM burst are only supported for chip-select 0.

All electrical characteristics of netX10 SRAM Memory Interface Part are related to CL: 15pF. For read accesses device access times must match following conditions:


tAC Data Access time tpw+tsys-5.0 ns

tAPM APM Data Access time tpaw+tsys-6.6 ns

Note: Access times can be extended by Ready signal usage.




tCSSr(1)

Chip-Select Setup time (read) tpr-1.3 ns

tCSHr(2) Chip-Select Hold time (read) tpo-1.2 ns

tCSSw Chip-Select Setup time (write) tpr+tpw+tSYS-0.8 ns

tCSHw Chip-Select Hold time (write) post-pause 0 post-pause > 0

tsys-1.2tpo-1.2

ns

tCSI Chip-Select Idle time tsys-1.7 ns

tASr(1) Address Setup time (read) tpr-2.7 ns

tAHr(2) Address Hold time (read) tpo-1.6 ns

tASw Address Setup time (write) tpr+tpw+tsys-1.2 ns

tAHw Address Hold time (write) post-pause 0 post-pause > 0

tsys-2.2tpo-2.2

ns

tAchg Address Change time (read burst) 2.6 ns

tDSr Data Setup time (read) 5.6 ns

tDHr(2) Data Hold time (read) -2.6 ns

tLZ Data Low-Z time (read) 0.0 ns

tHZ Data High-Z time (read) pre-pause 0 pre-pause > 0

tsys-2.6 tpr-2.6

ns

tDSw Data Setup time (write) tpr+tpw+tsys-1.3 ns

tDHw Data Hold time (write) post-pause 0 post-pause > 0

tsys-2.4tpo-2.4

ns

tDDw Data-Disable time (write) post-pause 0 post-pause > 0

tsys-3.4 tpo-3.4

ns

tRI Read-Enable Idle time tpr+tpo-1.7 ns

tWI Write-Enable Idle time post- and pre-pause 0 post- or pre-pause > 0

tsys-1.7tpr+tpo-1.7

ns

tWA Write-Enable Active time tpw+tsys-0.7 ns Notes:

1. For pre-pause setting 0 (tpr is 0) chip-select and address-setup time could become negative at read access start. That means they could change while read-enable has already become low in the first 2.7ns of an access. This can be avoided by setting pre-pause to 1 or more. However this will increase total access time by 10ns.

2. For post-pause setting 0 (tpo is 0) chip-select and address-hold time could become negative at read access end. That means they could already change while read-enable still is low in the last 1.6ns of an access. However, that will not cause read data problems as read data is already sampled at least 2.6ns (tDHr) before read access end. To guarantee stable chip-select and ad-dress signals at read access end post-pause can be set to 1 or more. However this will increase total access time by 10ns.



The following table provides timing parameters for optional Ready-signal. Wait-state-pause (tpw) must be set at least to 1 when ready is used.


tRSb Ready Setup Busy time tpw-0.5*tsys -4.6

tRAb Ready Active Busy time 1024 tsys(1) ns

tRSr Ready Setup Ready time trf+1.5*tsys -5.2

tRAr Ready Active Ready time trf+tsys +0.7

tRbsp Ready Busy Spike time post-pause 0 post-pause > 0

trf-0.6

Notes: 1. Ready timeout. Timeout can be disabled by software. However netX will be stalled when

Ready-signal is asserted permanently to busy state.



3.4.9 SPI

3.4.9.1 Master mode

SPI master signal timing (SPO=0 and SPH=0)




SPI master timing for worst case operating conditions: VDD: 3.0..3.6V, Tj: -40..+125°C, CL: 20pF. Values in brackets apply if input filtering is enabled.

Symbol Master Mode Parameter Min Typ Max Unit

tCP SPI_CLK period 20.0(1) 40960/N(1)

40960(1) ns

tCH SPI_CLK high phase 0.5*tCP-3.0 ns

tCL SPI_CLK low phase 0.5*tCP-3.0 ns

tR Signal rise time 0.4(2) 3.4(2) ns

tF Signal fall time 0.3(2) 2.0(2) ns

tCSS SPI_CS_N to first SPI_CLK edge setup time 0.5*tCP ns

tCSH last SPI_CLK edge to SPI_CS_N inactive time - SPH 0 Modes - SPH 1 Modes

10.0 0.5*tCP+10.0

11.5 0.5*tCP+11.5

ns

tCSW SPI_CS_N minimum high pulse width 0.5*tCP-3.0(3,4)

ns

tMOSIS SPI_MOSI to SPI_CLK setup time 0.5*tCP-3.4 ns

tMOSIH SPI_MOSI hold time 0.5*tCP ns

tMOSIHZ SPI_MOSI High-Z time 3.5 ns

tMISOS SPI_MISO to SPI_CLK setup time 2.5(12.5)(5) ns

tMISOH SPI_MISO hold time 6.5(16.5)(5) ns

tSPW Tolerated spike pulse width - with input filtering - without input filtering

9.0 0.0

ns

Notes:

3. N is programmed by spi_cr0 register sck_muladd bits. N = 1..2048

4. Signal rise and fall times differ greatly depending on external capacitive load. Approximation can be done by:

rise times: tr = 0.350 + 0.150 * CL [ns]; CL: external capacitive load fall times: tf = 0.237 + 0.087 * CL [ns]; CL: external capacitive load

5. If fss_static bit is set in spi_cr1 register, SPI_CS_N will not toggle between data words but half clock pause before next word MSB will be inserted anyway.

6. In SPH=1 modes SPI_CS_N does not become inactive during continuous transfers between LSB and next word MSB.

7. Input filtering can be enabled / disabled by filter_in bit in spi_cr0 register.



3.4.9.2 Slave Mode

SPI slave signal timing (SPO=0 and SPH=0)

SPI slave signal timing (SPO=0 and SPH=1)



SPI slave signal timing (SPO=1 and SPH=0) SPI slave signal timing (SPO=1 and SPH=1)



SPI slave timing for worst case operating conditions: VDD: 3.0..3.6V, Tj: -40..+125°C, CL: 20pF. Values in brackets apply if input filtering is enabled.

Symbol Slave Mode Parameter Min Typ Max Unit

tSCP SPI_CLK high phase ns

tSCH SPI_CLK high phase ns

tSCL SPI_CLK low phase ns

tR Signal rise time ns

tF Signal fall time ns

tSMOSIS SPI_MOSI to SPI_CLK setup time ns

tSMOSIH SPI_MOSI hold time ns

tSMISOS SPI_CLK to SPI_MISO setup time ns

tSMISOS1 SPI_CS_N to SPI_MISO MSB setup time ns

tSMISOH SPI_MISO hold time ns

tSMISOLZ SPI_CS_N to SPI_MISO MSB Low-Z time ns

tSMISOHZ SPI_CS_N to SPI_MISO LSB High-Z time ns

tSCSS SPI_CS_N to SPI_CLK setup time - SPH=0 modes - SPH=1 modes

ns

tSCSDH SPI_CS_N hold from deselected SPI_CLK edge time ns

tSCSH SPI_CS_N hold time ns

tSPW Tolerated spike pulse width - with input filtering - without input filtering

ns

Notes:

1. Minimum SPI_CLK period results from maximum MISO data setup time (tSMISOS) for valid read data.

2. Using SPH=0 modes SPI Chip Select falling edge is MSB data out trigger. Hence SPI Chip Se-lect must toggle between each transferred word. Using SPH=1 modes SPI Chip Select may remain active between transferred words.

3. For fast SPI clock rates early SPI_MISO signal generation can be enabled by slave_sig_early bit in spi_cr0 register. SPI_MISO will then be generated one SPI_CLK edge prior. For SPH=0 modes tSMISOS and tSMISOH will be related to SPI_CLK edges 1, 3, 5,... instead of 2, 4, 6,… (SPH=1 modes: SPI_CLK edges 2, 4, 6,... instead of 3, 5, 6,…).



3.4.10 I2C

The I2C Module IO timing depends on pad delays and internal module structure. All timings are related to an internal system clock running at 100MHz.


fSCL SCL clock frequency 50 (1) - 3333 (1) kHz

tSCL SCL clock period (1/ fSCL) 300 (1) - 20000 (1) ns

tfCL SCL fall time ns

trCL SCL rise time - (3) ns

tfDA SDA fall time ns

trDA SDA rise time - (3) ns

tLOW Low period of SCL clock tSCL/2 - tfCL - (1) ns

tHIGH High period of SCL clock tSCL/2 - trCL - tSCL/2 ns

tHD;DAT SDA hold time 0.0 - 0.0 ns

tSU;DAT SDA setup time tSCL/2 - trDA - - ns

tHD;STA SCL hold time after (repeated) START condition tSCL/2 - - ns

tSU;STA SCL setup time before repeated START condition tSCL/2 - trCL - - ns

tSU;STO SCL setup time before STOP condition tSCL/2 - trCL - - ns

tBUF I2C bus idle time between STOP and START tSCL/2 - trDA - - ns

tSP Pulse width of spikes suppressed by input filters - - tSCL/32 ns Notes:

1. SCL Clock frequency may decrease (period may increase) if SCL is held low by other devices. SCL frequency is set by mode-bits of i2c_mcr register.

2. Signal fall times are only typical. Approximation can be done by following formula:

fall times: tf = 0.197 + 0.058 * CL [ns]; CL: external capacitive load

3. Signal rise times depend on pullup resistor and capacitive bus load. Specified rise times are for 500 Ohms pull-up resistor and 400pF load. For I2C High-speed mode and high capacitive load external driver devices can be used to reach faster rise times.



3.4.11 UART

Symbol Description Condition Min Max Unit Bit Time 0 255 Bit Times t1 Programmable leading time

System Time 0 2.55 µs

Bit Time 0 255 Bit Times t2 Programmable trailing time

System Time 0 2.55 µs

t3 Setup Time before the end of stop bit 70 ns Note: This example uses the following settings: - 1 Start Bit - 1 Stop Bit - 8 Data Bits - Mode = '1'



3.4.12 Dual-port Memory Signal Timing

3.4.12.1 Parallel Modes DPM read accesses can be read or chip-select signal controlled. Additionally netX10 DPM supports read burst access handling without necessity of read or chip-select signal toggling between each ac-cess. On read accesses netX10 DPM will always insert wait cycles by asserting DPM_RDY signal.

Note: Data Qualifier signals (DPM_DQM) have address function. They are treated as address lines.

Fig. 71 Detailed timing DPM SRAM mode read access DPM_RDn controlled (DPM_WRn signal is

all time inactive high)



Fig. 72 Detailed timing DPM SRAM mode read access DPM_CSn controlled (DPM_WRn signal is


Fig. 73 Detailed timing DPM read burst access (DPM_A or DPM_DQM change without DPM_CSn

or DPM_RDn toggling. DPM_WRn signal is all time inactive high)

Note: Read burst support must be enabled by programming dpm_timing_cfg register.

Note: Undriven idle states of ready drive modes 2 and 3 are too slow for read bursts. Hence they are omitted in Fig. 73.

Time tACHGB is the maximum time of stable but invalid address occurring on address bus when burst addresses change.



DPM write cycles always end with positive edge of active low DPM write signal (DPM_WRn). No wait cycles will be inserted if netX internal part of DPM interface is idle.

Fig. 74 Detailed timing DPM SRAM mode write access when internal netX DPM side is idle (no

insertion of wait cycles, DPM_RDn signal is all time inactive high)

After end of an external write access (positive edge of DPM_WRn signal) internal access to netX ad-dress area will be started. If a new external DPM write access is initiated before prior write access finished internally, external wait cycles are inserted by asserting DPM_RDY signal.



Fig. 75 Detailed timing DPM SRAM mode write access when internal netX DPM side busy (inser-

tion of wait cycles, DPM_RDn signal is all time inactive high).



In multiplexed mode read bursts are not supported. Read-Enable signal must become inactive between subsequent accesses. Only data phase will be extended by asserting DPM_RDY to wait state. Address phase never will be extended. In multiplexed mode additional signal nADV (not Address/Data Valid) flags state of multiplexed ad-dress/data bus. Address part multiplexed on data lines must be valid around the positive edge of nADV signal.


Fig. 76 Detailed timing DPM SRAM mode read access DPM_RDn controlled (DPM_WRn signal is




DPM write cycles always end with positive edge of active low DPM write signal (DPM_WRn). No wait cycles will be inserted if netX internal part of DPM interface is idle.


Fig. 77 Detailed timing DPM multiplexed mode write access when internal netX DPM side is idle

(no insertion of wait cycles, DPM_RDn signal is all time inactive high)



After end of an external write access (positive edge of DPM_WRn signal) internal access to netX ad-dress area will be started. If a new external DPM write access is initiated before prior write access finished internally, external wait cycles are inserted by asserting DPM_RDY signal. DPM_RDY signal will only be asserted to wait state during data phase (nADV high). Address phase will never be extended.

Fig. 78 Detailed timing DPM multiplexed mode write access when internal netX DPM side busy

(insertion of wait cycles, DPM_RDn signal is all time inactive high).



Configurable Timing Parameters IO timings are derived from


tsys1) Main System Clock Period 10.0 ns

tOSA2)

Programmable DPM Address Setup Time Parameter

0.0 3tsys ns

tRDS2)

Programmable DPM Read Data Setup Time Parameter

0.0 7tsys ns

tf2) Delay time of programmable input

signal filter filtering disabled filtering enabled

0.0 tsys

0.0 tsys

ns

Notes: 1. tsys is netX internal system clock period (by default 10.0ns). System clock period affects

DPM IO timing as sample and output register stages run on this clock. System clock speed could be decreased (e.g. for power down) by configuration registers inside netX ASIC_CTRL address area

2. Configurable by dpm_timing_cfg register.

Standard Timing Parameters

Symbol Parameter Min Max Unit

tASr Address Setup Time (Read cycle)

0.9 0.9-tOSA

1) ns

tAHr Address Hold Time (Read cycle)

0.0 ns

tASw Address Setup Time (Write cycle)

10.8 tSYS+tf+0.8

ns

tAHw Address Hold Time (Write cycle)

0.9 ns

tDSw Data Setup Time (Write cycle) 10.8 tSYS+tf+0.8

ns

tDHr Data Hold Time (Read cycle) 2.1 ns

tDHw Data Hold Time (Write cycle) 0.8 ns

tDLZ Data enable Low Z time (Read cycle)

5.7 tSYS+tOSA+tf-4.3

2tSYS+tOSA-3.1

ns

tDHZ Data High Z Time (Read cycle) 4.9 ns

tAC Access Time (Read cycle) Read-data latched Read data not latched not shared shared

31.72)

2tSYS+tOSA+tf-11.72) 51.23)

(4+w)tSYS+tOSA+tf-11.24) (3+wm)tSYS+tOSA+tf-11.25)

2048tsys

6) 2048tsys

6)

ns

tRDI

tWRI Read inter access Idle Time Write inter access Idle Time

10.5 tsys+tf+0.57)

ns



tWC Write Cycle Time 10.5 tsys+tf+0.5

ns

tCSHw Chip-Select Hold Time (Write cycle)

0.0 ns

tWWP Write access Wait Phase 0.0 2048tsys 6) ns

tRWE Ready to Write Cycle End Time

0.0 ns

Notes: 1. Read Address Setup Time can be decreased by programmable timing parameter t_OSA

(0..3 system clock cycles, view Fehler! Verweisquelle konnte nicht gefunden wer-den.). Setup Time becomes negative e.g. t_OSA=1 leads to tAS=-9.1ns. That means stable address is required 9.1ns after chip-select and read-enable became active. That avoids problems caused by different signal runtimes if host devices activating read-enable, chip-select and address signals simultaneously.

2. This timing is valid when requested read data is already latched inside DPM module (Fehler! Verweisquelle konnte nicht gefunden werden.) or when read access targets read-ahead address area and read access matches read ahead address (Fehler! Ver-weisquelle konnte nicht gefunden werden.).

3. Standard read access to netX address area with 0 wait-states (e.g. INTRAM, Hand-shake-Cells). It has no effect whether a 0 wait state AHB slave is shared with other system masters or not. This timing is valid for first read after 4-byte-address-boundary changed or for read-ahead mismatch.

4. Standard read access to netX address area with w wait-states when netX AHB slave tar-get is not shared with another netX system master. If access targets netX address area with w wait-states, access time will be extended by 1 system clock for each wait state (netX wait state areas: Fehler! Verweisquelle konnte nicht gefunden werden., system memory INTRAM and Handshake-Cells run with 0 wait-states.)

5. Standard read access to netX address area with w wait-states when netX AHB slave tar-get is shared with another netX system master. Example: DPM access to INTLOGIC area (e.g. to xC Pointer FIFO) when netX ARM CPU also performs access to INTLOGIC area (e.g. SPI controller). Maximum wait-states is wm=wo+wDPM where wo are maximum internal wait-states of other master and wDPM are maximum internal wait-states of DPM access. (netX wait state areas: Fehler! Verweisquelle konnte nicht gefunden werden., system memory INTRAM and Handshake-Cells run with 0 wait-states.)

6. Ready-Timeout if access targets permanently busy netX address area.

7. If read burst support is not enabled.

Multiplexed Mode Timing Parameters:


tDVL nADV Low Time 10.7 tSYS+tf+0.7

ns

tDVS nADV Setup Time 0.0 ns

tDVH nADV Hold Time 0.0 ns

tDAS Data multiplexed Address Setup Time 10.6 tSYS+tf+0.6

ns

tDAH Data multiplexed Address Setup Time 1.0 ns



Ready Signal Timing Parameters


tDVR Data Valid to Ready Time (Read cycle) tRDS -2.21) ns

tRA Ready Active Time 5.7 ns

tRLZ Ready enable Low Z time 2.8 ns

tRHZ Ready High Z Time 2) 2)

tRH Ready Hold Time 2.6 ns

Notes: 1. Data Valid to Ready Time can be increased by programmable timing parameter t_RDS

(0..7 system clock cycles, view Fehler! Verweisquelle konnte nicht gefunden wer-den.). For t_RDS=0, DPM_RDY will be asserted 0.7ns before read data is valid. For correct t_RDS setting view host device requirements and datasheet.

2. Ready High Z times differ depending on programmed ready mode. Information is given in following tables.

Special Ready timing for Ready Signal Mode 0 and Drive Mode 2


tRPm02 Ready Pulse Width 8.0 tsys+tf-2.0

ns

tRHZm02 Ready High Z Time 10.4 tsys+tf+0.4

ns

Ready timing for Ready Signal Mode 0 and Drive Mode 3


tRHZm03 Ready High Z Time 1.3 ns



tRPm12 Ready Pulse Width 5.3 tsys+tf-4.7

ns

tRHZm12 Ready High Z Time 19.4 2tsys+tf-0.6

ns





tRHZm13 Ready High Z Time 3.8 ns

Special Read Burst Timing Parameters:


tACHGrb Address Change Time (Read burst) 8.6 tsys+tf-1.4

ns

tDHrb Data Hold Time (Read burst) 12.9 tsys+tf+2.9

ns

tRArb Ready Active Time (Read burst) 27.0 2tsys+tf+7.0

ns

Serial Mode IO Timing

Note: For serial DPM pinning view Fehler! Verweisquelle konnte nicht ge-funden werden..

Fig. 79 DPM SPI slave timing SPO=0 and SPH=0 transfer (data sampling on positive edge of se-

rial clock)

Fig. 80 DPM SPI slave timing SPO=0 and SPH=1 transfer (data sampling on negative edge of

serial clock)



Fig. 81 DPM SPI slave timing SPO=1 and SPH=0 transfer (data sampling on positive edge of se-

rial clock)

Fig. 82 DPM SPI slave timing SPO=1 and SPH=1 transfer (data sampling on negative edge of

serial clock)

Serial DPM Timing

Symbol Slave Mode Parameter Min Typ Max Unit

tSCP Serial Clock Period 8.01)2) ns

tSMOSIS MOSI to Serial Clock Setup Time 0.0 ns

tSMOSIH MOSI Hold Time 1.0 ns

tSMISOS Serial Clock to MISO Setup Time 1.83) tSCP-6.2

ns

tSMISOH MISO Hold Time 2.54) ns

tSMISOLZ Serial Chip Select to MISO MSB Low-Z time 2.9 ns

tSMISOHZ Serial Chip Select to MISO LSB High-Z time 2.0 ns

tSCSS Serial Chip Select to Serial Clock Setup Time 3.0 ns

tSCSDH Serial Chip Select from deselected Serial Clock edge Hold Time

3.0 ns

tSCSH Serial Chip Select Hold Time 3.0 ns

tSCSIW Serial Chip Select Idle Width 7.0 ns



Notes: 4. Serial Clock duty cycle is 30%.

5. Minimum Serial Clock Period is limited to 8ns (125MHz) even if Serial Clock to MISO Setup Time (tSMISOS) is shorter. This is caused by netX internal synchronization logic. If using serial clock rates above 66MHz take care for netX internal access times (e.g. non INTRAM access, view Fehler! Verweisquelle konnte nicht gefunden werden.).

6. For 125MHz serial clock.

7. Serial DPM Data Out (netX MISO) is always generated on sampling clock edge netX internally. This is done to achieve higher serial clock rates than generating MISO one edge later. Hold tim-ing is met due to netX internal serial clock latency.



3.4.13 JTAG

netX10 Technical Data Reference Guide - Preliminary • 128


3.5 Failure Rate (FIT)

Due to the comparatively low volume of netX controller production, Failure Rates for the complete chip are not available. However, as a guideline value, the known FIT values (as at August 2007) for the CB-12 process, the netX10, netX50, netX100 and netX500 are based on, can be used:

Failure Rate (FIT), Confidence Level = 60%

Junction Temperature Ea = 0.3eV Ea = 0.5eV (Typ.) Ea = 0.7eV

55 °C 26 5 1 70 °C 41 12 3 80 °C 55 19 7 90 °C 72 31 13 100 °C 94 48 24 125 °C 168 127 95

netX10 Technical Data Reference Guide - PreliminaryPackage and Signal Information • 129


4 Package and Signal Information

4.1 Thermal Package Specification

Absolute maximum junction temperature: Tj_max = 125 °C Absolute minimum junction temperature: Tj_min = -40 °C Thermal Characterization (based on JEDEC 2s2p test board (4 Layer)):

Air Flow [m/s] Symbol Parameter 0 0.2 1 2 Unit

θja Thermal resistance, junction-to-ambient 18.27 17.31 15.81 15.07 °C/W

ψjt Thermal parameter, junction to the top center of the package surface 0.11 0.17 0.29 0.36 °C/W

ψta Thermal parameter, the top center of the package surface to ambient 18.16 17.14 15.52 14.72 °C/W

θjc Thermal resistance, junction-to-case 6.69 °C/W



4.2 Soldering Conditions

The following soldering parameters are recommended for infrared reflow soldering. The netX package is suitable for a Pb-free soldering process.

4.2.1 Infrared Reflow Soldering Characterization

Symbol Parameter Value TPSTmax Maximum temperature, package´s surface temperature 260 °C t1 Preheating time at 160 to 180 °C 60 … 120 s t2 Maximum time of temperature higher than 220 °C ≤ 60 s t3 Maximum time at maximum temperature ≤ 10 s Maximum chlorine content of rosin flux 0.2 %



4.2.2 Vapour Phase Reflow Soldering (VPS) Characterization

Symbol Parameter Value TPSTmax Maximum temperature, package´s surface temperature 215 °C t1 Preheating time 30s - 60s t2 Time of temperature > 200°C 25s - 40 s Maximum chlorine content of rosin flux 0.2 %

4.3 General storage conditions

Parameter Conditions Min. Max. Unit Storage temperature Note 1) Sealed Drypack 5 30 °C Storage humidity Note 1) Sealed Drypack 20 70 %RH Storage time Note 2) Sealed Drypack 2 years

Storage temperature Note 3) Open Drypack < 25 °C Storage humidity Note 3) Open Drypack < 65 %RH Storage time after opening dry pack Note 3) Open Drypack 7 days

Baking time 125°C 20 72 hours Number of times of mounting 3 times

Notes:

1) Storing the sealed Drypacks at other conditions, may affect solderability of the components. 2) When storing sealed Drypacks for more than two years, it is recommended to check for oxida-

tion of the solder balls and perform tests to approve solderability prior to using the components for production. The two year period starts at the seal date, printed on the Drypack label.

3) Open Drypacks / unpacked components may be stored at these conditions for 7 days before

soldering. When exceeding one of the parameters temperature, humidity or time after opening a



sealed Drypack, components must be tempered according to parameter “Baking time” before soldering.



4.4 Signal Definitions

Signal PAD Type Description General PORn IUS Power on Reset RDY IOUS6 RDY-LED / Boot start option / secure eeprom SCL RUN IOUS6 RUN-LED / Boot start option / secure eeprom SDA XTAL OSC_XTI XTAL 25 MHz Crystal Input OSC_XTO XTAL 25 MHz Crystal Output OSC_VSS GND Oscillator Ground Supply OSC_VDDC PWR Oscillator Power Supply 1.5 V JTAG JT_TRSTn IDS JTAG Test Reset JT_TMS IUS JTAG Test Mode Select JT_TCLK IUS JTAG Test Clock JT_TDI IUS JTAG Test Data Input JT_TDO OZ6 JTAG Test Data Output SPI SPI0_CLK IOD6 SPI0 Clock SPI0_CS0n IOU6 SPI0 Chip Select 0 SPI0_MISO IOD6 SPI0 Master Input Slave Output Data / IO1 (Quad SPI mode) SPI0_MOSI IOD6 SPI0 Master Output Slave Input Data / IO0 (Quad SPI mode) SPI0_SIO2 IOD6 SPI0 IO2 (Quad SPI mode) SPI0_SIO3 IOD6 SPI0 IO3 (Quad SPI mode) USB USB_DNEG USB USB D- Line USB_DPOS USB USB D+ Line USB_VSS GND USB Ground Supply USB_VDDIO PWR USB Power Supply 3.3 V Test function TEST ID Activate Test Mode TMC1 ID Test Mode 1 TMC2 ID Test Mode 2 BIST_TRSTn IDS Reset Test Controller BSCAN_TRSTn IDS Boundary Scan Reset

Leave open for normal operating mode



Signal PAD Type Description MMIOs shared with PWM, Fiberoptic Interface and ‘direct’ XMAC signals MMIO0 IODS6 Multiplex Matrix IO 0 FO_RD

shared IODS6 (’IDS’) Fiberoptic Ethernet, Receive Data

MMIO1 IODS6 Multiplex Matrix IO 1 XM_TX IODS6 (’OD6’) XMAC Transmit Data XM_TX_ECLK IODS6 (’OD6’) XMAC Transmit Data, clocked with external clock FO_TD

shared

IODS6 (’OD6’) Fiberoptic Ethernet, Transmit Data MMIO2 IODS6 Multiplex Matrix IO 2 XM_ECLK IODS6 External Clock input for XM_TX / output from XMAC FB_CLK IODS6 (’OD6’) Clock output of fb_clk FO_EN

shared

IODS6 (’OD6’) Fiberoptic Ethernet, Enable MMIO3 IODS6 Multiplex Matrix IO 3 XM_TXOE IODS6 (’OD6’) XMAC TX Output Enable XM_TXOE_ECLK IODS6 (’OD6’) XMAC TX Output Enable, clocked with external clock FO_SD

shared

IODS6 (’IDS’) Fiberoptic Ethernet, SD MMIO4 IODS6 Multiplex Matrix IO 4 PWM0

shared IODS6 (’OD6’) PWM Signal 0

MMIO5 IODS6 Multiplex Matrix IO 5 PWM1










MMIO10 IOUS6 Multiplex Matrix IO 10 PWM6

shared IOUS6 (’OU6’) PWM Signal 6

MMIO11 IOUS6 Multiplex Matrix IO 11 PWM7

shared IOUS6 (’OU6’) PWM Signal 7

MMIO12 IOUS6 Multiplex Matrix IO 12 MMIO13 IOUS6 Multiplex Matrix IO 13 MMIO14 IOUS6 Multiplex Matrix IO 14 MMIO15 IOUS6 Multiplex Matrix IO 15 MMIO16 IOUS6 Multiplex Matrix IO 16 MMIO17 IOUS6 Multiplex Matrix IO 17 MMIO18 IOUS6 Multiplex Matrix IO 18 MMIO19 IOUS6 Multiplex Matrix IO 19 MMIO20 IOUS6 (5k pu) Multiplex Matrix IO 20 MMIO21 IOUS6 (5k pu) Multiplex Matrix IO 21 MMIO22 IOUS6 (5k pu) Multiplex Matrix IO 22 MMIO23 IOUS6 (5k pu) Multiplex Matrix IO 23



Signal PAD Type Description PIOs shared with Dual-Port Memory shared with Memory Interface. PIOs PIO00 - 15 IOD6 Programmable IOs 00 - 15 PIO32 - 55 IOD6 Programmable IOs 32 - 55 PIO57 - 63 IOU6 Programmable IOs 57 - 63 Dual-Port Memory DPM_D0 -15 IOD6 Dual port memory Data 0 -15 DPM_A0 -16 IOD6 (’ID’) Dual port memory Address 0 -16 DPM_CSn IOU6 (’IU’) Dual port memory Chip Select DPM_BHEn IOU6 (’IU’) Dual port memory Byte High Enable DPM_RDn IOU6 (’IU’) Dual port memory Read DPM_WRn IOU6 (’IU’) Dual port memory Write DPM_RDY IOU6 (’OZU6’) Dual port memory Ready DPM_DIRQ IOU6 (’OZU6’) Dual port memory Interrupt DPM_SIRQ IOU6 (’OZU6’) Dual port memory Interrupt Memory Interface MEMSR_CS0 - 1n IOU6 (’OU6’) SRAM Chip Select (MEMSR_CS1n shared with MEMDR_CSn) MEMSR_OEn IOU6 (’OU6’) SRAM Output Enable (shared with MEMDR_CKE) MEMSR_DQM0 IOD6 (’OD6’) SRAM Data Qualifier Mask D0-7 (shared with MEM_A0) MEMSR_A14 - 23 IOD6 (’OD6’) SRAM Address 14-23 MEM_D0 - 15 IOD6 SRAM / SDRAM Data 0-15 MEM_A0 - 13 IOD6 (’OD6’) SRAM / SDRAM Address 0-13 (MEM_A0 shared with MEMSR_DQM0) MEM_DQM1 IOU6 (’OU6’) SRAM / SDRAM Data Qualifier Mask D8-15 MEM_WEn IOU6 (’OU6’) SRAM / SDRAM Write Enable MEMDR_CSn IOU6 (’OU6’) SDRAM Chip Select (shared with MEMSR_CS1n) MEMDR_RASn IOD6 (’OD6’) SDRAM RAS (shared with MEMSR_A16) MEMDR_CASn IOD6 (’OD6’) SDRAM CAS (shared with MEMSR_A17) MEMDR_CKE IOU6 (’OU6’) SDRAM Clock Enable (shared with MEMSR_OEn) MEMDR_CLK IOU6 (’OZU6’) SDRAM Clock MEMDR_DQM0 IOD6 (’OD6’) SDRAM Data Qualifier Mask D0-7 (shared with MEMSR_A18) MEMDR_BA0 IOD6 (’OD6’) SDRAM Bank Select 0 (shared with MEMSR_A14) MEMDR_BA1 IOD6 (’OD6’) SDRAM Bank Select 1 (shared with MEMSR_A15)



Signal PAD Type Description

PHY PHY_RXN PHY PHY Receive Input negative PHY_RXP PHY PHY Receive Input positive PHY_TXN PHY PHY Transmit Output negative PHY_TXP PHY PHY Transmit Output positive PHY_VSSAT1 AGND PHY Analog Ground Supply PHY_VSSAT2 AGND PHY Analog Ground Supply PHY_VSSAR AGND PHY Analog Ground Supply PHY_VDDCART APWR PHY Analog TX/RX Power Supply 1.5 V PHY_EXTRES ANA Reference Resistor 12.4 k / 1% PHY_ATP ANA leave open! PHY_VSSACP AGND PHY Analog Central Ground Supply PHY_VDDCAP APWR PHY Analog Central Power Supply 1.5 V PHY_VDDIOAC APWR PHY Analog Central Power Supply 3.3 V PHY_VSSAT AGND PHY Analog Test Ground Supply PHY_VDDIOAT APWR PHY Analog Test Power Supply 3.3 V Power Supply VSS GND Ground Supply (except PHYs and OSC) VDDC PWR Power Supply, Core 1.5 V (except PHYs and OSC) VDDIO PWR Power Supply, IO Buffer 3.3 V (except PHYs and USB)

PAD Type Explanation: Symbol Description I Input O Output Z Output is tristateable or open drain S Input provides Schmitt trigger U Internal pull-up 50 k (MMIO20-23: pull-up 5k) D Internal pull-down 50 k 6 Output buffer can source / sink 6 mA 9 Output buffer can source / sink 9 mA XTAL Crystal input or output USB USB pad PHY PHY pad ANA Analog pin PWR 1.5 V (Core) or 3.3 V (I/O) GND Digital Ground (0 V) APWR Analog power (1.5V or 3.3V) AGND Analog ground (0 V) Notes:

1) PAD Types in brackets resemble the logical functionality of a buffer in a certain situation (when a pure input signal is assigned to an IO buffer, the buffer does of course not change in any way, however as its output driver is then automatically disabled, the buffer behaves like an input buffer)



IO9

OUT

OE

IN

I/O

50k

IOU6,IOU9

VDDIO

50k

IN

50k

VDDIO

IN

IU

OUT

OE

IN

I/O

IOD6,IOD9

IN

ID

50k

IN

OUT

OE

IN 5k /50k

IOUS6,IO(Z)US9

VDDIO

OUT

OE

IN

I/O

(TDBIAC33NN09) (TDBIAC33UN06,TDBIAC33UN09)

(TDBIAC33DN06,TDBIAC33DN09)

OUT OUT

O6,O9

OUT

OE

OUT

OZ6,OZ9(TDOPAC33NN06,TDOPAC33NN09)

(TDOTAC33NN06,TDOTAC33NN09)

(TDBIAC33WN09S)

(TDIPAC33U) (TDIPAC33D)

I/O

IN

IDS

50k

IN

(TDIPAC33DS)

OUT

OE

IN

IOC9

VDDH

(TDBIAPCUNLP36C)

(TDBIAC33WN06S)

IN

50k

VDDIO

IN

IUS(TDIPAC33US)

OUT

OE

IN

(TDBIAC33UN09S)

I/O

(TDBIAC33UN06S)

50k

IODS6(TDBIAC33DN06S)

4.4.1 Schematic View of netX Pad Types:

Notes:

1) The IO9, IOU9, IOD9, IOC9, O6, O9, OZ9, IU and IOZUS9 buffer types are not used in the netX10.



4.5 Multiplex Matrix Signals

Signal Direction Description Power On

MMIO Mapping Hilscher Default MMIO Mapping

Multiplex Matrix signals (MMIO) SPI SPI0_CS1n IO Chip Select 1 signal of SPI0 interface MMIO23 MMIO23 SPI0_CS2n IO Chip Select 2 signal of SPI0 interface SPI1_CLK IO Clock signal of SPI1 interface - - SPI1_CS0n IO Chip Select 0 signal of SPI1 interface - - SPI1_CS1n IO Chip Select 1 signal of SPI1 interface - - SPI1_CS2n IO Chip Select 2 signal of SPI1 interface - - SPI1_MISO IO Master In / Slave Out signal of SPI1 interface - - SPI1_MOSI IO Master Out / Slave In signal of SPI1 interface - - I2C I2C_SCL IO I2C Interface clock signal - - I2C_SDA IO I2C Interface data signal - - UARTs UART0_CTS I UART0 Clear To Send - MMIO12 UART0_RTS OZ UART0 Request To Send - MMIO13 UART0_RXD I UART0 Receive Data MMIO20 MMIO20 UART0_TXD OZ UART0 Transmit Data MMIO21 MMIO21 UART1_CTS I UART1 Clear To Send - MMIO18 UART1_RTS OZ UART1 Request To Send - MMIO19 UART1_RXD I UART1 Receive Data - MMIO16 UART1_TXD OZ UART1 Transmit Data - MMIO17 GPIO0 IO General Purpose IO - GPIO1 IO General Purpose IO - GPIO2 IO General Purpose IO - GPIO3 IO General Purpose IO - GPIO4 IO General Purpose IO - MMIO04 (IO-LINK) GPIO5 IO General Purpose IO - MMIO08 (IO-LINK) GPIO6 IO General Purpose IO - MMIO12 (IO-LINK) GPIO7 IO General Purpose IO - MMIO16 (IO-LINK) IO-LINK IOLINK0_IN I IO-LINK Channel 0 Input - MMIO05 IOLINK0_OUT O IO-LINK Channel 0 Output - MMIO06 IOLINK0_OE O IO-LINK Channel 0 Output Enable - MMIO07 IOLINK1_IN I IO-LINK Channel 1 Input - MMIO09 IOLINK1_OUT O IO-LINK Channel 1 Output - MMIO10 IOLINK1_OE O IO-LINK Channel 1 Output Enable - MMIO11 IOLINK2_IN I IO-LINK Channel 2 Input - MMIO13 IOLINK2_OUT O IO-LINK Channel 2 Output - MMIO14 IOLINK2_OE O IO-LINK Channel 2 Output Enable - MMIO15 IOLINK3_IN I IO-LINK Channel 3 Input - MMIO17 IOLINK3_OUT O IO-LINK Channel 3 Output - MMIO18 IOLINK3_OE O IO-LINK Channel 3 Output Enable - MMIO19



Signal Direction Description Power On

MMIO Mapping Hilscher Default MMIO Mapping

Encoder ENC0_A I Encoder 0 input A - MMIO12 ENC0_B I Encoder 0 input B - MMIO13 ENC0_N I Encoder 0 input index - MMIO14 ENC_MP0 I Encoder - MMIO15 ENC1_A I Encoder 1 input A - MMIO16 ENC1_B I Encoder 1 input B - MMIO17 ENC1_N I Encoder 1 input index - MMIO18 ENC_MP1 I Encoder - MMIO19 PWM PWM_FAILUREn I PWM Module Failure Input - - XMAC (Fieldbus ) XM_IO0 IO XMAC Programmable IO 0 - MMIO03 XM_IO1 IO XMAC Programmable IO 1 - MMIO02 XM_IO2 - 5 IO XMAC Programmable IO2 - 5 - - XM_RX I XMAC Receive Data - MMIO00



4.6 Pin Table Sorted By Pin Numbers Pin Signal Pin Signal Pin Signal Pin Signal A1 not populated DPM_WRn F1 OSC_XTI L11 VDDC

DPM_A16 MEMSR_WRn F2 JT_TDI L12 PHY_EXTRES MEMSR_A16 MEMDR_WEn F3 no connect L13 PHY_VSSAT2 MEMDR_RASn

B11

PIO59 F4 MMIO23 L14 PHY_TXP PIO00 DPM_CSn F5 no connect L15 PHY_TXN

A2

ETM_DACK MEMSR_CSn F6 no connect DPM_A14

B12 PIO60 F7 – F10 not populated M1 SPI0_SIO2

MEM_A14 DPM_BHEn F11 VDDC M2 SPI0_SIO3 MEMDR_BA0 MEM_DQM1 F12 MMIO12 M3 VSS PIO54

B13 PIO57 F13 VSS M4 VDDC

A3

ETM_TCLK DPM_D14 DPM_D10 M5 ADC1_IN1 DPM_A12 MEM_D14 MEM_D10 M6 ADC1_IN5 MEM_A12 PIO14 PIO10 M7 ADC1_VSS PIO52

B14

ETM_TPKT14

F14

SDPM_CSn M8 ADC0_IN1 A4

ETM_TPKT03 DPM_D06 DPM_D02 M9 ADC0_IN5 DPM_A10 MEM_D06 MEM_D02 M10 VDDC MEM_A10 PIO38 PIO34 M11 BSCAN_TRSTn PIO50

B15

ETM_TPKT06

F15

ETM_TPKT10 M12 PHY_VSSACP A5

ETM_TPKT01 M13 PHY_VDDIOAC DPM_A08 MEMSR_A18 G1 OSC_XTO M14 PHY_VDDCAP MEM_A08 MEMDR_DQM0 G2 JT_TDO M15 PHY_ATP PIO48

C1 PIO02 G3 BIST_TRSTn A6

ETM_PSTAT2 MEMSR_A19 G4 VSS N1 SPI0_MISO DPM_A06 C2 PIO03 G5 VDDC N2 SPI0_MOSI MEM_A06 C3 no connect G6 – G10 not populated N3 no connect PIO46 C4 VSS G11 no connect N4 ADC1_VDDIO A7

ETM_PSTAT0 C5 VDDIO DPM_DIRQ N5 VSS DPM_A04 C6 VSS MEMDR_CSn N6 VSS MEM_A04 C7 TEST

G12 PIO62 N7 VDDC A8

PIO44 C8 VSS G13 VDDIO N8 ADC0_VDDIO DPM_A02 C9 VDDIO DPM_D09 N9 no connect MEM_A02 C10 VSS MEM_D09 N10 VSS A9 PIO42 C11 TMC1 PIO09 N11 VSS DPM_A00 C12 VSS

G14

SDPM_MOSI N12 VDDIO MEM_A00 C13 VDDIO DPM_D01 N13 no connect MEMSR_DQM0 DPM_D13 MEM_D01 N14 VSS A10

PIO40 MEM_D13 PIO33 N15 VDDC DPM_RDY PIO13

G15

ETM_TPKT09 MEMSR_RDY

C14

ETM_TPKT13 P1 SPI0_CLK A11 PIO61 DPM_D05 H1 RDY MMIO11 DPM_SIRQ MEM_D05 H2 RUN

P2 PWM7

MEMDR_CLK PIO37 H3 OSC_VSS MMIO09 A12 PIO63

C15

ETM_TPKT05 H4 JT_TMS P3 PWM5 DPM_D15 H5 VSS P4 ADC1_VREFP MEM_D15 MEMSR_A20 H6 –H10 not populated P5 ADC1_IN2 PIO15 D1 PIO04 H11 no connect P6 ADC1_IN6 A13

ETM_TPKT15 MEMSR_A21 H12 VDDC P7 VDDIO DPM_D07 D2 PIO05 H13 VSS P8 ADC0_IN2 MEM_D07 D3 VSS DPM_D08 P9 ADC0_IN6 PIO39 D4 no connect MEM_D08 P10 ADC0_VSS A14

ETM_TPKT07 D5 MMIO21 PIO08 MMIO07 A15 not populated D6 MMIO20

H14

SDPM_MISO P11

PWM3 D7 MMIO19 DPM_D00 MMIO05

MEMSR_A17 D8 MMIO18 MEM_D00 P12

PWM1 MEMDR_CASn D9 MMIO17 PIO32 MMIO03 B1 PIO01 D10 MMIO16

H15

ETM_TPKT08 XM_TXOE DPM_A15 D11 MMIO15 XM_TXOE_ECLK MEMSR_A15 D12 MMIO14 J1 USB_DNEG

P13

FO_SD MEMDR_BA1 D13 VSS J2 VDDIO MMIO01 PIO55 DPM_D12 J3 OSC_VDDC XM_TX

B2

ETM_TSYNC MEM_D12 J4 USB_VSS XM_TX_ECLK DPM_A13 PIO12 J5 USB_VDDIO

P14

FO_TD MEM_A13

D14

ETM_TPKT12 J6 –J10 not populated P15 VSS PIO53 DPM_D04 J11 PHY_VSSAT B3

ETM_DREQ MEM_D04 J12 PHY_VDDIOAT R1 not populated DPM_A11 PIO36 J13 VDDC MMIO10 MEM_A11

D15

ETM_TPKT04 J14 VDDC R2

PWM6 PIO51 J15 VSS MMIO08 B4

ETM_TPKT02 MEMSR_A22 R3 PWM4 DPM_A09

E1 PIO06 K1 USB_DPOS R4 ADC1_IN0

MEM_A09 MEMSR_A23 K2 VSS R5 ADC1_IN4 PIO49 E2 PIO07 K3 no connect R6 ADC1_VREFM B5

ETM_TPKT00 E3 VDDIO K4 JT_TCLK R7 ADC0_VREFP DPM_A07 E4 MMIO22 K5 no connect R8 ADC0_IN0 MEM_A07 E5 VDDC K6 – K10 not populated R9 ADC0_IN4 PIO47 E6 no connect K11 PHY_VSSAT1 R10 ADC0_VREFM B6

ETM_PSTAT1 E7 no connect K12 PHY_VDDCART MMIO06 DPM_A05 E8 VDDC K13 PHY_VSSAR

R11 PWM2 MEM_A05 E9 no connect K14 PHY_RXP MMIO04 B7 PIO45 E10 VDDC K15 PHY_RXN

R12 PWM0

DPM_A03 E11 no connect MMIO02 MEM_A03 E12 MMIO13 L1 PORn XM_ECLK B8 PIO43 E13 TMC2 L2 SPI0_CS0n FB_CLK DPM_A01 DPM_D11 L3 VDDIO

R13

FO_FN_EN MEM_A01 MEM_D11 L4 JT_TRSTn MMIO00 B9 PIO41 PIO11 L5 VDDC

R14 FO_RD

DPM_RDn

E14

SDPM_CLK L6 ADC1_IN3 R15 not populated MEMSR_OEn DPM_D03 L7 ADC1_IN7 MEMDR_CKE MEM_D03 L8 ADC0_IN3

B10

PIO58 PIO35 L9 ADC0_IN7

E15

ETM_TPKT11 L10 no connect



4.7 Pin Table Sorted By Signals

Signal Shared with Pin Signal Shared with Pin System DPM_WRn MEMSR_WRn MEMDR_WEn PIO59 B11 DPM_RDY MEMSR_RDY PIO61 A11 RDY H1 DPM_SIRQ MEMDR_CLK PIO63 A12 RUN H2 DPM_DIRQ MEMDR_CSn PIO62 G12 SPI0_CLK P1 SDPM_CLK MEM_D11 PIO11 DPM_D11 E14 SPI0_CS0n L2 SDPM_CSn MEM_D10 PIO10 DPM_D10 F14 SPI0_MISO N1 SDPM_MISO MEM_D08 PIO08 DPM_D08 H14 SPI0_MOSI N2 SDPM_MOSI MEM_D09 PIO09 DPM_D09 G14 SPI0_SIO2 M1 SPI0_SIO3 M2 Memory USB_VDDIO J5 USB_VSS J4 MEM_A00 MEMSR_DQM0 PIO40 DPM_A00 A10 USB_DNEG J1 MEM_A01 PIO41 DPM_A01 B9 USB_DPOS K1 MEM_A02 PIO42 DPM_A02 A9 MEM_A03 PIO43 DPM_A03 B8 OSC_VDDC J3 MEM_A04 PIO44 DPM_A04 A8 OSC_VSS H3 MEM_A05 PIO45 DPM_A05 B7 OSC_XTI F1 MEM_A06 ETM_PSTAT0 PIO46 DPM_A06 A7 OSC_XTO G1 MEM_A07 ETM_PSTAT1 PIO47 DPM_A07 B6 MEM_A08 ETM_PSTAT2 PIO48 DPM_A08 A6 PORn L1 MEM_A09 ETM_TPKT00 PIO49 DPM_A09 B5 MEM_A10 ETM_TPKT01 PIO50 DPM_A10 A5 JT_TCLK K4 MEM_A11 ETM_TPKT02 PIO51 DPM_A11 B4 JT_TDI F2 MEM_A12 ETM_TPKT03 PIO52 DPM_A12 A4 JT_TDO G2 MEM_A13 ETM_DREQ PIO53 DPM_A13 B3 JT_TMS H4 MEMSR_A14 MEMDR_BA0 ETM_TCLK PIO54 DPM_A14 A3 JT_TRSTn L4 MEMSR_A15 MEMDR_BA1 ETM_TSYNC PIO55 DPM_A15 B2 MEMSR_A16 MEMDR_RASn ETM_DACK PIO00 DPM_A16 A2 BIST_TRSTn G3 MEMSR_A17 MEMDR_CASn PIO01 B1 BSCAN_TRSTn M11 MEMSR_A18 MEMDR_DQM0 PIO02 C1 TEST C7 MEMSR_A19 PIO03 C2 TMC1 C11 MEMSR_A20 PIO04 D1 TMC2 E13 MEMSR_A21 PIO05 D2 MEMSR_A22 MEMSR_CS3n PIO06 E1 MEMSR_A23 MEMSR_CS2n PIO07 E2 DPM MEM_D00 ETM_TPKT08 PIO32 DPM_D00 H15 DPM_A00 MEM_A00 MEMSR_DQM0 PIO40 A10 MEM_D01 ETM_TPKT09 PIO33 DPM_D01 G15 DPM_A01 MEM_A01 PIO41 B9 MEM_D02 ETM_TPKT10 PIO34 DPM_D02 F15 DPM_A02 MEM_A02 PIO42 A9 MEM_D03 ETM_TPKT11 PIO35 DPM_D03 E15 DPM_A03 MEM_A03 PIO43 B8 MEM_D04 ETM_TPKT04 PIO36 DPM_D04 D15 DPM_A04 MEM_A04 PIO44 A8 MEM_D05 ETM_TPKT05 PIO37 DPM_D05 C15 DPM_A05 MEM_A05 PIO45 B7 MEM_D06 ETM_TPKT06 PIO38 DPM_D06 B15 DPM_A06 MEM_A06 PIO46 ETM_PSTAT0 A7 MEM_D07 ETM_TPKT07 PIO39 DPM_D07 A14 DPM_A07 MEM_A07 PIO47 ETM_PSTAT1 B6 MEM_D08 SDPM_MISO PIO08 DPM_D08 H14 DPM_A08 MEM_A08 PIO48 ETM_PSTAT2 A6 MEM_D09 SDPM_MOSI PIO09 DPM_D09 G14 DPM_A09 MEM_A09 PIO49 ETM_TPKT00 B5 MEM_D10 SDPM_CSn PIO10 DPM_D10 F14 DPM_A10 MEM_A10 PIO50 ETM_TPKT01 A5 MEM_D11 SDPM_CLK PIO11 DPM_D11 E14 DPM_A11 MEM_A11 PIO51 ETM_TPKT02 B4 MEM_D12 ETM_TPKT12 PIO12 DPM_D12 D14 DPM_A12 MEM_A12 PIO52 ETM_TPKT03 A4 MEM_D13 ETM_TPKT13 PIO13 DPM_D13 C14 DPM_A13 MEM_A13 PIO53 ETM_DREQ B3 MEM_D14 ETM_TPKT14 PIO14 DPM_D14 B14 DPM_A14 MEM_A14 MEMDR_BA0 PIO54 ETM_TCLK A3 MEM_D15 ETM_TPKT15 PIO15 DPM_D15 A13 DPM_A15 MEMSR_A15 MEMDR_BA1 PIO55 ETM_TSYNC B2 DPM_A16 MEMSR_A16 MEMDR_RASn PIO00 ETM_DACK A2 MEMDR_BA0 MEMSR_A14 ETM_TCLK PIO54 DPM_A14 A3 MEMDR_BA1 MEMSR_A15 ETM_TSYNC PIO55 DPM_A15 B2 DPM_D00 MEM_D00 PIO32 ETM_TPKT08 H15 MEMDR_CLK PIO63 DPM_SIRQ A12 DPM_D01 MEM_D01 PIO33 ETM_TPKT09 G15 MEMDR_CKE MEMSR_OEn PIO58 DPM_RDn B10 DPM_D02 MEM_D02 PIO34 ETM_TPKT10 F15 MEMDR_CSn PIO62 DPM_DIRQ G12 DPM_D03 MEM_D03 PIO35 ETM_TPKT11 E15 MEMDR_DQM0 MEMSR_A18 PIO02 C1 DPM_D04 MEM_D04 PIO36 ETM_TPKT04 D15 MEM_DQM1 PIO57 DPM_BHEn B13 DPM_D05 MEM_D05 PIO37 ETM_TPKT05 C15 MEMDR_RASn MEMSR_A16 ETM_DACK PIO00 DPM_A16 A2 DPM_D06 MEM_D06 PIO38 ETM_TPKT06 B15 MEMDR_CASn MEMSR_A17 PIO01 B1 DPM_D07 MEM_D07 PIO39 ETM_TPKT07 A14 MEMDR_WEn MEMSR_WRn PIO59 DPM_WRn B11 DPM_D08 MEM_D08 SDPM_MISO PIO08 H14 DPM_D09 MEM_D09 SDPM_MOSI PIO09 G14 MEMSR_CSn PIO60 DPM_CSn B12 DPM_D10 MEM_D10 SDPM_CSn PIO10 F14 MEMSR_DQM0 MEM_A00 PIO40 DPM_A00 A10 DPM_D11 MEM_D11 SDPM_CLK PIO11 E14 MEM_DQM1 PIO57 DPM_BHEn B13 DPM_D12 MEM_D12 SDPM_DIRQ PIO12 ETM_TPKT12 D14 MEMSR_OEn MEMDR_CKE PIO58 DPM_RDn B10 DPM_D13 MEM_D13 SDPM_SIRQ PIO13 ETM_TPKT13 C14 MEMSR_RDY PIO61 DPM_RDYn A11 DPM_D14 MEM_D14 PIO14 ETM_TPKT14 B14 MEMSR_WRn MEMDR_WEn PIO59 DPM_WRn B11 DPM_D15 MEM_D15 PIO15 ETM_TPKT15 A13 MEMSR_CS1n MEMDR_CSn PIO62 DPM_DIRQ G12 DPM_BHEn MEM_DQM1 PIO57 B13 MEMSR_CS2n MEMSR_A23 PIO06 E1 DPM_CSn MEMSR_CSn PIO60 B12 MEMSR_CS3n MEMSR_A22 PIO07 E2 DPM_RDn MEMSR_OEn MEMDR_CKE PIO58 B10



Signal Shared with Pin Signal Shared with Pin XC PIO32 MEM_D00 ETM_TPKT08 DPM_D00 H15 PIO33 MEM_D01 ETM_TPKT09 DPM_D01 G15 XM_TX XM_TX_ECLK FO_TD MMIO01 P14 PIO34 MEM_D02 ETM_TPKT10 DPM_D02 F15 XM_TXOE XM_TXOE_ECLK FO_SD MMIO03 P13 PIO35 MEM_D03 ETM_TPKT11 DPM_D03 E15 XM_ECLK FB_CLK FO_FN_EN MMIO02 R13 PIO36 MEM_D04 ETM_TPKT04 DPM_D04 D15 XM_TX_ECLK XM_TX FO_TD MMIO01 P14 PIO37 MEM_D05 ETM_TPKT05 DPM_D05 C15 XM_TXOE_ECLK XM_TXOE FO_SD MMIO03 P13 PIO38 MEM_D06 ETM_TPKT06 DPM_D06 B15 FB_CLK XM_ECLK FO_FN_EN MMIO02 R13 PIO39 MEM_D07 ETM_TPKT07 DPM_D07 A14 PIO40 MEMSR_DQM0 MEM_A00 DPM_A00 A10 PIO41 MEM_A01 DPM_A01 B9 PHY PIO42 MEM_A02 DPM_A02 A9 PIO43 MEM_A03 DPM_A03 B8 PHY_ATP M15 PIO44 MEM_A04 DPM_A04 A8 PHY_EXTRES L12 PIO45 MEM_A05 DPM_A05 B7 PHY_VDDCAP M14 PIO46 MEM_A06 ETM_PSTAT0 DPM_A06 A7 PHY_VDDCART K12 PIO47 MEM_A07 ETM_PSTAT1 DPM_A07 B6 PHY_VDDIOAC M13 PIO48 MEM_A08 ETM_PSTAT2 DPM_A08 A6 PHY_VDDIOAT J12 PIO49 MEM_A09 ETM_TPKT00 DPM_A09 B5 PHY_VSSACP M12 PIO50 MEM_A10 ETM_TPKT01 DPM_A10 A5 PHY_VSSAR K13 PIO51 MEM_A11 ETM_TPKT02 DPM_A11 B4 PHY_VSSAT1 K11 PIO52 MEM_A12 ETM_TPKT03 DPM_A12 A4 PHY_VSSAT2 L13 PIO53 MEM_A13 ETM_DREQ DPM_A13 B3 PHY_VSSAT J11 PIO54 MEMSR_A14 MEMDR_BA0 ETM_TCLK DPM_A14 A3 PHY_RXP K14 PIO55 MEMSR_A15 MEMDR_BA1 ETM_TSYNC DPM_A15 B2 PHY_RXN K15 PHY_TXP L14 PIO57 MEM_DQM1 DPM_BHEn B13 PHY_TXN L15 PIO58 MEMSR_OEn MEMDR_CKE DPM_RDn B10 PIO59 MEMSR_WRn MEMDR_WEn DPM_WRn B11 FO_RD MMIO00 R14 PIO60 MEMSR_CSn DPM_CSn B12 FO_TD MMIO01 XM_TX XM_TX_ECLK P14 PIO61 MEMSR_RDY DPM_RDYn A11 FO_SD MMIO03 XM_TXOE XM_TXOE_ECLK P13 PIO62 MEMSR_CS1n MEMDR_CSn DPM_DIRQ G12 FO_FN_EN MMIO02 XM_ECLK FB_CLK R13 PIO63 MEMDR_CLK DPM_SIRQ A12 I/O PWM MMIO00 FO_RD R14 PWM0 MMIO04 R12 MMIO01 XM_TX XM_TX_ECLK FO_TD P14 PWM1 MMIO05 P12 MMIO02 XM_ECLK FB_CLK FO_FN_EN R13 PWM2 MMIO06 R11 MMIO03 XM_TXOE XM_TXOE_ECLK FO_SD P13 PWM3 MMIO07 P11 MMIO04 PWM0 R12 PWM4 MMIO08 R3 MMIO05 PWM1 P12 PWM5 MMIO09 P3 MMIO06 PWM2 R11 PWM6 MMIO10 R2 MMIO07 PWM3 P11 PWM7 MMIO11 P2 MMIO08 PWM4 R3 MMIO09 PWM5 P3 MMIO10 PWM6 R2 ADC MMIO11 PWM7 P2 MMIO12 F12 ADC0_IN0 R8 MMIO13 E12 ADC0_IN1 M8 MMIO14 D12 ADC0_IN2 P8 MMIO15 D11 ADC0_IN3 L8 MMIO16 D10 ADC0_IN4 R9 MMIO17 D9 ADC0_IN5 M9 MMIO18 D8 ADC0_IN6 P9 MMIO19 D7 ADC0_IN7 L9 MMIO20 D6 ADC0_VDDIO N8 MMIO21 D5 ADC0_VSS P10 MMIO22 E4 ADC0_VREFP R7 MMIO23 F4 ADC0_VREFM R10 ADC1_IN0 R4 PIO00 MEMSR_A16 MEMDR_RASn ETM_DACK DPM_A16 A2 ADC1_IN1 M5 PIO01 MEMSR_A17 MEMDR_CASn B1 ADC1_IN2 P5 PIO02 MEMSR_A18 MEMDR_DQM0 C1 ADC1_IN3 L6 PIO03 MEMSR_A19 C2 ADC1_IN4 R5 PIO04 MEMSR_A20 D1 ADC1_IN5 M6 PIO05 MEMSR_A21 D2 ADC1_IN6 P6 PIO06 MEMSR_A22 MEMSR_CS3n E1 ADC1_IN7 L7 PIO07 MEMSR_A23 MEMSR_CS2n E2 ADC1_VDDIO N4 PIO08 MEM_D08 SDPM_MISO DPM_D08 H14 ADC1_VSS M7 PIO09 MEM_D09 SDPM_MOSI DPM_D09 G14 ADC1_VREFP P4 PIO10 MEM_D10 SDPM_CSn DPM_D10 F14 ADC1_VREFM R6 PIO11 MEM_D11 SDPM_CLK DPM_D11 E14 PIO12 MEM_D12 ETM_TPKT12 DPM_D12 D14 PIO13 MEM_D13 ETM_TPKT13 DPM_D13 C14 PIO14 MEM_D14 ETM_TPKT14 DPM_D14 B14 PIO15 MEM_D15 ETM_TPKT15 DPM_D15 A13



Signal Shared with Pin Signal Pin ETM Power ETM_TCLK MEMSR_A14 MEMDR_BA0 PIO54 DPM_A14 A3 ETM_TSYNC MEMSR_A15 MEMDR_BA1 PIO55 DPM_A15 B2

VDDIO C5, C9, C13, E3, G13, J2, L3, N12, P7

ETM_DREQ MEM_A13 PIO53 DPM_A13 B3 ETM_DACK MEMSR_A16 MEMDR_RASn PIO00 DPM_A16 A2 ETM_PSTAT0 MEM_A06 PIO46 DPM_A06 A7

VDDC E5, E8, E10, F11, G5, H12, J13, J14, L5, L11, M4, M10, N7, N15

ETM_PSTAT1 MEM_A07 PIO47 DPM_A07 B6 ETM_PSTAT2 MEM_A08 PIO48 DPM_A08 A6 ETM_TPKT00 MEM_A09 PIO49 DPM_A09 B5 VSS C4, C6, C8, C10, C12, D3, D13, F13, G4, H13, H5, J15, K2, M3,

N5, N6, N10, N11, N14, P15 ETM_TPKT01 MEM_A10 PIO50 DPM_A10 A5 ETM_TPKT02 MEM_A11 PIO51 DPM_A11 B4 ETM_TPKT03 MEM_A12 PIO52 DPM_A12 A4 ETM_TPKT04 MEM_D04 PIO36 DPM_D04 D15 ETM_TPKT05 MEM_D05 PIO37 DPM_D05 C15 No connect C3, D4, E6, E7, E9, E11, F3, F5, F6, G11, H11, K3, K5, L10, N3,

N9, N13 ETM_TPKT06 MEM_D06 PIO38 DPM_D06 B15 ETM_TPKT07 MEM_D07 PIO39 DPM_D07 A14 ETM_TPKT08 MEM_D00 PIO32 DPM_D00 H15 ETM_TPKT09 MEM_D01 PIO33 DPM_D01 G15 ETM_TPKT10 MEM_D02 PIO34 DPM_D02 F15 ETM_TPKT11 MEM_D03 PIO35 DPM_D03 E15 ETM_TPKT12 MEM_D12 PIO12 DPM_D12 D14 ETM_TPKT13 MEM_D13 PIO13 DPM_D13 C14 ETM_TPKT14 MEM_D14 PIO14 DPM_D14 B14 ETM_TPKT15 MEM_D15 PIO15 DPM_D15 A13



4.8 Pin overview

4.8.1 Overview 1

Pinning netX 10 Top view

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

A

DPM_A16 MEMSR_A16

MEMDR_RASn PIO00

ETM_DACK

DPM_A14 MEMSR_A14 MEMDR_BA0

PIO54 ETM_TCLK

DPM_A12 MEM_A12

PIO52 ETM_TPKT03

DPM_A10 MEM_A10

PIO50 ETM_TPKT01

DPM_A08 MEM_A08

PIO48 ETM_PSTAT2

DPM_A06 MEM_A06

PIO46 ETM_PSTAT0

DPM_A04 MEM_A04

PIO44

DPM_A02 MEM_A02

PIO42

DPM_A00 MEM_A00

MEMSR_DQM0 PIO40

DPM_RDY MEMSR_RDY

PIO61

MEMDR_CLK DPM_SIRQ

PIO63

DPM_D15 MEM_D15

PIO15 ETM_TPKT15

DPM_D07 MEM_D07

PIO39 ETM_TPKT07

B MEMSR_A17

MEMDR_CASn PIO01


PIO55 ETM_TSYNC

DPM_A13 MEM_A13

PIO53 ETM_DREQ

DPM_A11 MEM_A11

PIO51 ETM_TPKT02

DPM_A09 MEM_A09

PIO49 ETM_TPKT00

DPM_A07 MEM_A07

PIO47 ETM_PSTAT1

DPM_A05 MEM_A05

PIO45

DPM_A03 MEM_A03

PIO43

DPM_A01 MEM_A01

PIO41

DPM_RDn MEMSR_OEn MEMDR_CKE

PIO58

DPM_WRn MEMSR_WRn MEMDR_WEn

PIO59

DPM_CSn MEMSR_CSn

PIO60

DPM_BHEn MEM_DQM1

PIO57

DPM_D14 MEM_D14

PIO14 ETM_TPKT14

DPM_D06 MEM_D06

PIO38 ETM_TPKT06

C MEMSR_A18

MEMDR_DQM0 PIO02

MEMSR_A19 PIO03 NC VSS VDDIO VSS TEST VSS VDDIO VSS TMC1 VSS VDDIO

DPM_D13 MEM_D13

PIO13 ETM_TPKT13

DPM_D05 MEM_D05

PIO37 ETM_TPKT05

D MEMSR_A20 PIO04

MEMSR_A21 PIO05 VSS NC MMIO21 MMIO20 MMIO19 MMIO18 MMIO17 MMIO16 MMIO15 MMIO14 VSS

DPM_D12 MEM_D12

PIO12 ETM_TPKT12

DPM_D04 MEM_D04

PIO36 ETM_TPKT04

E MEMSR_A22

MEMSR_CS3n PIO06

MEMSR_A23 MEMSR_CS2n

PIO07 VDDIO MMIO22 VDDC NC NC VDDC NC VDDC NC MMIO13 TMC2

DPM_D11 MEM_D11

PIO11 SDPM_CLK

DPM_D03 MEM_D03

PIO35 ETM_TPKT11

F OSC_XTI JT_TDI NC MMIO23 NC NC VDDC MMIO12 VSS

DPM_D10 MEM_D10

PIO10 SDPM_CSn

DPM_D02 MEM_D02

PIO34 ETM_TPKT10

G OSC_XTO JT_TDO BIST_TRSTn VSS VDDC NC DPM_DIRQ

MEMDR_CSn PIO62

VDDIO

DPM_D09 MEM_D09

PIO09 SDPM_MOSI

DPM_D01 MEM_D01

PIO33 ETM_TPKT09

H RDY RUN OSC_VSS JT_TMS VSS NC VDDC VSS

DPM_D08 MEM_D08

PIO08 SDPM_MISO

DPM_D00 MEM_D00

PIO32 ETM_TPKT08

PHY_VSSAT PHY_VDDIOAT J USB_DNEG VDDIO OSC_VDDC USB_VSS USB_VDDIO

VDDC VDDC VSS

PHY_VSSAT1 PHY_VDDCART PHY_VSSAR K USB_DPOS VSS NC JT_TCLK NC

PHY_RXP PHY_RXN

PHY_VSSAT2 L PORn SPI0_CS0n VDDIO JT_TRSTn VDDC ADC1_IN3 ADC1_IN7 ADC0_IN3 ADC0_IN7 NC VDDC PHY_EXTRES

PHY_TXP PHY_TXN

ADC1_VSS PHY_VSSACP PHY_VDDIOAC PHY_VDDCAP M SPI0_SIO2 SPI0_SIO3 VSS VDDC ADC1_IN1 ADC1_IN5

ADC0_IN1 ADC0_IN5 VDDC BSCAN_TRSTn

PHY_ATP

ADC1_VDDIO ADC0_VDDIO N SPI0_MISO SPI0_MOSI NC

VSS VSS VDDC

NC VSS VSS VDDIO NC VSS VDDC

ADC1_VREFP ADC0_VSS P SPI0_CLK MMIO11 PWM7

MMIO09 PWM5

ADC1_IN2 ADC1_IN6 VDDIO ADC0_IN2 ADC0_IN6

MMIO07 PWM3

MMIO05 PWM1

MMIO03 XM_TXOE

XM_TXOE_ECLKFO_SD

MMIO01 XM_TX

XM_TX_ECLK FO_TD

VSS

ADC1_VREFM ADC0_VREFP ADC0_VREFM R MMIO10 PWM6

MMIO08 PWM4 ADC1_IN0 ADC1_IN4

ADC0_IN0 ADC0_IN4

MMIO06 PWM2

MMIO04 PWM0

MMIO02 XM_ECLK FB_CLK

FO_FN_EN

MMIO00 FO_RD

IO-Power (3.3V) Core-Power (1.5V) Ground

USB ADC RDY / RUN

DPM / MEM MMIO PHY

XTAL / Reset JTAG / Test SPI



4.8.2 Overview 2 (b/w)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

A

DPM_A16 MEMSR_A16

MEMDR_RASn PIO00

ETM_DACK


PIO54 ETM_TCLK

DPM_A12 MEM_A12

PIO52 ETM_TPKT03

DPM_A10 MEM_A10

PIO50 ETM_TPKT01

DPM_A08 MEM_A08

PIO48 ETM_PSTAT2

DPM_A06 MEM_A06

PIO46 ETM_PSTAT0

DPM_A04 MEM_A04

PIO44

DPM_A02 MEM_A02

PIO42

DPM_A00 MEM_A00

MEMSR_DQM0 PIO40

DPM_RDY MEMSR_RDY

PIO61

MEMDR_CLK DPM_SIRQ

PIO63

DPM_D15 MEM_D15

PIO15 ETM_TPKT15

DPM_D07 MEM_D07

PIO39 ETM_TPKT07

B MEMSR_A17

MEMDR_CASn PIO01


PIO55 ETM_TSYNC

DPM_A13 MEM_A13

PIO53 ETM_DREQ

DPM_A11 MEM_A11

PIO51 ETM_TPKT02

DPM_A09 MEM_A09

PIO49 ETM_TPKT00

DPM_A07 MEM_A07

PIO47 ETM_PSTAT1

DPM_A05 MEM_A05

PIO45

DPM_A03 MEM_A03

PIO43

DPM_A01 MEM_A01

PIO41

DPM_RDn MEMSR_OEn MEMDR_CKE

PIO58

DPM_WRn MEMSR_WRn MEMDR_WEn

PIO59

DPM_CSn MEMSR_CSn

PIO60

DPM_BHEn MEM_DQM1

PIO57

DPM_D14 MEM_D14

PIO14 ETM_TPKT14

DPM_D06 MEM_D06

PIO38 ETM_TPKT06

C MEMSR_A18

MEMDR_DQM0 PIO02

MEMSR_A19 PIO03 NC VSS VDDIO VSS TEST VSS VDDIO VSS TMC1 VSS VDDIO

DPM_D13 MEM_D13

PIO13 ETM_TPKT13

DPM_D05 MEM_D05

PIO37 ETM_TPKT05

D MEMSR_A20 PIO04

MEMSR_A21 PIO05 VSS NC MMIO21 MMIO20 MMIO19 MMIO18 MMIO17 MMIO16 MMIO15 MMIO14 VSS

DPM_D12 MEM_D12

PIO12 ETM_TPKT12

DPM_D04 MEM_D04

PIO36 ETM_TPKT04

E MEMSR_A22 PIO06

MEMSR_A23 PIO07 VDDIO MMIO22 VDDC NC NC VDDC NC VDDC NC MMIO13 TMC2

DPM_D11 MEM_D11

PIO11 SDPM_CLK

DPM_D03 MEM_D03

PIO35 ETM_TPKT11

F OSC_XTI JT_TDI NC MMIO23 NC NC VDDC MMIO12 VSS DPM_D10 MEM_D10

PIO10 SDPM_CSn

DPM_D02 MEM_D02

PIO34 ETM_TPKT10

G OSC_XTO JT_TDO BIST_TRSTn VSS VDDC NC DPM_DIRQ

MEMDR_CSn PIO62

VDDIO

DPM_D09 MEM_D09

PIO09 SDPM_MOSI

DPM_D01 MEM_D01

PIO33 ETM_TPKT09

H RDY RUN OSC_VSS JT_TMS VSS NC VDDC VSS DPM_D08 MEM_D08

PIO08 SDPM_MISO

DPM_D00 MEM_D00

PIO32 ETM_TPKT08

PHY_VSSAT PHY_VDDIOAT J USB_DNEG VDDIO OSC_VDDC USB_VSS USB_VDDIO

VDDC VDDC VSS

PHY_VSSAT1 PHY_VDDCART PHY_VSSAR K USB_DPOS VSS NC JT_TCLK NC

PHY_RXP PHY_RXN

PHY_VSSAT2 L PORn SPI0_CS0n VDDIO JT_TRSTn VDDC ADC1_IN3 ADC1_IN7 ADC0_IN3 ADC0_IN7 NC VDDC PHY_EXTRES

PHY_TXP PHY_TXN

ADC1_VSS PHY_VSSACP PHY_VDDIOAC PHY_VDDCAP M SPI0_SIO2 SPI0_SIO3 VSS VDDC ADC1_IN1 ADC1_IN5

ADC0_IN1 ADC0_IN5 VDDC BSCAN_TRSTn

PHY_ATP

ADC1_VDDIO ADC0_VDDIO N SPI0_MISO SPI0_MOSI NC

VSS VSS VDDC

NC VSS VSS VDDIO NC VSS VDDC

ADC1_VREFP ADC0_VSS P SPI0_CLK MMIO11 PWM7

MMIO09 PWM5

ADC1_IN2 ADC1_IN6 VDDIO ADC0_IN2 ADC0_IN6

MMIO07 PWM3

MMIO05 PWM1

MMIO03 XM_TXOE

XM_TXOE_ECLKFO_SD

MMIO01 XM_TX

XM_TX_ECLK FO_TD

VSS

ADC1_VREFM ADC0_VREFP ADC0_VREFM R MMIO10 PWM6

MMIO08 PWM4 ADC1_IN0 ADC1_IN4

ADC0_IN0 ADC0_IN4

MMIO06 PWM2

MMIO04 PWM0

MMIO02 XM_ECLK FB_CLK

FO_FN_EN

MMIO00 FO_RD



4.9 Mechanical Dimensions / Physical Dimensions

The netX 10 comes in a 197 pin PBGA package. Mechanical Dimensions of the netX 10

Symbol Min. Typ. Max. A1 0.29 mm 0.35 mm 0.41 mm A2 1.13 mm b 0.40 mm 0.50 mm 0.55 mm E 12.90 mm 13.00 mm 13.10 mm e 0.80 mm D 12.90 mm 13.00 mm 13.10 mm



4.10 Material composition

4.10.1 Solder balls

Solder ball weight: 69.5 mg Material CAS No. Amount per ball Concentration Copper 7440-50-8 3.34 mg ~ 0.5 % Tin 7440-31-5 61.10 mg ~ 96.5 % Silver 7440-22-4 2.08 mg ~ 3 %

4.11 Ordering Information

Ordering Number: 2250.000 NETX 10 netX 10 Network Controller (single chip) 2250.100 NETX 10 (BOX) - / - 15 pcs. 2250.200 NETX 10 (TRAY) - / - 152 pcs. 2250.300 NETX 10 (PACKAGE) - / - 240 pcs.

netX10 Technical Data Reference Guide - Preliminary Printed Circuit Board Design • 150


5 Printed Circuit Board Design

5.1 Routing hints

When routing the netX traces keep in mind, that there are some critical signal pairs. Especially the Ethernet differential pairs must be routed close to each other and must be of equal length. Care must be taken when routing the SDRAM interface lines. The SDRAM clock line is a 100 MHz sig-nal line and all the SDRAM bus lines should have equal length and capacitive load. For some applications, serial impedance matching resistors for all SDRAM signals may be required to maintain signal quality. We strongly recommend the use of CAD systems, that support impedance controlled routing to detect and eliminate signal integrity problems in the first place. The main quartz oscillator must be placed close to the netX chip, allowing the signal lines to be directly connected to the netX by short traces. Generally, netX power connections must be as short as possible.

5.2 Vcc Pin Requirements / Decoupling Capacitors

Since most of the power pins of the netX 10 are located on the inner ball rings, most of the power pins must be supplied by internal planes, which should be decoupled properly (on PCBs with double sided mounting, the decoupling capacitors for the inner pins should be placed on the bottom side, close to the pins). Recommended decoupling capacitor types are X7R ceramic type with 100 nF / 6.3 V, which are avail-able in 0603 package. Additionaly, X5R or X7R ceramic capacitors of 10 uF / 6.3 V can be used. They are available in 1206 or 0805 package.

6 Reference PCB Layout Design

An appropriate reference design has not yet been published. It will be downloadable from the Hilscher website (netX Downloads at www.hilscher.com ) as soon as available.

7 Reference Schematics

Appropriate reference schematics have not yet been published. They will be downloadable from the Hilscher website (netX Downloads at www.hilscher.com ) as soon as available. However, the schemat-ics for the NXHX10-ETM (netX10 Evaluationboard) are available for download.



netX10 Technical Data Reference Guide - Preliminary Revision History • 151


8 Revision History

Rev. Date Changes Who 0.9 03-12-2010 Preliminary version published JL Note: The specified date of a change is for (internal) reference only. Date-based revision steps are generally not published, hence a published (released) revision always contains ALL changes applied after the date of the previous revision.

netX10 Technical Data Reference Guide - Preliminary Contacts • 152


9 Contacts

Headquarter Germany Hilscher Gesellschaft für Systemautomation mbH Rheinstrasse 15 65795 Hattersheim Phone: +49 (0) 6190 9907-0 Fax: +49 (0) 6190 9907-50 E-Mail: [email protected] Support Phone: +49 (0) 6190 9907-99 E-Mail: [email protected]

Subsidiaries

China Hilscher Ges.f.Systemaut. mbH Shanghai Representative Office 200010 Shanghai Phone: +86 (0) 21-6355-5161 E-Mail: [email protected] Support Phone: +86 (0) 21-6355-5161 E-Mail: [email protected] France Hilscher France S.a.r.l. 69500 Bron Phone: +33 (0) 4 72 37 98 40 E-Mail: [email protected] Support Phone: +33 (0) 4 72 37 98 40 E-Mail: [email protected] Italy Hilscher Italia srl 20090 Vimodrone (MI) Phone: +39 02 25007068 E-Mail: [email protected] Support Phone: +39 / 02 25007068 E-Mail: [email protected]

Japan Hilscher Japan KK Tokyo, 160-0022 Phone: +81 (0) 3-5362-0521 E-Mail: [email protected] Support Phone: +81 (0) 3-5362-0521 E-Mail: [email protected] Switzerland Hilscher Swiss GmbH 4500 Solothurn Phone: +41 (0) 32 623 6633 E-Mail: [email protected] Support Phone: +49 (0) 6190 9907-99 E-Mail: [email protected] USA Hilscher North America, Inc. Lisle, IL 60532 Phone: +1 630-505-5301 E-Mail: [email protected] Support Phone: +1 630-505-5301 E-Mail: [email protected]

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