“TDAQ for 2012 runs”

Gianluca Lamanna (CERN)

Annual review meeting 02.04.2012

Dry Run & Technical run• The October Technical Run is a good

opportunity to test the TDAQ structure and to readout data for detector calibration.

• The TDAQ is a relatively complex system.• To better take advantage of the beam time

available, it’s mandatory to test all electronics equipments that will be used in the technical run Dry Run will start July 15 (for 1 month)

• Some amendment to this law is possible in case of no interference with other systems.

TDAQ concepts

• For most of the detectors the readout and the definition of trigger primitives is done with the same FPGAs.

• The primitives trigger transmission is asynchronous while trigger decision transmission is synchronous.

DataTrigger primitivesTTC L1 requests

10 MHz

1 MHz

L0TP

TEL62

TEL62

TEL62

L1/L2 PCFARM

dete

ctor

dete

ctor

dete

ctor Asynchronous

Synchronous

100 kHz

10 kHz(1 ms max latency)

TDAQ for 2012

• LAV FEE• CEDAR board• CHANTI board• STRAW readout• CFD board

• TDCB• TEL62• SLM

• L0TP (TALK)• LTU & TTCex• TTC

• PCFarm • Network • Online software• Run Control

Front end electronics

Readout & Trigger

Data acquisition

Overview of 2012 runs TDAQ hardware

# channels (in 2012)

FEE R/O

CEDAR 128 CEDAR board

TDCB+TEL62

CHANTI 46 Chanti board + LAV FEE

TDCB+TEL62

LAV 480 LAV FEE TDCB+TEL62STRAW ~1800 Cover Board

+ SRBTEL62

CHOD 128 LAV FEE TDCB+TEL62LKR ~5000 CPD+SLM PCsMUV2 88 LAV FEE TDCB+TEL62MUV3 296 CFD+TRAM TDCB+TEL62IRC/SAC 8 LAV FEE TDCB+TEL62

LAV FEE board• ToT (Time Over Threshold) with

large dynamic range• Double threshold

– Redundant front end– Slewing correction

• Control PC, pulser and signal sum

• 9U board with mezzanines– 32 input, 64 output

• 31 boards in production– Ready and tested for the

end of May

Detector LAVFEE

CHANTI 2LAV 15

CHOD 4

MUV2 9

SAC/IRC 1

CEDAR board• “Amplificator-free” board

to house NINO chips.• The differential signals

are obtained using the last dinode.

• 128+5% special PM sockets in production (end of may).

• The final board design is started: final tested board ready for the middle of July.

• Since the PMs will be installed after the Dry Run, a procedure to pulse the NINOs from the readout is foreseen.

CHANTI board• CHANTI board:

– Provides Vbias for SiPM– Fast amplification – Reads currents (nA) for

monitoring– Reads temperatures

probes• 4 channels prototype

has been built:– Standalone lab test

passed– Test with the CHANTI

prototype are ongoing• The final board will be

ready at the end of June

CHAN

TI CHANTI board32 Ch.

LAV FEE board32 Ch

STRAW readout

• Cover board and SRB (Straw Readout Board) prototypes are ready:– Cover board final production in June– SRB final prototype will be ready in June with a

simplified version of the firmware.– TEL62 daughter board prototype ready in October

• In the Technical Run the readout will be done using VME (fall back solution), in case the daughter board will not be ready.

STRA

W (1

vie

w) SRBCover boardCover boardCover boardCover boardCover boardCover boardCover boardCover boardCover boardCover board

SRB

SRB

… 30 boards per view…

TEL62 daughter board

VME

CFD• The CFD (Constant Fraction Discriminator) coming from

the NA48 AKL readout system will be reused for the MUV3 frontend this year

• We need 19 boards:– We have already 18 working boards (additional tests

needed)– We will produce few additional boards (3 or 4),

probably ready in July• A level adaptor board (TRAM-TRAnslator for Muon

veto) will be ready in June

MUV3 Patch panel

CFD ECL->LVDS (TRAM board) TDCB/

TEL62

RG58 LemoFlat cable

TDCB cable

EB24

TEL62

• The TEL62 is a main board to digitize (using daughter boards), buffer data and to build trigger primitives.

• It’s an evolution of the LHCb TELL1 board.• 13 boards in production: will be ready at the end

of April.• Special crates ordered will arrive after Easter.

Detector TEL62CEDAR 1CHANTI 1LAV 3STRAW 1CHOD 1LKR/L0 3MUV2 1MUV3 1SAC/IRC 1

TEL62 Firmware

• A prototype firmware for the readout will be ready in May.

• The firmware to produce trigger primitives depends on the manpower (see later).

TDCB

• The TDCB board is a TEL62 mezzanine.• 4 HPTDC for a total of 128 channels per board

(512 per TEL62). • 12 boards already distributed to sub-detectors

groups.• 12 additional boards will be ready at the end of

April.

Detector TDCBCEDAR 1CHANTI 1LAV 9CHOD 2MUV2 2MUV3 3SAC/IRC 1

SLM & TALK board

• 40% of the channels are already equipped with new Fastbus power supply.

• The CREAM (Calorimeter REAdout Module) system will be ready in 2013.

• For the 2012 runs we will use the old readout (CPD (Calorimeter Pipeline Digitizer)) with the SLM (Smart Link Modules) to bring data inside readout PCs.

• The trigger distribution will be done using the TALK (Trigger Adaptor for LKr) board.

PP

PP

PP

PP

SL

TTC

TAXI

TALK FPGA

To CPD

to R/O PC

TEL62

TALK board as L0TP• The TALK board will be

used during the 2012 runs as L0TP (L0 Trigger Processor)

• FPGA, 5 Ethernet connectors, input/output LEMOs, RJ11 for choke/error, connector for the LTU (Local Trigger Unit), connection with the TEL62.

• The board is ready and tested.

• The firmware is almost ready.

Triggering with TALK board• Two ways:

– With LEMO.– Using the primitives

produced inside the TEL62.

• The use of the asynchronous primitives is the baseline solution. This depends on the specific firmware inside the TEL62.

• The fall back solution will be done using the signals coming directly from the FEE boards.

TEL62

TALKeth

LAV

TALK

CHOD

lemo

Trigger partition: LTU & TTCex• The L0TP will communicate

trigger decision through TTC system.

• The trigger partition for each detector is composed by LTU+TTCex and optical splitters.

• The LTU+TTCex for 2012 runs has been already produced and distributed to the sub-detectors groups.

• The firmware and the control software are complete.

Clock & Trigger distribution• The fibers for clock & trigger distribution will be installed this week.• The copper cables for choke/error will be installed after the fibers.• A board to make the control signals “local OR” (CHEF – CHoke and Error Fan in) has been designed and will be ready in June.

HP2910

PCFarm & Network

• 7 x HP2910 already bought.• HP8212 ordered with 3 “8x10Gb/s”

modules and 1 “24x1 Gb/s” module (middle of May).

• Six 12 cores PCs foreseen for this year (to partially test the switches):– 2 already available.– 4 to be buy soon.

• 10 Racks with cooling door ordered (end of April).

HP8212

PCFarm

HP2910

HP8219

1 Gb/s copper10 Gb/s fiber

Readout software & Run Control

• Readout software almost ready: prototype at the end of April.

• Run Control program in preparation in collaboration with the EN/ICE group: base on PVSS, SMI++ and DIM.

Summary • Most of the Hardware will be ready in

June.• We will have readout firmware for

TEL62 in May. We hope to have the firmware to test the asynchronous part of the TDAQ system (it depends on man power).

• Network, trigger distribution and control lines infrastructure will be completed in April.

• The PCFarm and the software will be tested in May.

SPARES

GPU• During the Dry Run/Technical run we have the unique

possibility to test a real “demonstrator” parasitically connected to the TDAQ.

• We are preparing a framework to run efficiently GPU algorithms.

• For this year we will try to make the CHOD corrections in the GPU.

• Some work is needed on the TEL62 firmware to send out reduced data for the GPU.

TRAM board

• The schematic has been prepared by Riccardo and my self

• Mainz will take care to make the layout and to produce the board

• TRAnslator for Muon veto

• ECLTTLLVDS• Each board: 64 inputs

on 4 cables, two TDCB standard cable in outputs

• 9U TEL62 format (+5V, -5V, +3.3V from the connector)

CHEF Board

• CHoke and Error Fan in• 8 inputs, 3 outputs (one common

output, two 4 channels output)• VME 6U for LKr, 1U format (with

external power supply) for other detectors

• LAV (already in 2012), CEDAR, STRAW, RICH, MUV, LKr

crate

Patch panel

CHEF

CHOD FEE• CHOD is evaluating two

possibilities for the readout:– Florence NINO board with

attenuation – LAV FEE (baseline)

• The advantage to use the NINO board is in the number of TDC channels (128 instead of 256)

• An attenuation of ¼ isn’t enough to go in the linearity region of the NINO

• A greater factor could affect the efficiency

LKr Trigger distribution• The TALK board will be

used for the LKr trigger distribution

• The TAXI has been tested in the Lab, we need to test it in the real system

clock

PECL TAXI receiver

TALK firmware

Data pulser• Both in LAVFEE and in the CEDAR FEE

it’s possible to generate pulses using the last pair in the TDC cable.

• The TEL62 can trigger the pulser.• The signal TEL62TDCBFEE is sent

for pre-decided timestamps; at the same time the L0TP will produce a trigger request.

• For the LKr the same things can be done using one TALK board output.

PulserTDCB

TTC

Data

TEL62

L0TP

Cedar NINO Board

tTEL62

L0TP

Timestamp: 0xA0A0A0A0Send pulser signal to FEE

Timestamp: 0xA0A0A0A0Send calibration trigger request1 ms