Task 2.2 Update5/10/2011

1

Task 2.2 Update5th October 2011Agrate, Milano

2Task 2.2 Update

5/10/2011

Contents

- Deliverables

- Completed Deliverables

- Final Deliverable

3Task 2.2 Update

5/10/2011

Contents

- Deliverables

- Completed Deliverables

- Final Deliverable

4Task 2.2 Update

5/10/2011

T2.2 Deliverables

DeliveraDeliverableble

ContributoContributorsrs

TitleTitle

D2.2.1 UNGL

Assessment of state-of-the-art TCAD methodology and usability concerning PV for industrial purposes including identification of current deficiencies of tools

D.2.2.2 UNGL, UNET, ST-I, SNPS

Device simulation analysis of dominant variability sources in 45nm planar bulk CMOS technologies and and Discrete Power Device,SiC, GaN/AlGaN technologies. Prototype implementation of the treatment of individual dopants and traps in the device modeling tools

D.2.2.3 UNET UNGL, NMX, SNPS

Device simulation analysis of dominant variability sources in state-of-the-art Non-Volatile-Memory technologies

5Task 2.2 Update

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T2.2 DeliverablesDeliveraDelivera

blebleContributoContributo

rsrsTitleTitle

D2.2.4 UNGL, IMEP,UNET, POLI

Forecast of the magnitude of statistical variability in 32nm planar bulk CMOS devices via device simulation Efficient compact model extraction procedures for modeling process variations and device fluctuations

D.2.2.5 UNET, UNGL

Application of mixed-mode device-circuit simulations for the analysis of the impact of fluctuations TCAD based assessment of PV effects of potential 22nm device architectures

D.2.2.6 NMX,UNGL,STF2

Sensitivity analysis of NVM device performance as a function of individual trap position Toolbox (methodologies, models, tools) to make dominant variability effects accessible to industrial usage of TCAD Outlook to 16nm device architecture robustness using MASTAR

6Task 2.2 Update

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Contents

- Deliverables

- Completed Deliverables

- Final Deliverable

7Task 2.2 Update

5/10/2011

Previously Reported

D2.2.1 UNGL

Assessment of state-of-the-art TCAD methodology and usability concerning PV for industrial purposes including identification of current deficiencies of tools

D.2.2.2 UNGL, UNET, ST-I, SNPS

Device simulation analysis of dominant variability sources in 45nm planar bulk CMOS technologies and and Discrete Power Device,SiC, GaN/AlGaN technologies. Prototype implementation of the treatment of individual dopants and traps in the device modeling tools

D.2.2.3 UNET UNGL, NMX, SNPS

Device simulation analysis of dominant variability sources in state-of-the-art Non-Volatile-Memory technologies

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T2.2 Deliverables

- What was accomplished?

- Statistical Variability in 32nm Bulk CMOS Technology, and in Nanowires.

- Statistical Variability in DPD, SiC, GaN/AlGaN Technologies

- Compact Modelling Strategies for Statistical Variability

D2.2.4 UNGL, IMEP,UNET, POLI

Forecast of the magnitude of statistical variability in 32nm planar bulk CMOS devices via device simulation Efficient compact model extraction procedures for modeling process variations and device fluctuations

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D2.2.4: Statistical Variability in 32nm Bulk CMOS Technology

UNGL Contribution

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IUNET Contribution

D2.2.4: Statistical Variability in 32nm Bulk CMOS Technology

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RVT-NMOS RVT-PMOS

RVT-NMOSSNPS Contribution

RVT-PMOS

D2.2.4: Statistical Variability in 32nm Bulk CMOS Technology

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IMEP Contribution

D2.2.4: Statistical Variability in Nanowire technology

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PCM STUDIO

EHD5 SEMICELL

SENTAURUS WORKBENCH

DOE

PCM

ST-I Contribution

D2.2.4: Statistical Variability in DPD, SiC, GaN/AlGaN Technologies

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POLI Contribution

D2.2.4: Statistical Variability in DPD, SiC, GaN/AlGaN Technologies

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RVT-NMOSUNGL Contribution

D2.2.4: Compact Modelling Strategies for Statistical Variability

RVT-PMOS

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Source Drain

a

s (surface potential) (conductivity)

Gate

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NMOS - 0.12µmx5µm

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IMEP Contribution

D2.2.4: Drain Current Variability in 45nm Bulk N-MOSFET

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T2.2 Deliverables

- What was accomplished?

- UNGL: Creation and Study of Variability in 22nm FinFET

- IUNET Contribution

D.2.2.5 UNET, UNGL

Application of mixed-mode device-circuit simulations for the analysis of the impact of fluctuations TCAD based assessment of PV effects of potential 22nm device architectures

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UNGL Contribution

D2.2.5: UNGL: Variability in 22nm FinFET

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D2.2.5: IUNET Contribution

Deliverable delayed but has been completed and submitted.

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Contents

- Deliverables & Timeline

- Completed Deliverables

- Final Deliverable

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Final T2.2 DeliverableRef Deliverable/ Contributors Due date

D2.2.6 Sensitivity analysis of Non Volatile Memory device performance as a function of individual trap position (NMX,UNET,POLI,SNPS,UNGL)

Toolbox (methodologies, models, tools) to make dominant variability effects accessible to industrial usage of TCAD (SNPS,UNGL)

Outlook to 16nm device architecture robustness using MASTAR (STF2)

M36

Plans and Initial Progress

NMX contribution (in collab. with IUNET-MI)Task 2.2D2.2.6

Andrea Ghetti, Augusto Benvenuti

Investigation of RDF and RTN depedence on Substrate Doping

• Investigated different doping profile varying along the length, width and depth of the device

• Doping engineering in the vertical direction most effective in reducing RDF

• RTN reduces more putting dopant atoms as far as possible from the interface

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T2.2 publication list

• Journals• Gareth Roy, Andrea Ghetti, Augusto Benvenuti, Axel Erlebach, Asen Asenov, “Comparative Simulation Study of

the Different Sources of Statistical Variability in Contemporary Floating Gate Non-Volatile Memory”, IEEE-TED, in press

• Workshops• Conferences Proceedings• A. Ghetti, S.M. Amoroso, A. Mauri, C. Monzio Compagnoni , "Doping Engineering for Random Telegraph Noise

Suppression in Deca-nanometer Flash Memories“, International Memory Workshop 2011, p. 91, Monterey, CA; 5/22-25/2011

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25© Synopsys 2011 25© Synopsys 2011

SNPS ContributionT2.2

D2.2.6

26© Synopsys 2011 26© Synopsys 2011

Implementations

Implementation Available since Release

Application

Geometrical noise analysis in 2D and 3D

2010.12 Applied to 32 and 45nm bulk devices (ST Crolles, see D2.2.2 and D2.2.4), 32nm NVM (Micron, see D2.2.3), and to FinFET devices (NXP); implementation is explained in D5.3.2

Random dopant fluctuation

Implemented before project start

Applied to 32 and 45nm bulk devices (ST Crolles, see D2.2.2 and D2.2.4), 32nm NVM (Micron, see D2.2.3), and to FinFET devices (NXP)

Single traps 2010.03 Ongoing work for NVM (Micron, planned for D2.2.6)Randomization of traps

2010.03 Ongoing work for NVM (Micron, planned for D2.2.6)

Single dopands 2010.12 Ongoing work for NVM (Micron, planned for D2.2.6)Deterministic fluctuations

2010.12 Planned to be applied in the last year of the project

Hybrid method F-2011.09 Planned to be applied to NVM (Micron), FinFET (NXP), and 32nm bulk (ST Crolles) in the last quarter of 2011

Work function variability

G-2012.06 Planned to be applied to FinFET (NXP) and 32nm bulk (ST Crolles) in the last quarter of 2011

27© Synopsys 2011 27© Synopsys 2011

Plan for Deliverable D2.2.6

SNPS agreed to join D2.2.6.

We plan to apply some of the new methods implemented in Sdevice to the NVM structure.

In detail we are thinking about the following:

Investigation of influence of single traps and single dopands on IV characteristics and gate leakage (direct statistical method).

Applying IFM hybrid method to RDF.

IUNET contribution for D2.2.6

Alessandro Spinelli – UMET-MI in collab. with NMX

Susanna Reggiani – UNET-BO

Paolo Pavan, Luca Larcher – UNET-MORE

CONFIDENTIAL

Study of RDF and RTN dependence on device geometry

Different curvature radii of the active area of template MOSFETs were considered

RDF VT distribution slightly widens for larger radii

RTN VT slope improves as curvature radius is increased

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CONFIDENTIAL30

MODERN Progress report: IUNET-Bologna Industrial Partner: MICRON

D 2.2.6 – Proposed activity: Sensitivity analysis of Non Volatile Memory device performance as a function of random dopant fluctuations (RDF). Comparison of the RDF results carried out by using Sentaurus Device and (i) the Impedance Field Method (IFM), based on the Green’s function noise calculations, or (ii) a set of randomized doping configurations generated by using the “cloud-in-cell” method.

Status: on scheduleNext steps:i)Investigation of the Vth of a 32-nm Flash cell (template device)ii)Determination of the role played by the doping definition (see right figure).iii)Determination of the role played by short-channel effects (tox, LG, xj,Na).iv)Study of the role played by mobility by means of the IFM method.

CONFIDENTIAL

IUNET – MORE Contribution: Gate current simulations

nMOS - 1nm IL/3nm HfO2 gate stack pMOS - 1nm IL/5nm HfO2 gate stack

IG-VG simulation through a multi-phonon trap-assisted tunneling model

Investigation of IG temperature dependencies: carrier-limited (depletion/ /weak

inversion) and transport-limited (strong inversion) regimesIdentification of the atomic configuration of the defects assisting the electron (hole) conduction in nMOS (pMOS) devices

Progress IUNET-Udine• Task 2.2.6(b) – reference NMX: Quantization

– Extremely efficient Schroedinger poisson solver for rounded corner FinFET/wire structures

– More than 100x speed improvement

[Paussa et al., SISPAD 2010, pp.234, accepted TED]

Example of Schr.-Poi. solution for hexagonal wire

Luca Selmi - IUNET-Udine - MODERN Progress report Nov. 2010

Publications with MODERN ack.

Luca Selmi - IUNET-Udine - MODERN Progress report Nov. 2010

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UNGL: D2.2.6 Contributions

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UNGL D2.2.6 Plans

•Sensitivity analysis of Non-Volatile Memory performance as a function of individual trap position.

•Couple sensitivity of trap position to other variability sources.

•Outline of GSS approach to Toolbox methodologies.

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UNGL D2.2.6 Progress

NBTI/PBTI capabilities developed

and used in D2.4.3

NMOS

PMOS

Initial studies of charge trapping carried out in D2.2.3

Work in progress to look at effects of single charge trapping and sensitivity of other sources of variability to charge trapping.

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UNGL D2.2.6 Toolbox

GSS Mystic GSS RandomSpiceGSS GARAND

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STF2 Contibution to D.2.2.6• Using analytical MASTAR model, goal is to give a

first outlook on device structure impact on variability at the 16nm node. Bulk, FinFET and FDSOI will be studied interms of SNM variation and Vdd,min variation.

• Test case will be a 16nm 6T-SRAM Cell

• Variability will be implemented on the following device parameters : Doping, Lgate, Electrode workfunction, film thickness variation (for FD devices), and mobility

• Typical 3sigma variation inputs will be based on result obtained in MODERN of 45nm/28nm technology

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STF2 Contibution to D.2.2.6• Example of results (20nm node)