tallinn university of technology department of computer engineering estonia department of computer...

Tallinn University of TechnologyDepartment of Computer Engineering

Estonia

Department of computer Engineeringati.ttu.ee

CEBE SeminarDigitaalsüsteemide diagnostika

Jäneda mõis, Juuni 17, 2013

Raimund Ubar

CEBE Workshop, Jäneda, Juuni 17, 2013 © R.Ubar

CEBE teadustöö temaatikad

Süsteemide verifitseerimine ja diagnostika (R.Ubar)

Töökindlad sardsüsteemid (P.Ellervee)

Sensorsignaalitöötlus ja impedantsspektroskoopia (M.Min)

Pooljuhttehnoloogia (T.Rang)

Optilised diagnostikameetodid kardioloogias (K.Meigas)

Biovedelike optika (I.Fridolin)

Ajusignaalide interpreteerimine (H.Hinrikus)

CEBE koostöö

CEBE koostööruumi dimensioonid

P1

P2

P5

Koostöö otsingud

P7


Valitud tulemusi diagnostika valdkonnas 1. Kõrgtaseme otsustusdiagrammid (KTOD - HLDD)

2. Digitaalsüsteemide formaalne verifitseerimine ja disainivigade automaatne parandamine digitaalsüsteemide kanooniline mudel – HLDD esitus

karakteristlike polünoomidena mudeli ja meetodite eelisteks on parem skaleeruvus tänu

ülesande originaalsele tükeldamisviisile

3. Digitaalsüsteemide diagnostika rikete simulaator (kiirem kommertssimulaatoritest) testide generaatorid rikete diagnostika uudne kontseptsioon:

• rikete testimise taandamine skeemi korrasoleku tõestamisele • vabanemine rikete mudelitest ja vastastikkusest maskeerimisest


4

entity rd_pc is port ( clk, rst : in bit; rb0 : in bit; enable : in bit; reg_cp : out bit ; reg : out bit ; outreg : out bit ; fin : out bit ) ; end rd_pc ; architecture archi_rd_pc of rd_pc is type STATETYPE is (state1, state2); signal state, nstate: STATETYPE ; signal enable_in : bit ; signal reg_cp_comb : bit ; begin seq: process(clk, rst) begin if rst='1' then state <= state1 ; elsif (clk'event and clk='1') then state <= nstate ; end if ; end process ; process(clk, enable) begin if clk='1' then enable_in <= enable ; end if ; end process ;

VHDL description of 4 processes for a simple Control Unit

process(clk, reg_cp_comb) begin if clk='0' then reg_cp <= reg_cp_comb ; end if ; end process ; comb: process (state, rb0, enable_in) begin case state is when state1 => outreg <= '0' ; fin <= '0' ; if (enable_in='0') then nstate <= state1 ; reg <= '1' ; reg_cp_comb <= '0' ; else nstate <= state2 ; reg <= '1' ; reg_cp_comb <= '1' ; end if ; when state2 => if (rb0='1') then nstate <= state2 ; reg <= '0' ; reg_cp_comb <= '1'; outreg <= '0'; fin <= '0'; elsif (enable_in='0') then nstate <= state1 ; reg <= '0' ; reg_cp_comb <= '0'; outreg <= '1'; fin <= '1'; else nstate <= state2 ; reg <= '0' ; reg_cp_comb <= '0'; outreg <= '0'; fin <= '1'; end if ; end case ; end process ; end archi_rd_pc ;

1. Kõrgtaseme otsustusdiagrammid


5

DDs for state, enable_in and nstateentity rd_pc is port ( clk, rst : in bit; rb0 : in bit; enable : in bit; reg_cp : out bit ; reg : out bit ; outreg : out bit ; fin : out bit ) ; end rd_pc ; architecture archi_rd_pc of rd_pc is type STATETYPE is (state1, state2); signal state, nstate: STATETYPE ; signal enable_in : bit ; signal reg_cp_comb : bit ; begin seq: process(clk, rst) begin if rst='1' then state <= state1 ; elsif (clk'event and clk='1') then state <= nstate ; end if ; end process ; process(clk, enable) begin if clk='1' then enable_in <= enable ; end if ; end process ;

nstate

rst

clk

#1

state’

state1

0

0

1

state’

rb0

enable_in

#2

#11

1

120

0nstate

Superposition of DDs

clk

enable’

enable1enable_in

0

1. Kõrgtaseme otsustusdiagrammid - süntees


6

1. Kõrgtaseme otsustusdiagrammid - süntees process(clk, reg_cp_comb) begin if clk='0' then reg_cp <= reg_cp_comb ; end if ; end process ; comb: process (state, rb0, enable_in) begin case state is when state1 => outreg <= '0' ; fin <= '0' ; if (enable_in='0') then nstate <= state1 ; reg <= '1' ; reg_cp_comb <= '0' ; else nstate <= state2 ; reg <= '1' ; reg_cp_comb <= '1' ; end if ; when state2 => if (rb0='1') then nstate <= state2 ; reg <= '0' ; reg_cp_comb <= '1'; outreg <= '0'; fin <= '0'; elsif (enable_in='0') then nstate <= state1 ; reg <= '0' ; reg_cp_comb <= '0'; outreg <= '1'; fin <= '1'; else nstate <= state2 ; reg <= '0' ; reg_cp_comb <= '0'; outreg <= '0'; fin <= '1'; end if ; end case ; end process ; end archi_rd_pc ;

rst #1state 1

0

state’

rb0

enable'

#2

#11

1

120

0

enable

#0011

#0001

1

0

enable

#0100

#1100

1

0

state

rb0

1

2

0

#0010

1

outregfinreg_cpreg

HLDD model for the Control Unit


Each node in SSBDD represents a signal path:

y4

y3 y1 R1 + R2

IN + R2

R1* R2

IN* R2

y2

R2 0

1

2 0

1

0

1

0

1

0

R2

IN

R12

3The faults at y3 in HLDD represent the faults in the control circuitry and in the multiplexer M3 in the RTL circuit

The faults at R1*R2 in HLDD represent the faults in multiplier, input and output buses, and in the registers

1. Kõrgtaseme otsustusdiagrammid - näide

R2M3

e+M1

a

*M2

b

R1

IN

c

d

y1 y2 y3 y4

Control path

Data path


8

2. Digitaalsüsteemide verifitseerimine

System specification

System buggy RTL implementation

New variables appeared: reg t and state The order of checking predicate values is also changedA copy-paste error: condition c_c should hold when we are adding in c, not the negation of c_c

Bug


9

Novelty: Boolean methods can be generalized in a straightforward way to higher functional levels

Specification Implementation

Each graph has a unique polynomial

2. Digitaalsüsteemide verifitseerimine

Canonical Form of HLDDs


10

For every node w in HLDD define a subgraph Gw of G with root node w and all descendant nodes (with polynomial P(w,vT))

For every pair of nodes v, w we define a subgraph Gv,w with root

node v and a single terminal node w (with polynomial p(v,w))

Correction procedure:

v0 v w vT

w'

P(v0,v) p(v,w)P(w,vT)

P(w’,vT)

P(v0, vT) = P(v0,v) p(v,w) [ P(w’,vT ) - P(w,vT) ]

Root node

Terminal node with faulty

P(v0,vT)

Modification of the HLDD

2. Disainivigade parandamine


11

2. Keerukusega võitlemisest - skaleeruvus

A=FA1 (...)

B=FB1 (...)

C=FC1 (...)

A=FA2 (B,C,...)

A=FAn (D,E,...)

State space

Program data flow

Behavior of A

DE

B

C

High-Level Decision Diagrams

Novelty: Instead of reasoning the design as a whole, it will be partitioned into the behavioral sub-models of functional variables (HLDDs)


3. Testide genereerimine registertasandil

R2M 3

e+M 1

a

*M 2

b

R1

IN

c

d

y1 y2 y3 y4

y4

y3 y1 R1 + R2

IN + R2

R1* R2

IN* R2

y2

R2 0

1

2 0

1

0

1

0

1

0

R2

IN

R12

3

Single path activation in a single DDData function R1* R2 is tested

Data path

Decision Diagram

High-level test generation with DDs: Scanning test

Test program:

Control path

Control: y1 y2 y3 y4 = 0032

Data: For all specified contents of (R1, R2)


Instruction set:

I1: MVI A,M A IN

I2: MOV R,A R A

I3: MOV M,R OUT R

I4: MOV M,A OUT A

I5: MOV R,M R IN

I6: ADD R A A + R

I7: ORA R A A R

I8: ANA R A A R

I9: SUB R R R - 1

I10: MOV C,R C R

I11: CMA R,C R C

I12: JMP PC, C IF C=0 THEN

PC = IN

13

I R3

A

OUT4

HLDD-model of a microprocessor:I IN

1A

A

A + R6

A R7

A R8

I A2

R

IN5

R

R - 19

C11

I C12

PC

PC + 1

IN0

I R10

C

C

3. Testide genereerimine – mikroprotsessor


14

I R3

OUT4

I A2

R5

R

R - 19

C11

I C12

PC

PC + 1

IN0

I R3

C

C

I IN1

A

A

A + R6

A R7

A R8

IN

A

Scanning test program:

For j=1,nBeginI5: Load R = IN(j1)I1: Load A = IN(j2)I7: ADD A = A + RI4: Read A End

IN(j1) IN(j2)A

Test data Signature

3. Testide genereerimine – mikroprotsessor


15

1

1

1

1

&

1

x111x1

x2

x3

x4x5

x6

&

&

&

&

&

&

x7

x8

x9

x610

x221

x420

tTest patterns Tt Test

faultsMask faultsx1 x2 x3 x4 x5 x6 x7 x8 x9

1 0 0 - 1 1 1 0 1 0 x11 1 x61 02 1 0 - 1 1 1 0 0 1 x61 0 x22 13 0 0 1 1 0 1 1 - 1 x22 1 x42 04 0 1 0 1 1 1 1 - 1 x42 0 x11 15 1 0 - 1 1 0 0 1 0 x22 1

T2

x11 1

x42 0 x22 1

x61 0

T4

T1

T3

T5

x22 1 can be detected by T5

How to find this pattern?

Ring masking

Rikete maskeerumise näide

3. Diagnostika üldjuht


16

y

1

1

1

1

&

1

x111x1x2x3

x4x5x6

&

&

&

&

&

&

x7

x8

x9

x610

x221

x420

x11 x21y

x41 x5

x12

x9

x61

x42x22

x3

x7

x62

x8

x7

1

0

Kahekordne topoloogia rikete maskeeruvuse

analüüsiks

4 SAF (x11 1, x22 1, x42 0, x61 0) are masking each other

10

111/00

0

1

1/0

0/1



17

y

1

1

1

1

&

1

x111x1x2x3

x4x5x6

&

&

&

&

&

&

x7

x8

x9

x610

x221

x420

x11 x21y

x41 x5

x12

x9

x61

x42x22

x3

x7

x62

x8

x7

1

0

10

111/00

0

1x1 x2 x3 x4 x5 x6 x7 x8 x9 Y

1 0 0 1 1 1 0 0 1 1/1

1 0 0 1 1 0 0 0 1 0/0

1 0 0 1 0 1 0 0 1 0/1


Test gruppide meetod


18

CEBE kaks tüüpi sünergiat

Välja-poole

suunatud

Arvuti-tehnika

Elektroonika

Tehnomeedikum

Sisse-poole

suunatud

Rakendused

Meetodite ja algoritmide

konversioon


CEBE teadustöö temaatikad

Süsteemide verifitseerimine test ja diagnostika (R.Ubar)

Töökindlad sardsüsteemid (P.Ellervee)

Sensorsignaalitöötlus ja impedantsspektroskoopia (M.Min)

Pooljuhttehnoloogia (T.Rang)

Optilised diagnostikameetodid kardioloogias (K.Meigas)

Biovedelike optika (I.Fridolin)

Ajusignaalide interpreteerimine (H.Hinrikus)

CEBE koostöö

Sünergiaotsingute tulemus

P1

P2

P5

Koostöö otsingud

P7


a...

.

. b...

.

.

bk...

.

.

be...

.

.

bs...

.

.

c...

.

. d...

.

. de...

.

.

Shared preprocessorand integrator

Common buffersfor all channels

Shared prepocessorand shared integrator


Shared preprocessor

Sharedpreprocessor

Shared adder/subtractorin the preprocessor

Initial design


and shared integrator

Added buffersfor every samplefor every channel

Protsessorite perekond

Koostöö projekti P1 tulemus


Tulemused:Rikete simulaator: Uus meetod rikete simuleerimiseks, kus on loodud uus matemaatika

nii testvektorite kui ka rikete analüüsiks süsteemide diagnostilisel modelleerimisel

Algoritm on suurusjärgu võrra kiirem kui professionaalsed disaini tarkvaratööriistad

Doktoritööd: Maksim Jenihhin. Test Time Minimization for Parellel Hybrid BIST

Architectures (2008). Supervisors: R.Ubar, J.Raik. Sergei Devadze. Fault Simulation of Digital Systems (2009).

Supervisors: R.Ubar, P.Ellervee. Vineeth Govind. DfT-based External Test and Diagnosis of Mesh-like

Networks on Chips (2009). Supervisor: J.Raik.

21

P2: Verifitseerimine ja diagnostika


Defekt0101

DOT – Hierarhiline testide generaator

Võimaldas esmakordselttõestada defektide liiasust

(mitteolulisust)

Konstantrike

P2: Uued defektide analüüsi meetodid

22

Määramatu (Byzantine’i) rike, X-rikke mudel

Tingimuslik konstant

Synopsys

X-rikke simulaator

Konstantrikke simulaator,DOT – defektide simulaator

Simuleerimise aeg

Eri katseskeemid


23

CEBE sünergiast

Professionaalne analoog

TTÜ simulaator

Signaaliprotsessorite arhitektuuride simuleerimine

Simuleerimise aeg

Objektide pere

Miks on ühe objekti puhul

simulaator aeglasem?


a...

.

. b...

.

.

bk...

.

.

be...

.

.

bs...

.

.

c...

.

. d...

.

. de...

.

.

Shared preprocessorand integrator


Shared prepocessorand shared integrator


Shared preprocessor

Sharedpreprocessor


Initial design


and shared integrator

Added buffersfor every samplefor every channel


ROx xRIy

ySSBDDT)(

Testitavuse marker:


25

Professionaalne analoog

TTÜ simulaator

Topoloogia omadus

CEBE sünergiast

Võimaluse korrelatsiooniomaduse

avastamiseks andis koostööprotsessorite pere loomisel

Simuleerimise aeg

Objektide pere

ROx xRIy

ySSBDDT)(


Deterministic test generation time

Fault simulation time

Random test generation time

Test length


Protsessorite testitavus

ROx xRIy

ySSBDDT)(


27

Süsteemide diagnostika

Süsteemi spetsifikatsioon

Matemaatiline mudel

Re-Disain

Testide süntees

Testimine

Disainivigade diagnoos

Verifitseerimine

Rikete diagnoos

Koodi katte analüüs

Rikete analüüs

Disainigrupp

Elektroonikagrupp


Tervishoid ruudus - Health2

28

Meditsiini-tehniline seade

Doktor

Tehnoloogia

Patsient

Testide süntees,

verifitseerimine

Diagnoos, rikete

parandamine

Süsteemi tervis

Patsiendi tervis

Meditsiini alane teave


29

Evolutionary Health Risk Prevention Tool

Sensors, equipments

Health diagnosis

toolDoctors

Synergy: Evolutionary Risk Prevention Tool

Risk factors

Risks

Biosignals Healthcare plan


Health2: Development Objectives

30

Health diagnosis

tool

Data, risk factor

values

Network ofsensors,

equipments

Patients

Doctor

Risks, risk factors

Research

Risk parameter selection

Medical knowledge

Medical part

Self repair

System and network design

Design and test platform

andtools

Engineering knowledge

Methods, models, and algorithms

Engineering part


Bioimpedancespectrography& tomography

Brain research, EEG spectral

analysis, SASI marker

Optical dialysis monitoring

Optical pulse wave measurement

in arteries

Research in biomedical engineering

Signal processing algorithms

Design for low power, speed, cost, reliability

System design

Design of dedicated processors

Verification, design error automated

diagnosis and repair

Design for dependability

Automated testing and fault diagnosis

CEBE R&D Fields for Health2

Pacemakers

Mobile SASI analyser

Equipments foroptical signal measurement

Medical equipment

Applications

Information for doctors


32

Bioengineering applications health monitoring systems, body area sensor networks, implantable cardiac

pacemakers

Mission critical embedded systems

Data acquisitionbioimpedance,

biosignals,biooptical methods

Signal processing

theory, methods, algorithms,

non-classical DASP techniques

Technologymicro, nano,

MEMSSemiconductor

research

Digital design

verification, simulation

Defect analysis

Human being

Biosignal interpretation

Bioengineering research

brain processes,atherosclerosis,

predicting sudden cardiac death,

monitoring clinical treatments

Laboratories-on-chipimpedance spectroscopy in scientific

experiments, bio-MEMS products, bioprocessors-on-chip

Industrial applicationsfood processing, medical instrumentation, energy

conversion

Dedicated processor

architectures, SOC, NOC

Analog, mixed signal

designApplications:

CAD tools

Test research,

fault diagnosis,

dependability

Sensorics, sensor networks

Cooperation in CEBE

BME

EMBEL

RES


33

Health DiagnosisTool

Health Diagosis Tool

Rj = Dj (F11,..., Fhm)

F11 ... F1m Risk factors(parameters)

RisksR1

R2

Rn

Diagnosed risk pattern

Medical knowledge

development subtasks

F21 ... F2m Fh1 ... Fhm

Ri

Rj

Rk

Biofactors Genetic factors Life style factors

Sensor network

Otherfactors


34

RM4Health2: Tasks and Subtasks


P1 P2 P3 P4 ... Risk factors

(Parameters)

P1 – Blood pressure (Kalju, Mart)P2 – Nefrology (Ivo)P3 – Neurology (SASI – Hiie)P4 – Bioimpedance (Mart)

Risks

R1

R2

R3

Diagnosed risk

Engineering development subtasksMedical

knowledge development

subtasks

T1 – HL Synthesis (Peeter)T2 – Design (ZamiaCAD/Maksim)T3 – Verification (Jaan)T4 – Debug (Jaan)T5 – Test gener (DECIDER/Jaan)T6 – Fault simulation (Raimund)T7 – Fault diagnosis (Raimund)T8 – BIST/BISD (Raimund)T9 – Test instruments (Artur)

Tools and platform development subtasks

Theory, models, algorithms, methods, tools > Novelty


35

Health DiagnosisTool


Rj = Dj (F11,..., Fhm)

F11 ... F1m Risk factors(parameters)

RisksR1

R2

Rn

Diagnosed risk pattern

Medical knowledge

development subtasks

F21 ... F2m Fh1 ... Fhm

Ri

Rj

Rk

Biofactors Genetic factors Life style factors

Sensor network

Otherfactors


DUT1 DUT2 DUTn---

MUX

MUX

SA

RAM

MP

Off-line Watch-Dog

DUT1 DUT2 DUTn

Functional modelfor signature calculation

DUT1 DUT2 DUTn

Structural modelfor fault simulation

Fault simulator

At-speed on-line testvectors

Monitoring checkpoints

Self-testing system

Signature analyzer

Microprocessor computes off-line the signatures and compares with the

real one

Go/NoGo

Fault coverage

Cloud

Watch-Dog is connected to different parts of the system for

(1) on-line testing, (2) off-line test results analysis

(3) test quality evaluation in backgound

DUT1

DUT2

DUTn

VHDL Design with watchdog

On-line testing

tallinn university of technology department of computer engineering estonia department of computer...

Documents