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The top documents tagged [clock gating]
Analytical Thermal Placement for VLSI Lifetime Improvement and Minimum Performance Variation Andrew B. Kahng †, Sung-Mo Kang ‡, Wei Li ‡, Bao Liu † † UC
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Xiaocheng Zhou Intel Labs China “Single-chip Cloud Computer” An experimental many-core processor from Intel Labs
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Formal Engineering Research with Models Abstractions and Transformations FERMAT Low Power Hardware Synthesis from Concurrent Action Oriented Specifications
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“Single-chip Cloud Computer” An experimental many-core processor from Intel Labs
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Opeoluwa (Luwa) Matthews, Meng Zhang, and Daniel J. Sorin
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Register and Counter Design
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GPU Power Model Nandhini Sudarsanan
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@umn.edu Nathan Vanderby
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Neeraj Mishra
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Usha Vinodh
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1 COMP541 Sequential Circuits Montek Singh Feb 1, 2007
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Reduction of Power Consumption in FPGAs
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Sabyasachi Ghosh Mark Redekopp Murali Annavaram Ming-Hsieh Department of EE USC
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Registers & Register Transfers Digital Logic Design Instructor: Kasım Sinan YILDIRIM
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1 Lecture 21: Core Design, Parallel Algorithms Today: ARM Cortex A-15, power, sort and matrix algorithms
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