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  • 8/10/2019 SystemC Data Types 2pages

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    KTH IL2452 System Design

    Languages Lecture 5 1

    Dr. Zhonghai Lu ()

    School for ICT

    KTH Royal Institute of Technology

    2

    C++ Basics SystemC

    Introduction

    and Get

    Started

    Concurrency

    and Time

    SystemC

    Data Types

    andDebugging

    Modules

    and

    Processes

    Channels

    and

    Interfaces

    Transaction

    Level

    Modeling

    SystemC

    Summary

    IL2452 System Design Languages

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    3IL2452 System Design Languages

    Aim

    Understand SystemC data types and master how

    to use them

    Content

    Overview of SystemC data types

    Integer and vector types

    Type conversion

    Resolved signals (bus resolution)

    4IL2452 System Design Languages

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    SystemC supports

    Native C/C++ Types

    SystemC Types: Data types oriented for hardware

    modeling

    SystemC Types

    2 value (0,1) logic/logic vector

    4 value (0,1,Z,X) logic/logic vector

    Arbitrary sized integer (Signed/Unsigned) Fixed Point types (Templated/Untemplated)

    Using namespace sc_dt

    5IL2452 System Design Languages

    Type Description

    Integer types

    sc_int Signed Integer from 1-64 bits: sc_int

    sc_uint Unsigned Integer from 1-64 bits

    sc_bigint Arbitrary size signed integer: sc_bigint

    sc_biguint Arbitrary size unsigned integer

    Logic and Vector types

    sc_logic Simple bit with 4 values(0/1/X/Z)

    sc_bv Arbitrary size 2-values vector: sc_bv

    sc_lv Arbitrary size 4-values vector

    Fixed point types

    sc_fixed templated signed fixed point

    sc_ufixed templated unsigned fixed point

    sc_fix untemplated signed fixed point

    sc_ufix untemplated unsigned fixed point

    6IL2452 System Design Languages

    sc_fix is the base class for sc_fixed. The size of an object of type

    sc_fix is set when the object is created (i.e. by the constructor)

    as opposed to sc_fixed where the size is set by the compiler

    (using the template parameter).

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    Four integer types: signed, unsigned, limited

    width and big width.

    sc_int, sc_uint

    n 64

    Regardless of the bit width n given by the template

    parameter, internally stored with 64 bits of precision

    sc_bigint, sc_biguint

    No max. for n (unbounded)

    Internally stored with as many as necessary to hold theresult

    All integers are stored as binary numbers. Signed

    numbers are stored in twos complement format.

    sc_int, sc_lv, sc_bv7IL2452 System Design Languages

    Operators Overloaded operators: bitwise, arithmetic, assignment,

    equality, relationship

    Bitwise operators (&(and), |(or), ^(xor), ~(not), )

    Arithmetic operators ( +, -, *, /, %(modulo) )

    Assignment (=) and compound assignment (+=, -=, *=, /=, %=,>>=,

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    Assignment to any of the integer types causes

    the value to be truncated to the given number of

    bits without warning.

    Precision of intermediate results determinedonly by the operands.

    sc_uint a, b, c;

    sc_uint d;

    a = b = 15;

    c = a + b;

    d = a + b;

    c=14

    d=30

    sc_uint j = 0x7fff ffff ffff ffff;

    sc_biguint k;k = j * j;

    k = sc_biguint (j) * j;

    Truncated to 64 bits.

    stored with arbitrary precision9IL2452 System Design Languages

    sc_uint sc_int sc_int

    Truncation!

    problematic

    Due to implicit type conversion,

    it allows to mix the SystemC integer types sc_int

    and sc_uint with C++ fundamental types int.

    Any two SystemC types can be converted by

    assignment operator =, which is overloaded. Signed/unsigned conversion loses sign without

    warning.

    sc_int a, b;

    int d;

    d = a & b;

    a = b + d;

    sc_int a;

    sc_bigint B;

    B = a;

    a = B;

    sc_int s;

    sc_uint u;

    s = -1;

    u = s;

    s = u;

    u = 255

    s = -1

    10IL2452 System Design Languages

    Give an example of implicit

    type conversion, which auser expects to occur?

    Cannot add an sc_int to

    an sc_logic.

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    sc_logic is a 4-valued data type, similar to

    VHDL type std_logic 4 values: 0, 1, X, Z

    Initial value is X

    Slower than bool

    Vectors

    sc_lv arbitrary length vector of sc_logic

    sc_bv arbitrary length vector of bool Used for vectors longer than 64 bits where no need

    arithmetic operators (shift is Ok).

    Faster than sc_biguint

    For vectors of 64 bits or less, sc_uint is faster and

    more convenient.

    Bitwise & | ^ ~

    As sign ment = &= != ^=

    Equality == !=

    sc_logic a, b;

    a = 1;

    b = Z;

    b = a & b;

    11IL2452 System Design Languages

    Similar to std_logic in VHDL.

    Concatenation means composing two or more vectors end-

    to-end to create a single longer vector.

    Two ways of concatenation

    Overloaded comma operator

    Function concat()

    A concatenation can be used as an l-value, i.e., on the left

    hand side of an assignment.

    sc_uint a, b, d, e;

    sc_unit c;

    c = (a, b);

    (d, e) = c;

    11011100

    11001101

    a b

    c

    (a, b, c) = (c, b, a); concat(a, concat(b,c)) = concat(concat(c,b), a);12IL2452 System Design Languages

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    To support bit select, the index operator [] is overloaded.

    To support part select, use the method range() for sc_int,

    sc_uint, sc_lv, sc_bv with 2 arguments.

    For sc_int, sc_uint, the 1st argument the 2nd argument.

    For sc_lv, sc_bv, if the first argument is less than the second, the

    bits are read out of the vector in the reverse order.

    Range() can be abbreviated by calling the overloaded operator()(int, int).

    sc_int a;

    bool b;

    b = a[7]

    a[6] = b;

    a.range(7,4) = a.range(3,0);

    sc_lv v = ZX10;cout

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    Two SystemC data types can be

    converted by assignment

    (implicit type conversion). Thisdoes not hold for converting to

    C++ types.

    To convert from sc_bv,

    sc_lv to int, need explicit

    type conversion to_int().

    Function to_string() convert to

    a formatted text string.

    The 1st argument gives therepresentation

    The 2nd argument indicates

    whether to include a prefix

    showing the number base.

    sc_lv lv = 0xff;

    sc_bv bv = 0xff;sc_bigint si = 0xff;

    int i;

    i = lv.to_int( ); // return -1

    i = bv.to_uint( ); //return 255

    i = bi.to_long(); //return 255

    cout

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    Due to their compile-time overhead, fixed-

    point types are omitted from the default

    SystemC include file.

    To enable fixed-point types, SC_INCLUDE_FX

    must be defined prior to including the

    SystemC header file.

    IL2452 System Design Languages 17

    #define SC_INCLUDE_FX

    #include systemc.h

    sc_fixed

    }

    Word length

    Integer word length

    value in [- 4, 3.75], precision 0.25

    sc_fix var_1( 16, 4, SC_RND, SC_SAT);

    sc_fix var_2( 16, 4, SC_RND, SC_SAT);

    sc_fix var_3( 16, 4, SC_RND, SC_SAT);

    var_1 = 0.5;

    var_2 = 1.125;

    var_3 = 0.7;

    To model bus contention

    (multiple drivers on a tri-

    state bus wire), use a

    different data type

    sc_signal_resolved (not

    sc_signal). When multiple processes

    write to an instance of the

    sc_signal_resolved, the

    values are resolved

    according to a resolution

    table.

    SC_CTOR(Driver){

    SC_THREAD(p1);

    SC_THREAD(p2);

    }

    sc_signal_resolved s;

    void p1( ){

    s.write(sc_logic(0));}

    void p2( ){

    s.write(SC_LOGIC_1);

    wait(10, SC_NS);

    s.write(SC_LOGIC_Z);}

    }

    Resolved 0 1 X Z

    0 0 X X 0

    1 X 1 X 1

    X X X X X

    Z 0 1 X Z

    18IL2452 System Design Languages

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    sc_signal_resolved is a specialized channel of

    sc_signal for type sc_logic

    sc_signal_rv is a vector version of this

    channel.

    There are specialized ports, but they can

    only be bound to resolved signals.

    templateclass sc_signal_rv : public sc_signal< sc_lv > { }

    class sc_signal_resolved : public sc_signal { }

    sc_in< >

    sc_inout< >sc_out< >

    sc_in_resolved

    sc_inout_resolvedsc_out_resolved

    sc_in_rv< >

    sc_inout_rv< >sc_out_rv< >

    19IL2452 System Design Languages

    What if a user-defined data type passed over

    using sc_signal?

    Must define a default constructor

    Must overload operators =, ==,

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    Overview of SystemC data types: integer, vector, fixed

    point types

    Integer types

    Note their differences with int

    sc_int, sc_lv, sc_bv

    Type conversion

    Implicit conversion

    Use explicit type cast Resolved signals (bus resolution)

    sc_signal_resolved and sc_signal_rv

    Need specialized ports to connect to resolved channels

    User defined type passed over sc_signal21IL2452 System Design Languages

    Try the type conversion, assignment and

    truncation, bit/part select examples.

    Try the signal resolution example.

    22IL2452 System Design Languages

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    www.systemc.org

    www.doulos.com

    SystemC: From the Ground Up by D. C. Black,

    J. Donovan, B. Bunton, and A. Keist.

    System Design with SystemC by T. Grtker, S.

    Liao, G. Martin, and S. Swan

    Others

    23IL2452 System Design Languages