synthesis and verification of digital systems - … 667 - synthesis & verification 1 ece 667...

ECE 667 - Synthesis & Verification

1

ECE 667

Synthesis and Verification

of Digital Systems

Retiming


2

Retiming

Outline:

• Problem

– sequential synthesis

• Formulation

• Retiming algorithm


3

Optimizing Sequential Circuits by

Retiming Gate-level Netlist

Netlist of gates and registers:

Various Goals:

– Reduce clock cycle time

– Reduce area

• Reduce number of latches (registers)

Inputs

Outputs


4

Retiming Problem

– Pure combinational optimization can be myopic

since relations across register boundaries are

disregarded

Solutions

– Retiming: Move register(s) so that

• clock cycle decreases, or number of registers decreases

and

• input-output behavior is preserved

– Peripheral retiming: Combine retiming with

combinational optimization techniques

• move latches out of the way temporarily

• optimize larger blocks of combinational logic


5

Circuit Representation

[Leiserson, Rose and Saxe (1983)]

Circuit representation: G(V,E,d,w)

– V set of gates

– E set of wires

– d(v) = delay of gate/vertex v, (d(v)0)

– w(e) = number of registers on edge e, (w(e)0)


6

Circuit Representation

Example: Correlator

Circuit

(x, y) = 1 if x=y 0 otherwise

Operation delay

3

+ 7 Every cycle in the graph has at least one register,

i.e., there are no combinational loops.

0

3 3

0

0 0

0 2

Graph (Directed)

7

a b

+

Host


7

Preliminaries

For a path p :

Clock cycle c:

1

0

0

)()(

)()(

k

i

i

k

i

i

ewpw

vdpd endpoints) (includes

: ( ) 0max { ( )}

p w pc d p

For the correlator circuit: c = 13

Can we reduce it to 7 ? How ?

Path with

w(p)=0 0

3 3

0

0 0

0 2

7

0 11

0 1 1

ke ee

k kv v v v


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• Movement of registers

– from input to output of a gate or vice versa

• Does not affect gate functionalities

• A mathematical definition: retardation

– r: V Z, an integer vertex labeling

– wr(e) = w(e) + r(v) - r(u) for edge e = (u,v)

Basic Operation

Retime by 1

Retime by -1


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In the example, r(u) = -1, r(v) = -1 results in

• For a path p: s t, wr(p) = w(p) + r(t) - r(s)

• Retardation

– r : VZ, an integer vertex labeling

– wr(e) = w(e) + r(v) - r(u) for edge e = (u,v)

– A retiming r is legal if wr(e) 0, eE (prove it !)

Basic Operation

v u 0

3 3

0

0 0

0 2

7

0

v u 0

3 3

0

1 1

1

7


10

Retiming for Minimum Clock Cycle

Problem Statement: (minimum cycle time)

Given G (V, E, d, w), find a legal retiming r so that

is minimized

Retiming: 2 important matrices

• Register weight matrix

• Delay matrix

: ( ) 0max { ( )}

rp w pc d p

( , ) min{ ( ) : }p

pW u v w p u v

( , ) max{ ( ) : , ( ) ( , )}p

pD u v d p u v w p w u v


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Retiming for Minimum Clock Cycle

W V0 V1 V2 V3

V0 V1 V2 V3

0 2 2 2 0 0 0 0 0 2 0 0

0 2 2 0

c p, if d(p) then w(p) 1

D V0 V1 V2 V3

V0 V1 V2 V3

0 3 6 13 13 3 6 13 10 13 3 10 7 10 13 7

W = register path weight matrix ( minimum # latches on all paths between u and v ) D = path delay matrix ( maximum delay on all paths between u and v with min number of latches)

v2 v1

v0 0

3 3

0

0 0

0 2

7 v3

Delays exceeding 7 shown in red


12

Conditions for Legal Retiming

Assume that we are asked to check if a retiming exists for a clock cycle

Legal retiming: wr(e) 0 for all e. Hence

wr(e) = w(e) + r(v) - r(u) 0 or

r (u) - r (v) w (e)

For all paths p: u v such that d(p) , we require wr(p) 1

– Thus 1

0

1

1

0

0

1 ( ) ( )

[ (

( ) ( ) (

) ( ) ( )]

( ) ( )

)

( )

k

r r i

i

k

i i i

i

k

w p w e

w e r v

w p r

r v

w p r v v

r u

r

v

Or take the least w(p) (tightest constraint) r(u)-r(v) W(u,v)-1

Note: this is independent of the path from u to v, so we just need to apply it to

u, v such that D(u,v)


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• All constraints in difference-of-2-variable form

• Related to longest/shortest path problem

Solving the Constraints

Correlator: = 7

Legal: r(u)-r(v)w(e)

0)()(

0)()(

0)()(

0)()(

2)()(

03

32

31

21

10

vrvr

vrvr

vrvr

vrvr

vrvr

1)()(

1)()(

1)()(

1)()(

1)()(

1)()(

1)()(

1)()(

23

13

32

12

02

31

01

30

vrvr

vrvr

vrvr

vrvr

vrvr

vrvr

vrvr

vrvr

Timing D>7: r(u)-r(v)W(u,v)-1

W V0 V1 V2 V3

V0 V1 V2 V3

0 2 2 2 0 0 0 0 0 2 0 0 0 2 2 0

V2 v1

v0 0

3 3

0

0 0

0 2

7 v3

D V0 V1 V2 V3

V0 V1 V2 V3

0 3 6 13 13 3 6 13 10 13 3 10 7 10 13 7


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• Do shortest path on constraint graph: (O(|V|3 )).

• A solution exists if and only if there exists no negative weighted cycle.

Solving the Constraints

Legal: r(u)-r(v)w(e)

0)()(

0)()(

0)()(

0)()(

2)()(

03

32

31

21

10

vrvr

vrvr

vrvr

vrvr

vrvr

1)()(

1)()(

1)()(

1)()(

1)()(

1)()(

1)()(

1)()(

23

13

32

12

02

31

01

30

vrvr

vrvr

vrvr

vrvr

vrvr

vrvr

vrvr

vrvr

Timing D>7: r(u)-r(v)W(u,v)-1

A solution: r(v0) = r(v3) = 0, r(v1) = r(v2) = -1

r(1) r(0)

r(3) r(2)

0

1 1

1

1

1

-1

-1

-1

0,-1

0,-1

0

0 -1

2

Constraint graph


15

Retiming To find the minimum cycle time, do a binary search among the entries of the D matrix (0(V3 logV))

Retime

Retimed correlator:

v0

V2 v1

0

3 3

0

0 0

0 2

7

Clock cycle = 3+3+7=13

a b

+

Host

Clock cycle = 7

a b

+

Host

W V0 V1 V2 V3

V0 V1 V2 V3

0 2 2 2 0 0 0 0 0 2 0 0 0 2 2 0

D V0 V1 V2 V3

V0 V1 V2 V3

0 3 6 13 13 3 6 13 10 13 3 10 7 10 13 7


16

1. Relaxation based:

– Repeatedly find critical path;

– retime vertex at end of path by +1 (O(VElogV))

2. Also, Mixed Integer Linear Program formulation

Retiming: two more Algorithms

+1

u Critical path

v


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Relaxation Algorithm - Rationale


18

Relaxation Algorithm


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Relaxation Algorithm – step 1

Retime for = 13


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Retime for = 13


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Retimed for = 13


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Relaxation Algorithm – summary

(Retiming for = 13)


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Retiming for Minimum Area (Minimum # Latches)

Goal: minimize the number of registers used

:

:

min ( )

( ( ) ( ) ( ))

( ) ( ( ) ( ))

( ( ) ( ))

( )(# ( ) # ( )

( )

r r

e E

e u v

e E e u v

u v

v V

V

v V

N w e

w e r v r u

w e r v r u

N r v r u

N r v fanin v fanout v

N a r v

where av is a constant for each node v.


24

Minimize:

Minimum Registers - Formulation

( )v

v V

a r v

Subject to: wr(e) = w(e) + r(v) - r(u) 0

• Reducible to a flow problem

synthesis and verification of digital systems - … 667 - synthesis & verification 1 ece 667...

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