switched cap circuits ii
TRANSCRIPT
-
7/29/2019 Switched Cap Circuits II
1/23
Switched Capacitor Circuits II
Dr. Paul Hasler
Georgia Institute of Technology
-
7/29/2019 Switched Cap Circuits II
2/23
Basic Switch-Cap Integrator
1
GND
V1[n]
Vout[n]
2
GND
C2
C1
Vout[n] = Vout[n-1] - (C1/C2) V1[n]
Vout(z)
1 - z-1V1(z)= H(z) = - (C1/C2)
1
H(j) = - (C1/C2)1 - e-jT
1
~ - (C1/C2) / jT
assumes T
-
7/29/2019 Switched Cap Circuits II
3/23
Switch-Cap Implementation
1
GND
V1[n]
Vout
[n]
2
GND
C2
C1
1
GND
V1[n]V
out[n]
2
GND
C2
C1
-
7/29/2019 Switched Cap Circuits II
4/23
Switch-Cap Implementation
1
GND
V1[n]
Vout[n]
2
GND
C2
C1
Transistor switches result in:
Parasitic capacitances Charge / clock feedthrough
-
7/29/2019 Switched Cap Circuits II
5/23
Switch-Cap Implementation
1
GND
V1[n]
Vout[n]
2
GND
C2
C1
1
GND
V1[n]V
out[n]
2
GND
C2
C1
GND
Cp1
GND
Cp2
GND
Cp3
GND
Cp4 Cp5
GND
GND
Cp0
Now adding Parasitic capacitors:
-
7/29/2019 Switched Cap Circuits II
6/23
Switch-Cap Implementation
1
GND
V1[n]
Vout[n]
2
GND
C2
C1
GND
Cp1
GND
Cp2
GND
Cp3
GND
Cp4 Cp5
GND
GND
Cp0
Fortunately, many of these capacitors have minimal effect on the circuit
Parasitic capacitances to a voltage source can be neglected
Parasitic capacitances to a virtual AC GND can be neglected
(the effect of the capacitance is divided by the open-loop gain)
-
7/29/2019 Switched Cap Circuits II
7/23
Switch-Cap Implementation
1
GND
V1[n]
Vout[n]
2
GND
C2
C1
GND
Cp1
GND
Cp2
We still have parasitic capacitances effecting our result
We can either make large to swamp out parasitic capacitors,
or use a stray insensitive design
-
7/29/2019 Switched Cap Circuits II
8/23
Switch-Cap Integrator
1
GND
V1[n]
V2[n]
1
2
Vout[n]
2
GND
C2
C1
We will step through all four phases, to get the proper result.
-
7/29/2019 Switched Cap Circuits II
9/23
Switch-Cap Integrator
GND
V1[n-1]
V2[n-1]
Vout[n-1]
GND
C2
C1
This case is important to understand our starting point
charge is stored on a capacitor ; therefore we need to know the initial state
(4), [n-1] cycle
Q = -C2Vout[n-1]
Voltage = 0V
(Voltage remains held)
-
7/29/2019 Switched Cap Circuits II
10/23
Switch-Cap Integrator
GND
V1[n]
V2[n]
Vout[n-1]
GND
C2
C1
Charge up the capacitor with voltage V1[n]
(1), [n] cycle: 1
Q = -C2Vout[n-1]
(Output unchanged)
V1[n]
-
7/29/2019 Switched Cap Circuits II
11/23
Switch-Cap Integrator
GND
V1[n]
V2[n]
Vout[n-1]
GND
C2
C1
We remove the capacitor from the first voltage.
The voltage is stored across the capacitor
(2), [n] cycle
Q = -C2Vout[n-1]
(Output unchanged)
V1[n]
Q1 = C1V1[n]
Q1
= -C1V
1[n]
-
7/29/2019 Switched Cap Circuits II
12/23
Switch-Cap Integrator
GND
V1[n]
V2[n]
Vout[n-1] +
(C1/C2) (V2[n]- V1[n])GND
C2
C1
We connect the capacitor to the charge summing node
The charge initially stored on the capacitor as well as the resulting
charge from the second input (V2 [n]) contributes to the total charge
(3), [n] cycle: 2
Q = -C2Vout[n-1]
+ C1V1[n]
- C1V2[n]
-
7/29/2019 Switched Cap Circuits II
13/23
Switch-Cap Integrator
GND
V1[n]
V2[n]
Vout[n] =
Vout[n-1] +(C
1/C
2) (V
2[n]- V
1[n])
GND
C2
C1
We disconnect the capacitor from the charge summing node,
and return to our initial case
(4), [n] cycle
(Output unchanged)
Q = -C2Vout[n-1]
+ C1(V1[n]-V2[n])
Vout[n] = Vout[n-1] + (C1/C2) (V2[n]- V1[n])
-
7/29/2019 Switched Cap Circuits II
14/23
Switch-Cap Integrator
1
GND
V1[n]
V2[n]
1
2
Vout
[n]
C
2
GND
By switching which input is first,we can digitally invert the signal
A[n]
V1
[n]
V2 [n]V
out[n]
A[n]
1
2
-
7/29/2019 Switched Cap Circuits II
15/23
Differential Switch-Cap Circuit
1
1
2
Vout+[n]
2
Vout
-[n]
Vin
+[n]
Vin
-[n]
Why?
C2
C1
C2
-
7/29/2019 Switched Cap Circuits II
16/23
Differential Switch-Cap Circuit
1
1
2
Vout+[n]
2
Vout
-[n]
Vin
+[n]
Vin
-[n]
Why? Higher PSRR, lower harmonic Distortion, lower noise
Cost?
C2
C1
C2
-
7/29/2019 Switched Cap Circuits II
17/23
Differential Switch-Cap Circuit
1
1
2
Vout+[n]
2
Vout
-[n]
Vin
+[n]
Vin
-[n]
Why? Higher PSRR, lower harmonic Distortion, lower noise
Cost? Larger Op-Amp, more power
C2
C1
C2
Vin
[n] = Vin
+[n] - Vin
-[n]
Vout [n] = Vout+
[n] - Vout-
[n](assume balanced output)
-
7/29/2019 Switched Cap Circuits II
18/23
Differential Switch-Cap Circuit
Vout+[n-1]
Vout
-[n-1]
Vin
+[n-1]
Vin
-[n-1]
C2
C1
C2
This case is important to understand our starting point
charge is stored on a capacitor ; therefore we need to know the initial state
(4), [n-1] cycle
Q = -C2Vout[n-1]/2
Voltage = 0V
(Voltage remains held)
Q = C2Vout[n-1]/2
-
7/29/2019 Switched Cap Circuits II
19/23
Differential Switch-Cap Circuit
Vout+[n-1]
Vout
-[n-1]
Vin
+[n]
Vin
-[n]
C2
C1
C2
Charge up the capacitor with voltage Vin[n]
(1), [n] cycle: 1
(Output unchanged)
Vin[n]
Q = -C2Vout[n-1]/2
Q = C2Vout[n-1]/2
-
7/29/2019 Switched Cap Circuits II
20/23
Differential Switch-Cap Circuit
Vout+[n-1]
Vout
-[n-1]
Vin
+[n]
Vin
-[n]
C2
C1
C2
We remove the capacitor from the first voltage.
The voltage is stored across the capacitor
(2), [n] cycle
(Output unchanged)
Vin[n]
Q1 = C1Vin[n]
Q1 = -C1Vin[n]
Q = -C2Vout[n-1]/2
Q = C2Vout[n-1]/2
-
7/29/2019 Switched Cap Circuits II
21/23
Differential Switch-Cap Circuit
Vout+[n]
Vout
-[n]
Vin
+[n]
Vin
-[n]
C2
C1
C2
Vout[n] = Vout[n-1] +
-2(C1/C
2) (V
in[n])
We connect the capacitor to the charge summing node
(3), [n] cycle: 2
Q = -C2Vout[n-1]/2 + C1Vin[n]
Q = C2Vout[n-1]/2 -C1Vin[n]
-
7/29/2019 Switched Cap Circuits II
22/23
Differential Switch-Cap Circuit
Vout+[n]
Vout
-[n]
Vin
+[n]
Vin
-[n]
C2
C1
C2
We disconnect the capacitor from the charge summing node,
and return to our initial case
(4), [n] cycle
(Output unchanged)
Vout[n] = Vout[n-1] 2 (C1/C2) Vin[n]
~0
-
7/29/2019 Switched Cap Circuits II
23/23
Stray Insensitive Circuits
Discussed issue of stray insensitive circuits
Discussed two typically used circuits,one single ended and one differential ended