thermal noise estimation in switched-capacitor circuits

12/21/2004 [email protected] 1/22

THERMAL NOISE ESTIMATION IN THERMAL NOISE ESTIMATION IN

SWITCHED-CAPACITOR SWITCHED-CAPACITOR

CIRCUITSCIRCUITS

José Silva and Gábor C. Temes

School of Electrical Engineering and

Computer Science

Oregon State University


Outline

• Thermal noise effects in an SC

integrator

– Switch (kT/C) noise

– Opamp thermal noise

• Noise calculations in ADCs

• Noise calculation Example


Noise Effects In SC Integrators• The thermal noise sources are the switches and the opamp.

• Flicker noise is negligible if fcorner << fs. If not, techniques such as correlated double sampling or chopper stabilization can be used.

C1

vout’vin

C2

vout2

21

1

1

S1

S2 S3

S4

mINg

kTPSD

3

16

onkTRPSD 4


Switch Noise• Noise charge power in C1 (assuming ideal opamp):

vn1 C1Ron1

Ron3

vn3

vn4C1Ron4

Ron2

vn2

C2

vout

• MS noise charge into C2, in every clock period:

12

2,12

1,121 2kTCqqq

• This can be represented by an equivalent input voltage noise source vn1 with MS value:

1

21

2

C

kTvn

1

21

2

C

kTvn

End of 1 End of 2

12

1,1 kTCq 12

2,1 kTCq


Op-amp Noise (1)

• Simplified method, ignoring switch resistance during Φ2=1

• Charge drawn by C1 from C2 in every clock period: C1 v-. This effect can be represented by equivalent input noise source vn2 = v-

C1

C2

vout

2

21

1

vn,eq

v-

- vC2 +


Opamp Noise (2)• To find v-, assume a single-pole model for the op-amp with ωu=gm1/CL

2

12 13

4

C

C

C

kTv

Lout LCCC

kTv

21

2

13

4

• MS voltage noise of v-, by voltage division:• Output MS voltage noise:

• C1 will extract a charge C1v- from C2 in every clock period. This effect can be represented by an input source vn2.

• Since vout = v- + vC2, an output equivalent source vn3 is also required.

It represents the unity-gain output noise during Φ1=1

• Using = 1/(1+C1/C2) as the feedback factor:

L

n C

kTv

3

422

Ln C

kTv

3

422

Ln C

kTv

3

423

Ln C

kTv

3

423


Integrator Noise Model

• Combining the effects of switch and opamp thermal noise:

vn1 vn2 vn3

vin vout

1

2

C

kT LC

kT

3

4

LC

kT

3

4

• Insert these noise sources into every integrator and SC branch.


More Accurate Model

x

kTC

/111

)

1

6/11(2 1

21

x

kTCq

11 2,13

4mongRx

x

kTC

Total power acquired in Φ1 and Φ2:

Assuming an output-compensated opamp,

Noise power acquired by C1 during Φ2=1:

From Ron :

from vno :

During Φ2 :

,


Design Considerations

1

3/ 122 x

CkTvn• In the model, now .The other two sources

remain unchanged. The overall input-referred noise is now about 2dB lower than that obtained from the simpler model.

• For several input capacitors, the noise charge powers add. For

two C1 branches, there is a 3 dB noise increase.

• The input – referred noise voltage v2c1 = q2

1 / C21 is minimized

for gm1 >> 1 / Ron. This costs added power. For gm1 << 1 / Ron,

the noise power is only 7/6 ~ 1.17 times larger.


An Efficient Design Algorithm

)23/7(121

xv

kTgm

c

11)/12( CgR mon

1])1)(2ln2[( sfN

;2 2,

)1(21 effin

Nc vv

12 1 mongRx

onR

1mg

1C )1/(11 xgC m 1mg

21cv

From previous relations, at the end of Φ2 =1,,where

is the settling time constant of the stage, and is the

input-referred noise power .To minimize ,1. Choose ,the largest value allowed

for settling to N-bit accuracy; 2. Choose 3. Choose 4. Find and from eqs. above;

5. Find from


Example (Integrator)

Calculated and simulated integrated noise powers at the output of the integrator. Simulation used [7].

• Let C1 = C2 = 2CL = 1 pF, gm1 = 4 mA / V, RL = 250kΩ, 2Ron = 0.5kΩ, fs = 100MHz. Then 2Ron C1 = C0 / (βgm1)= 0.5ns = 1 / 20fs , allowing for accurate settling.

• Integrating the output noise PSD over 0 to fB = fs / (2 · OSR) gives

f(Hz)


Noise Calculations in ADCs

• Step 1: Identify noise sources in the topology.

• Step 3: Calculate transfer function from each noise source to output.

• Step 4: Integrate each noise PSD over desired bandwidth.

• Step 5: Total noise power is sum of all contributions

N

jojn vv

TOTAL1

22

OSRsf

dfNTFvf

v jjs

oj

2

0

222 2

• Step 2: Calculate PSDs of noise sources.


Noise Budget

kT/C(50%)

opamp(25%)

other(20%)

Quantization(< 5%)

22222

OTHEROPAMPswqTOTAL nnnnn vvvvv

Quantization noise

Noise from other sources (digital, etc)

Switch (kT/C) noise

Opamp thermal noise

2

2

maxmax

TOTALn

u

v

vSNR

• Maximum SNR of a data converter:Maximum input

signal power

Total noise power

• The total noise power includes contributions from several sources:

• A good balance between these contributions:


Example: Low-Distortion Topology

• Integrators do not process input signal, only quantization noise.

No signal No distortion.

• For MASH structures, quantization noise can be tapped directly from yi2.

• In conventional topologies, integrator nonlinearities are attenuated by loop.

For low oversampling ratios, this is not effective.

• Distortion can be avoided by making STF = 1:

121

212

2

HH

HHSTF

H(z)H(z) H(z)H(z)

u

vyi1 yi2

2

DACDAC

q

To next stage

212

121

1

zHH

NTF

Feedforward paths


Noise Calculation Example (1)• Step 1: Identify thermal noise sources in the topology:

21

1

1

Ci1

CS1CS2

2 1

2

Ci2

1

2

CF3

2

1

CF2

CF1

2

1

QuantizerQuantizer

2.v 2.v

VREF+ VREF-

u

vq


Noise Calculation Example (2)• Step 2: Calculate PSDs of noise sources:

H(z)H(z) H(z)H(z)

u

vyi1

yi2

2

DACDAC

q

1

3/2

1

1

1

21

x

CkT

C

kTv S

Sni

Lno C

kTv

3

421

1

3/2

2

2

2

22

x

CkT

C

kTv S

Sni

LF

FFFno C

kT

C

CCCkTv

3

42

1

32122

1niv 1nov

2nov

2niv

• Noise powers:

• The PSDs are obtained by dividing noise powers by fs/2.


Noise Calculation Example (3)• Step 3: Calculate transfer function from each noise source to output:

H(z)H(z) H(z)H(z)

u

vyi1

yi2

2

DACDAC

q

1niv 1nov

2nov

2niv

• Assuming H(z) = z-1/(1 – z-1):

212

2

1 21

2

zzH

HHzNTFi

1122 1

1

zz

H

HzNTFi

2122 1

1

1)(

z

HzNTFo

1122 21

1

2

zzH

HzNTFo


Noise Calculation Example (4)• Step 4: Integrate each noise PSD over desired bandwidth:

(Tip: To save time, use a symbolic analysis tool such as Maple™)

0 0.1 0.2 0.3 0.4 0.50

5

10

15

20

25

30

35

40

Mag

nitu

de

Normalized Frequency

OSR

fs2

|NTFi1(ejT)|2

|NTFo2(ejT)|2

|NTFo1(ejT)|2

|NTFi2(ejT)|2

OSR

v

OSROSRvdfNTF

f

vN ni

niis

nii

OSRsf

212

1

0

2

1

212

1 sin452 2


Noise Calculation Example (5)

• Step 5: Finally, total noise is sum of all contributions:

22

22

21

21

2oioiTOTAL NNNNN

3

22

22

222 3

sin22

OSR

v

OSROSRvN ninii

5

22

42

222 5

sin8

cossin26

OSR

v

OSROSROSROSRvN nonoo

• Similarly:

3

21

22

121 3

sin18

sincos414

OSR

v

OSROSROSROSRvN nonoo


Numerical Example

5.88 v2n = 8.25

8.25 0.75

1.2 pF

• Since Cs1 and CC1 dominate the noise performance, ignore the rest. • Assume maximum input power is 0.25V2 ,and 16-bit noise

performance is desired. Total allowed noise power:

• Assume the loop operates with OSR=256, and choose x=2. Then,

• Allocating 75% of total noise to the thermal noise:

2122 1038 rmstotal VN


Additional Considerations• Wideband operation (OSR < 16):

– Input stage does not dominate noise. Optimization algorithms should be used to minimize total capacitance while meeting the noise target.

• Fully-differential circuits:– Use same total capacitance as for single-ended circuit. Noise power

increases by 3 dB for each side, and by 6 dB for differential mode. Signal power also increases by 6 dB, so total SNR is the same.

• MASH topologies:– Transfer functions should be calculated for whole system.

– Quantization noise is cancelled, and so is the noise from some sources.

• Calculations assume brick-wall decimation filter.– For more accuracy, actual transfer function of the decimation block can be

included in calculations.

• |STF(f)| = 1 was assumed. – Calculations are output referred. Signal power is affected by STF.


References

thermal noise estimation in switched-capacitor circuits

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