sv-scaling of mos circuits

8/3/2019 SV-Scaling of MOS Circuits

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Scaling of MOS circuits

by

SURESHA VSURESHA V

S c a l i n g o f M O S c i r c u i t s

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ro essor, ep . oro essor, ep . oVisvesvaraya Technological University(VTU)Visvesvaraya Technological University(VTU)BelgaumBelgaum--590 014.karnataka State. INDIA590 014.karnataka State. INDIAee--mail: [email protected]: [email protected]

Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327


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Objectives:

To know what is Scaling To know why scaling is required Figure(s) of Merit (FoM) for scaling Scaling models Scaling factors for device parameters

Implications of scaling on design


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Learning outcomes: At the end of this module the students will be able understand what is

scaling.

Understand how to improve the performance of simple MOS circuits byscaling.

Writing scaling Model for simple MOS device Understand the effect and limitation of scaling.



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Introduction:

What is Scaling?

Proportional adjustment of the dimensions of an electronic device while

maintaining the electrical properties of the device, results in a device either

larger or smaller than the un-scaled device. Then Which way do we scale the


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ev ces or an or an at o we ga n

Why Scaling?...

Scale the devices and wires down, Make the chips fatter functionality,

intelligence, memory and faster, Make more chips per wafer increased

yield, Make the end user Happy by giving more for less and therefore, make

MORE MONEY!!



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C o n t d

FoM for ScalingImpact of scaling is characterized in terms of several indicators:

o Minimum feature sizeo Number of gates on one chipo Power dissipationo Maximum operational frequency


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o Die sizeo Production cost

Many of the FoMs can be improved by shrinking the dimensions of transistors

and interconnections.

Shrinking the separation between features transistors and wires

Adjusting doping levels and supply voltages .



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C o n t d

Technology Scaling Goals of scaling the dimensions by 30%:

Reduce gate delay by 30% (increase operating frequency by 43%)

Double transistor density

Reduce ener er transition b 65% 50% ower savin s 43% increase in


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frequency)

Die size used to increase by 14% per generation

Technology generation spans 2-3 years



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C o n t d

Figure1: Illustrates the technology scaling in terms of minimum feature size.


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C o n t d

Figure2 : illustrates the technology scaling in terms of transistor count .


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C o n t d

Figure4: illustrates the technology scaling in terms of power dissipation anddensity


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Scaling Models

Most commonly used Models are:

Full Scaling (Constant Electrical Field): Ideal model dimensions and voltage

scale together by the same scale factor

Fixed Voltage Scaling: Most common model until recently only the


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dimensions scale, voltages remain constant

General Scaling: Most realistic for todays situation voltages and dimensions

scale with different factors



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Scaling Factors for Device Parameters

In our discussions we will consider two scaling factors, and

1/ is the scaling factor for V DD and oxide thickness D

1/ is scaling factor for all other linear dimensions


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We will assume electric field is kept constant



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Contd

It is important that you understand how the following parametersare effected by scaling

Gate Area

Gate Capacitance per unit area Gate Capacitance

Charge in Channel


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Transistor Delay

Maximum Operating Frequency Transistor Current

Switching Energy Power Dissipation Per Gate (Static and Dynamic)

Power Dissipation Per Unit Area

Power - Speed Product



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Contd

Example : Sacling of MOS tansistor


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Scaling Factors for Device Parameters

1. Gate area A g :

Where L: Channel length and W: Channel width and both are scaled by 1/

Thus Ag

is scaled up by 1/ 2


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2. Gate capacitance per unit area C o or Cox

Where ox is permittivity of gate oxide(thin-ox)= ins o and D is the gate oxidethickness scaled by 1/

Thus C ox is scaled up by



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C o n t d

3. Gate capacitance C g :

Thus Cg is scaled up by * 1/ 2 = / 2

4. Parasitic capacitance C x


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C x is proportiona to Ax

where d is the depletion width around source or drain and scaled by 1/

A x is the area of the depletion region around source or drain, scaled by (1/ 2 ).

Thus Cx is scaled up by



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C o n t d

5.Carrier density in channel Q on

where Q on is the average charge per unit area in the on state.

Co

is scaled by and Vgs

is scaled by 1/


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on

6.Channel Resistance R on

Where = channel carrier mobility and assumed constant

Thus Ron is scaled by (1/ * * 1) = 1



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C o n t d

7. Gate delay T d

T d is proportional to R on * Cg

Thus Td is scaled by

8. Maximum operating frequency f o


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f o is inversely proportional to delay T d and is scaled by



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C o n t d

9.Saturation current Idss

Both V gs and V t are scaled by (1/).

Therefore, Idss is scaled by


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10. Current density J:J= Idss /A

where A is cross sectional area of the

Channel in the on state which is scaled by (1/ 2)

So, J is scaled by



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C o n t d

11.Switching energy per gate Eg

So Eg is scaled by

12. Power dissipation per gate P g


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P g comprises of two components: static component P gs and dynamic component P gd:

Where, the static power component P gs is given by:

Dynamic component P gd is given by:

Since V DD scales by (1/ ) and Ron scales by 1, Pgs scales by (1/ 2 ).

Since Eg scales by (1/ 2 ) and fo by ( 2 / ), Pgd also scales by (1/ 2 ).

Therefore, P g scales by (1/ 2).



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C o n t d

13. Power dissipation per unit area P a

14. Power speed product P T


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S u m m a r y o f s c a l i n g e f f e c t s


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Physical Limits

Will Moores Law run out of steam?

Cant build transistors smaller than an atom

Many reasons have been predicted for end of scaling

Dynamic power


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Sub-threshold leakage, tunneling

Short channel effects

Fabrication costs

Electro-migration

Interconnect delaySuresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327


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Limitations of Scaling

Effects, as a result of scaling down- which eventually become severe enough to

prevent further miniaturization.

o Substrate doping

o De letion width


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o Limits of miniaturization

o Limits of interconnect and contact resistance

o Limits due to sub threshold currents

o Limits on logic levels and supply voltage due to noise

o Limits due to current density



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Contd

1. Substrate doping

Built-in(junction) potential V B depends on substrate doping level can be neglected

as long as V B is small compared to V DD.

As length of a MOS transistor is reduced, the depletion region width scaled down to

prevent source and drain depletion region from meeting.


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The depletion region width d for the junctions is given by



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Contd

V b built in potential and it given by


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Contd

2. Depletion width

N B is increased to reduce d, but this increases threshold voltage V t - against

trends for scaling down.

Maximum value of N B(1.3*1019 cm -3) , at higher values, maximum electric


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field applied to gate is insufficient and no channel is formed.

N B maintained at satisfactory level in the channel region to reduce the above

problem.

E max maximum electric field induced in the junction and it is given by



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Contd

If N B is increased by and if V a = 0 then Vb increased by ln and d is decreased

by

Therefore Electric field across the depletion region is increased by

Reach a critical level E crit with increasing N B


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Fig:5.2a shows the depletion width d as a function of N B and V dd .The dashed

line indicates the maximum depletion width for Emax= Ecrit ,then d we have



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Contd

Figure 5.1a: shows the relation between substrate concentration Vs depletion width ,


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Contd

Figure 5.1b: shows the relation between depletion width d and Electric field Vs,

substrate doping N B


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Contd

Figure 5.1c : Demonstrates the interconnect length Vs. propagation delay


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Contd

Figure 5.1d : Demonstrates the oxide thickness Vs. thermal noise.


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Contd

3. Limits of miniaturization Minimum size of transistor; process tech and physics of the device

Reduction of geometry; alignment accuracy and resolution

Size of transistor measured in terms of channel length L

=


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L determined by N B and V dd

Minimum transit time for an electron to travel from source to drain is

then the transit time t is given by



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Contd

Maximum carrier drift velocity is approx. equals to V sat ,regardless of supplyvoltage.Therefore minimum transit time maybe assumed to occur for a minimum sizetransistor when Va is approx. 0 V


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Contd

Fig 5.3 b : Relation for channel length L vs transit time t


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Contd

4 . Limits of interconnect and contact resistance

Short distance interconnect- conductor length is scaled by 1/ and

resistance is increased by

For constant field scaling, I is scaled by 1/ so that IR drop remains constant

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. .

Following graphs 5.6a and 5.6b shows the effect of interconnect and

resistance



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Contd

Figure5.6a : Demonstrates the length of interconnect L (mm) Vs propagationdelay(sec).


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Contd

Figure5.6 b : Demonstrates the length of interconnect L (mm) Vs propagation

delay(sec).


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Contd

5. Limits due to subthreshold currents Major concern in scaling devices.

I sub is directly proportional exp (V gs Vt ) q / KT

As voltages are scaled down, ratio of V gs Vt to KT will reduce-so that threshold

current increases.


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Therefore scaling V gs and V t together with V dd .

Maximum electric field across a depletion region is



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Contd

6. Limits on supply voltage due to noise Decreased inter-feature spacing and greater switching speed result in noiseproblems

Fig5.7a : Relation for Thermal noise v/s oxide thickness


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Contd

Fig5.7b : Relation for Thermal noise v/s substrate concentration


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Contd

Figure 5.8 : relation for probability of total error v/s supply voltage Vdd


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Contd

7. Limits due to current density:

Aluminum most commonly used material for forming interconnection in VLSI chips.

However scalingdown dimension increase the current density in interconnections by

the same factor.

When the current density in Aluminum approaches 10 6 Amps/cm 2 , the interconnect


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are likely to be burned off owing to metal migration.

The allowable current density in Aluminum are set below the limit of

J= 1 to 2 mA /m 2



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CONCLUSION

Observation - Device scaling

Gate capacitance per micron is nearly independent of process

But ON resistance * micron improves with process

Gates get faster with scaling (good )


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Dynamic power goes down with scaling ( good )

Current density goes up with scaling ( bad )

Velocity saturation makes lateral scaling unsustainable



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CONCLUSION

Observations Interconnect scaling

Capacitance per micron is remaining constant

About 0.2 fF/mm

Rou hl 1 10 of ate ca acitance


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Local wires are getting faster

Not quite tracking transistor improvement

But not a major problem

Global wires are getting slower

No longer possible to cross chip in one cycle



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SUMMARY

Scaling allows people to build more complex machines That run faster too

It does not to first order change the difficulty of module design

Module wires will get worse, but only slowly


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You on t t in to ret in your wires in your a er, memory

Or even your super-scalar processor core

It does let you design more modules

Continued scaling of uniprocessor performance is getting hard

Machines using global resources run into wire limitations

Machines will have to become more explicitly parallel



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R e f e r e n c e

Basic VLSI design by Douglas A. Pucknel and Kamran Eshraghian, 3rd edition

PHI publication, India, year 2001( Page 123-144 )


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Any Question ?



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Any correction or suggestion please

feedback to:

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Suresha V Professor Dept of E&C KVG College Of Engineering Sullia D K 574 327

e-mail : [email protected]

Mobile : +91 - 94485 24399

sv-scaling of mos circuits

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