summary of chapter 5

7/30/2019 Summary of Chapter 5

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Components of the System Bus & Attached Devices

Operation ofthe Bus

1. Module send data (Transfer data via Bus)2. Module request data ( Must wait for second module to send data)

Internal Bus

Bus located within CPU chip for communications

External Bus

Supported by third-party hardware and software and more likely to adhere to one of anumber of industry standards for buses

System Bus consist common set of parallel wires

1. Address Buses (Frequently transfer address from program counter)2. Data Buses (Carry data, instructions and addresses between main MEM and ALU)3. Control Buses (Carry signals from control unit to other components of CPU and back to

Control Unit)

Introduction

BUS System Bus

Peripheral

Devices

Bus Clock

Pulse

Data

TransferRate
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Physical Realization of Bus Architecture
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High Performance Bus

Processor Cache/Bridge System Bus

SCSI P139

Graphic Video

Main Memory

LAN

High Speed Bus

FAXExpansion bus

interface Modem Serial

Expansion Bus

Local Bus


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Bus Hierarchy

1) The Processor Bus (System Bus)a) Highest level bus that chipset uses

2) The Cache Bus (Backside Bus)

a) High level architecture

b) Conventional processors using 5th generation motherboards; cache connected to

standard memory bus.

3) The Memory Bus

a) 2nd level bus that connects the memory subsystem to the chipset

4) The Local I/O Bus (High-speed I/O Bus)

a) High-speed input/output bus used for connecting

b) Common is VLB & PCI

5) The Standard I/O Busa) Used for slower peripherals and older devices

b) ISA (Industry Standard Architecture) bus

Diagram of Various Buses that connects to the CPU

CPU

Level 2

Cache

Memory

Controller

R

A

M

R

A

M

R

A

M

R

A

M

Bus

Bridge

AGP

Chipset

Graphics

Card

Bus

Bridge

System

Memory

Frontside S stem Bus

PCI

Devices

ISADevices

PCI BUS


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Performance of a Bus:-

1) Transfer Time

a) Amount of time taken to be delivered

b) Transfer time defines how long a processor will have to wait when it fetches aninstruction from memory

2) Bandwidth

a) Units bits per second measure the capacity of bus

b) Can be transferred in parallel in one transaction

c) 32 data lines deliver 1,000,000 packets per second , it has bandwidth of 32Mbps

Characteristics of

Bus

Data & Address Bus

Data bus (Lines that carry data)

Address bus (Set of lines that carry

information about where memory the

data is transferred)

Control bus(How the bus functions)

Bus Width

Wider bus , more information flow

Width of bus dictates No of memory

locations that bus can transfer

information to/from

ISA - 16bits

VLB/PCI - 32 bits

Bus Speed

Speed of bus , Bits of information sent

across

AGP buses move 2 bits of data per

clock cycle

Older buses like ISA have two clock

cycles to move 1 Bit

Bus Bandwidth

Total amount of data can theoretically

be transferred on a bus in given time

Measured in bits per second / bytes per

second

Bandwidth= bus width X bus speed

Slow bus bandwidth = (bus width X

bus speed)


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System Board

System board ofintegrated

technologies on it(ISA,PCI,AGP)

ISA slots are the blackslots on lower portion

of the board in theimage


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BUS

STANDARDS

Industry Standard Architecture

Common bus in PC world

Industry Standard Architecture

Standard = Actually fits

Many devices for which ISAs speed is more

than sufficient and will be standard modems

Micro Channel Architecture

MCA(Micro Channel Bus)

MCA(Micro Channel Architecture)

Introduced in 1987

Extended Industry Standard Architecture (EISA) Bus

Never became widely used and cannot be considered

an industry standard.

VESA Local Bus(VLB)

1st

to gain popularity

Introduced in 1992

To improve video performance in PCs

Peripheral Component Interconnect (PCI) Local Bus

Most popular local I/O bus

By Intel in 1993

Geared to 5th

and 6th

generation systems

Accelerated Graphic Port

Developed in response to the trend towards

greater performance requirements for video.

Increase bandwidth between main processor

and video subsystem


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PCI Bus

Performance

BURST MODE(Transferinformation in burst mode

where after an intialaddress is provided inmultiple sets of data

BUS MASTERING(PCIsupports full bus

mastering which leads toimproved performance)

HIGH BANDWIDTHOPTIONS(Specification

version 2.1 calls forexpandability to 64bits

and 66 MHz speed

summary of chapter 5

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