structured logic design with vhdl ivan dugic [email protected] veljko milutinovic [email protected]...
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Structured Logic Design With VHDL
Ivan [email protected]
Veljko [email protected]
School of Electrical Engineering
University of Belgrade
Department of Computer Engineering
Ivan Dugic
Reference
James R. Armstrong, F. Gail Gray Structured Logic Design with VHDL,
PTR Prentice Hall 1993.
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Introduction
VHDL - VHSIC Hardware Description Language VHSIC - Very High Speed Integrated Circuit
Development of a hardware description language model
as a step in digital design at a high level of abstraction
Development of VHDL began in 1983,sponsored by
Department of defense, further developed by the IEEE
and released as IEEE Standard 1076 in 1987
Today it is De facto industry standard for hardware description languages
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Structured Design Concepts
Ivan Dugic
Structured Design Concepts The abstraction hierarchy
The abstraction hierarchy employed by digital designers is a set of interrelated system representation
Can be expressed in two domains: structural domain, behavioral domain
Structural domain – component model is described in terms of an interconnection of more primitive components
Behavioral domain – component model is described by defining its input/output response
VHDL is used for behavioral description
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Structured Design Concepts The abstraction hierarchy Six abstraction hierarchy levels of detail commonly used in design: silicon,
circuit, gate, register, chip and system
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Structured Design Concepts Representations
Design representations can be either pictorial or textual Pictorial forms (used for structural description): block diagrams,
timing diagrams, state tables etc. Textual methods of representation (used for behavioral description):
natural languages (e.g., English), equations (e.g.,Boolean)
and computer languages (Hardware Description Language)
Pictures are better for illustrating interrelationships Text is better for representing complex behavior Excessive use of either pictures or text result
in a loss of perspective – “one cannot see the forest for the trees.”
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Structured Design Concepts
Types of behavioral descriptions
Two types of behavioral description – algorithmic and data flow Algorithmic – a procedure or program defining the I/O response with no
implies of any particular physical implementation Data flow – a behavioral description in witch the data dependencies is
the description match those in a real implementation
Algorithmic and data flow descriptions are HDL implementations of
behavior at the chip and register levels respectively
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Structured Design Concepts Design process
Design – a series of transformations from one representation of a system to another until a representation exists that can be fabricated
The design cycle consists of a series of transformations -
synthesis steps:
(1) Transformation from English to an algorithmic
natural language synthesis
(2) Translation from an algorithmic representation to a data flow
representation or to a gate level representation
algorithmic synthesis
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Structured Design Concepts Design process
(3) Translation from data flow representation to a structural logic
gate representation
logic synthesis
(4) Translation from logic gate to layout and circuit representation
layout synthesis
The design cycle steps can be carried out automatically in all stages except the first that is currently an active area of research
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Structured Design Concepts Design process
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Structured Design Concepts Structural design decomposition
The structural form of the design hierarchy implies
a design decomposition process Two types of design: full tree design and partial tree design
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Structured Design Concepts Structural design decomposition Difference – in the full tree design all behavior is specified
at the same level, in partial tree design at different levels Partial tree design is encountered because one frequently wants
to evaluate the relationships between system components
before they have been completely designed Two concepts of tree design: top-down and bottom-up
Digital design is carried out in order to meet some objective criterion Major criteria concerning design and fabrication process:
speed, chip area, cost
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Structured Design Concepts The digital design space
Major criteria can be considered to be dimensions
in Digital Design Space,with different tracks
for various designs
Example - circuits A and B implement the same logic function,
circuit A uses less area then B but is slower
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Design tools
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Design tools
CAD tool taxonomy
CAD tool – a software program used in the design process
which assists in performing or automates a particular design function CAD tool taxonomy breaks tools down into classes
and sub classes
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Design tools
CAD tool taxonomy
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Design tools
CAD tool taxonomy Editors – textual (circuit level – SPICE gate, register,chip – VHDL) or
graphic (used at all levels) Simulators – stochastic (system level,determines for example
the percentage of time that a particular unit is busy)
or deterministic (all levels above the silicon level) Checkers and Analyzers – employed at all levels,
used for example to insure that the layout implies a circuit
that can be fabricated reliably (rule checkers),
to check for the longest path through a logic circuit or system
(timing analyzers) Optimizers and Synthesizers – improving a form
of the design representation
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Design tools
Schematic editors
Editors that can be used to create and display an interconnected set of graphic tokens correspond to structural primitives
Also creates a simulation model Typical editor features:
(1) Library of primitive symbols including a simulation model
corresponding to each primitive
Primitives – native (fundamental logic elements e.g., ANDs and ORs),
standard parts families (e.g.,TTL,CMOS,ECL)
Library can be extended with new symbols
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Design tools
Schematic editors
(2) A system of graphic windows which can be used to create
an interconnect of graphic tokens
(3) Commands for creating wire lists
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Design tools
Simulators
Major tools used in the development of digital systems Programs which models the response of a system to input stimuli Modeling approach – system is modeled in interconnected net of
digital elements, mapping the function of a digital logic element onto one or more processes
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Design tools
Simulators
Process – computational entity which models the function
and delay of the digital device
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Design tools
Simulators A network of devices is modeled by a network of processes A wire between devices in the digital network is modeled by
a signal in the process network
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Design tools
Simulators The simulator operates on the network of processes –
tracking process responds to signal transactions on its inputs These transactions are kept in the simulator time queue as
a two-tuple forms (SignalName,Value)
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Design tools
Simulators Simulation efficiency – very important when simulating large systems,
defined as
E = real_logic_time / host_CPU_time
host_CPU_time – time of simulation process
Complete simulation of complicated VLSI system on conventional processors can literally require months (and even years!)
Various simulation engines are developed enforcing parallel processing
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Design tools
Simulators An example of complete simulation system
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Design tools
Synthesizers
Used either to automate a design step or to provide assistance during the performance of a design step
A computer program that automatically performs a translation
from one design representation to another
or a program that assists a human in making the translation
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Design tools
Synthesizers The process of optimizations is usually performed An optimization example
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Design tools
Synthesizers Specialized for a particular line of component or particular company
and are often restricted in availability due to industrial proprietary interests High level synthesizer
translates a representation of a circuit at a high level abstraction into
a lower level of abstraction e.g.,algorithmic to gate Low level synthesizer
gate to algorithmic Data flow synthesizer
data flow to lower level
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Basic Feature of VHDL
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Basic Features of VHDL Design entities
In VHDL a represented logic circuit is represented as
a design entity A design entity consists of two different types of description:
interface description and one or more architectural bodies
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Basic Features of VHDL Design entities The description of interface signals includes
the mode of the signal (i.e., in or out) and the type of the signal,
in previous case 3-bit and 2-bit vectors The truth table has been inserted as a comment –
any line beginning with two dashes is interpreted as a comment
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Basic Features of VHDL Architectural bodies
Architectural bodies are specifying the behavior of the entity Two types: algorithmic, structural Algorithmic - at the beginning of the design process,
designers usually would like to check the accuracy of the algorithm without specifying the detailed implementation
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Basic Features of VHDL Architectural bodies
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Basic Features of VHDL Architectural bodies Structural - the logic design stage
Used design hierarchy in ONES_CNT:
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Basic Features of VHDL Architectural bodies This architectural design implies the existence of
MAJ3 and OPAR3 gates at the hardware level
architectural MACRO of ONES_CNT is
begin
C(1) <= MAJ3(A);
C(0) <= OPAR3(A);
end MACRO;
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Basic Features of VHDL Architectural bodies MAJ3 and OPAR3 are decomposed into AND and OR gates
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Basic Features of VHDL Model testing
VHDL models must be tested Testing is performed by forming a top level entity called a test bench
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Basic Features of VHDL Model testing
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Basic Features of VHDL Model testing TEST_BENCH entity declaration contains no port statements – the test
signals are generated internal to the test bench The result of simulating this test bench:
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Basic Features of VHDL Block statements
A basic element of a VHDL description is the block
BlockName:block
----Inner block declaration section
----
begin
----Inner block executable statements
----
end block BlockName;
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Basic Features of VHDL Block statements Block nesting is possible
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Basic Features of VHDL Block statements GUARD Boolean condition can be associated with the block (CON = ‘1’) When FALSE enables certain types of statements inside the block –
guarded statements (O1 <= guarded I1;)
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Basic Features of VHDL Block statements Any guarded statement will be executed when
(1) The guard is TRUE and a signal on the right hand side
changes
(2) The guard changes from FALSE to TRUE
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Basic Features of VHDL Processes
Process is another major modeling element in VHDL
ProcessName ( sensitivity list of signals )
Example – MAJ3(A) Whenever a signal in sensitivity list changes, the process is activated
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Basic Features of VHDL VHDL lexical description
ASCII character code set is used in VHDL Character set – upper case A…Z, lower case letters a…z, digits 0-9,
special characters
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Basic Features of VHDL VHDL lexical description User defined identifiers – sequence of characters that starts with a letter
and includes only letters, digits and isolated underline characters,different from VHDL reserved words
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Basic Features of VHDL VHDL lexical description Comment – begins with two dashes,
extra dashes can enhance readability Character literals – one character between two apostrophe delimiters –
‘A’, ‘ ‘, etc. String literals – sequence of printable characters between
two quotation delimiters Long string literals exceeding the capacity of line must be concatenating
by shorter strings, using the & character
“A simple string literal.” -- length= 24
“ “ -- length =0
“A” --different from ‘A’
“This is a very long string… and” &
“it requires concatenation”
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Basic Features of VHDL VHDL lexical description
Bit string literal – real and integer Consists of a string of digits appropriate for the base, enclosed by
quotation delimiters and preceded by a base specifier,
B (binary), O (octal), X (hexadecimal)
B”11011110”
O”742”
X”DE”
Decimal literal – real and integer The exponent part of the literal is preceded by letter E, no spaces allowed
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Basic Features of VHDL Data types
Strong typed language Four classes of data types – scalar,composite,access,file Scalar data types – enumeration, numeric, physical data types Composite data types – arrays, records
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Basic Features of VHDL Scalar data types
Enumeration data types
type EnumerationTypeName is (value1,…valueN);
Example
type COLOR is (RED, ORANGE, YELLOW, GREEN, BLUE, INDIGO, VIOLET);
Specific number for every value – RED is 0, VIOLET is 6
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Basic Features of VHDL Scalar data types Different attributes can be used, for example “pos”, ”left”, ”right”, ”low”.
”high”, ”pred”, ”leftof”, ”rightof” etc. Attributes names are attached to the type name using the apostrophe,
sometimes called “tick” character – some examples follow
COLOR’pos(GREEN) = 3
COLOR’leftof(GREEN) = yellow etc.
Subtypes declaration do not define a new type –
simply contain the values of the specified type
subtype LONGWAVE is COLOR range COLOR’left to YELLOW;
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Basic Features of VHDL Scalar data types Numeric Data Types – Integer and Real
type NumericDataTypeName is range value1 to(downto) valueN;
Example
type COUNTER is range 0 to 100;
type PROBABILITY is range 0.0 to 1.0;
Attributes, subtypes can be used as in scalar data types
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Basic Features of VHDL Scalar data types
A physical data type is a scalar numeric data type
with an associated system of units, such as time, length, voltage, current etc.
TIME is only predefined physical data type, defined as follows
type TIME is range
units
fs;
ps = 1000fs;
ns = 1000ps;
us = 1000ns;
ms = 1000us;
sec = 1000ms;
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Basic Features of VHDL Scalar data types
(continued)
min = 60sec;
hr = 60min;
end units;
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Basic Features of VHDL Composite data types
Arrays
type ArrayName is array(value1 to(downto) valueN) of ArrayType;type ArrayName is array (POSITIVE(NATURAL) range <>) of ArrayType;
For example
type REGISTER_32_BIT is array (31 downto 0) of BIT;
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Basic Features of VHDL Composite data types Two predefined data types – STRING (array of CHARACTERs),
BIT_VECTOR (array of BITs)
type STRING is array (POSITIVE range <>) of CHARACTERS;
type BIT_VECTOR is array (NATURAL range <>) of BIT;
The effect is that a user may specify the range when declaring
an entity or type STRING – notation <> means unconstrained
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Basic Features of VHDL Composite data types Records - composite types with heterogeneous elements For example
type DATE is record
DAY : INTEGER range 1 to 31;
MONTH: MONTH_NAME;
YEAR : INTEGER range 0 to 3000;
end record;
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Basic Features of VHDL Classes of objects
There are three classes of data objects – constant, variable,signal Declaration of data objects
constant ConstantName:DataType := value;
variable VariableName:DataType := initial_value;
signal SignalName:DataType := initial_value;
All ports must be signals
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Basic Features of VHDL Assignment statements
Variable assignment is different from signal assignment –
in the first case it is used delimiter :=, in second <= Some examples
STAR_COLOR := GREEN;
BETA_LEVEL := 0.5;
X1 <= ’1’ after 10 ns;
SR1 <= 5 after 5 ns;
X2 <= ’0’ after 10 ns, ’1’ after 20 ns, ’0’ after 30 ns;
X5 <= ’1’;
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Basic Features of VHDL Assignment statements
Delta time – VHDL signals in order to correctly represent physical quantities do not change instantaneously
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Basic Features of VHDL Signal variables
The VHDL language predefines several attributes for signals:
“active”, ”event”, ”stable”, “quiet”, “last_event”, “last_active”, “last_value”, “delayed”
Examples
X2’active
–- TRUE when a transaction occurs on X2
X2’event
-- TRUE when an event occurs on X2
X1’stable
–- TRUE unless there is an event
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Basic Features of VHDL Signal variables
X1’stable(5 ns)
–- TRUE when there has been no events on signal X1
-- during the past 5 ns
X3’quiet
-- TRUE unless there is a transaction on signal
-- X3
X1’last_event
-- has a value equal to the amount of time that has
-- elapsed since last event on X1
X’delayed(5 ns)
-- defines a signal equal to X1 delayed by 5 ns
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Basic Features of VHDL Operators and expressions
Logic operators – on variables or signals of BIT or BOOLEAN type /= means not equal to ** exponentiation
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Basic Features of VHDL Control statements
Control statements – sequential, parallel
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Basic Features of VHDL Sequential control statements Wait statement
wait on SignalName[,SignalName] until Expression for Time;
Example
wait on Z,Y until Z=0 for 100 ns;
If an event occurs on X or Y prior to 100 ns, then “Z=0” is evalueted. If “Z=0” is TRUE when the event on X or Y occurs, then the process will resume at the time, otherwise suspension occurs.
The statement suspends execution of the process for maximum of 100 ns The process resumes after 100 ns has passed or when an event occurs
on X or Y with Z=0.
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Basic Features of VHDL Sequential control statements If statement
if Condition then
SequenceOfStatements
elseif Condition then
SequenceOfStatements
…
else
SequenceOfStatements
end if;
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Basic Features of VHDL Sequential control statements Example
if A<0 then
LEVEL := 1;
elseif A>1000 then
LEVEL := 3;
else LEVEL := 2;
end if;
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Basic Features of VHDL Sequential control statements Case statement
case Expression is when Choices => SequenceOfStatementswhen Choices => SequenceOfStatements…when others => SequenceOfStatements
end case;
Example
case A+B iswhen 0 => X <= ”ZERO”when (1 to 20) => X <= ”POSITIVE”when others => X <= ”NEGATIVE”
end case;
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Basic Features of VHDL Sequential control statements
Loop statement
-- Simple loop
loop
SequenceOfStatement
end loop;
-- FOR loop
for Name in Range loop
SequenceOfStatement
end loop;
-- WHILE loop
while Condition loop
SequenceOfStatement
end loop;
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Basic Features of VHDL Sequential control statements
Example
loop
compute (x);
exit when x<10;
end loop;
for I in 1 to 10 loop
A(I) := A(I) + 1;
end loop;
while A<B loop
A := A + 1;
end loop;
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Basic Features of VHDL Sequential control statements Next statement Used to terminate the current loop iteration if a given condition is true
next [LoopLabel] [when Condition];
Exit statement Similar to the “next” except that the entire loop statement is terminated
exit [LoopLabel] [when Condition];
Null statement Does nothing, useful in case statements – if no action is desired for
certain choices
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