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EECS 240 Lecture 2: CMOS - passive devices 2011 A. M. Niknejad,B. Boser,S.Gambini

EECS 240Analog Integrated Circuits

Lecture 2: CMOS Technology andPassive Devices

Ali M. Niknejad,Bernhard E. Boser,S.Gambini 2011

Department of Electrical Engineering and Computer Sciences

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CMOS Technology

Why look at it (again)?

Key issues:1. Perspective

Device dimensions

Device performance metrics, e.g.:

Current efficiency

Speed

Gain

Noise

2. Short-channel characteristics Square-law model

Models for circuit simulation

Design

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Todays Lecture

CMOS cross-section

Passive devices Resistors

Capacitors

Next time: MOS transistor

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CMOS Process

Cadence GPDK 90nm

Minimum channel length: 0.09m

1 level of polysilicon

7 levels of metal (Cu)

1.2V supply

Other choices

Shorter channel length (45/32 nm / 1.1V) Bipolar, SiGe HBT

SOI

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Supply Voltage

0

1.375

2.750

4.125

5.500

1 0.8 0.5 0.35 0.25 0.18 0.12 0.08 0.06

SupplyVoltag

e[V]

Feature Size [m]

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CMOS Cross Section

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Dimensions

Drawing is not to scale!

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Devices

Active NMOS, PMOS

NPN, PNP

Diodes

Passive Resistors

Capacitors Inductors

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Resistors

No provisions in standard CMOS

Resistors are bad for digital circuits

Minimized in standard CMOS

Sheet resistance of available layers:

Example: 100k poly resistor

1m wide by 20,000m long

Layer Sheet resistance

AluminumPolysiliconN+/P+ diffusionN-well

60 m/

5 /

5 /

1 k/

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Process Options

Available for many processes

Add features to baseline process

E.g. Capacitor option (MIM, 2 level poly, channel implant)

Low VTH devices

High voltage devices (3.3V)

EEPROM

Silicide stop option

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Silicide Technology

Implants used to lower resistance of source/drainand polysilicon.

Titanium Silicide (TiSi2) is widely used salicide

(self-aligned silicide), has low resistivity (13-17

m-cm) with melting point of 1540C. Another

widely used silicide is CoSi2.

Platinum Silicide (PtSi) is a highly reliable

contact metallization between the silicon substrateand the metal layers (Al).

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Silicide Block Option

For moderate resistor values (up to 100K), unsalicidedpoly by far the best option when available

Non-silicided layers have significantly larger sheetresistance

Resistor nonidealities:

Temperature coefficient: R = f(T)

Voltage coefficient: R = f(V)

Layer R/ [/] TC [ppm/oC]

@ T = 25o

C

VC [ppm/V] BC [ppm/V]

N+ polyP+ polyN+ diffusionP+ diffusionN-well

10018050

1001000

-800200

15001600

-1500

5050

500500

20,000

5050

-500-500

30,000

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Resistor ExampleGoal: R = 100 k, TC = 1/R x dR/dT = 0

Solution: combination of N+ and P+ poly resistors in series

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Voltage Coefcient

Example:

Diffusion resistor

Applied voltage modulates depletionwidth

(cross-section of conductivechannel)

Well acts as a shield

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Resistor Matching

Types of mismatch

Systematic (e.g. contacts)

Run-to-run variations

Random variations between devices

Absolute resistor value

E.g. filter time constant, bias current (BG reference)

~ 15 percent variations (or more)

Resistor ratios

E.g. opamp feedback network

Insensitive to absolute resistor value

unit-element approach rejects systematic variations(large area for non-integer ratios)

Process gradients

0.1 1 percent matching possible with careful layout

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Resistor Layout

Example: R1 : R2 = 1 : 2 gradient

R1

0.5 * R2 - R

0.5 * R2 + R

Dummy

Dummy

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Resistor Layout (cont.)

Serpentine layout for large values:

Better layout (mitigates offset due to thermoelectric effects):

See Hastings, The art of analog layout, Prentice Hall, 2001.

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MOSFETs as Resistors

Triode region (square law):

Small signal resistance:

Voltage coefficient:

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MOS Resistors

Example: R = 1 M Large R-values realizable in small area

Very large voltage coefficient

Applications:

MOSFET-C filters: (linearization)Ref: Tsividis et al, Continuous-Time MOSFET-C Filters in VLSI, JSSC, pp. 15-30, Feb. 1986.

Biasing: (>1G)

Ref: Geen et al, Single-Chip Surface-

Micromachined Integrated Gyroscope with 50o/hour Root Allen Variance, ISSCC, pp. 426-7,Feb. 2002.

Mostly for low-frequency application

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Resistor Summary

No or limited support in standard CMOS

Costly: large area (compared to FETs)

Nonidealities:

Large run-to-run variations

Temperature coefficient

Voltage coefficients (nonlinear)

Avoid them when you can

Especially in critical areas, e.g.

Amplifier feedback networks

Electronic filters

A/D converters

We will get back to this point

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Capacitor Applications

Large value

Bypass capacitors

Frequency compensation

High accuracy, linearity

Feedback & sampling networks

Filters

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Capacitor Options

Type C [aF/m2] VC [ppm/V] TC [ppm/oC]

Gate ~20000 Huge Big

Poly-poly (option) 1000 10 25

Metal-metal (Finger) 1000-2000 20 30

Metal-substrate 30

Metal-poly 50

Poly-substrate 120

Junction capacitors ~ 1000 Big Big

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MOS Capacitor

High capacitance in inversion:

Linear region

Strong inversion

SPICE:

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MOS Capacitor

High non-linearity,

temperature coefficient

Gate leakage for thin-ox devices

Useful only for non-criticalapplications, e.g.

(Miller) compensation capacitor

Bypass capacitor (supply, bias)

Sometimes depletion devices

available which have better

linearity (NMOS in N-well)

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Poly-Poly Capacitor

Applications:

Feedback networks

Filters (SC and continuous time)

Charge redistribution DACs & ADCs

Cross-section

Bottom- and top-plate parasitics

Shields

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Capacitor Layout

Unit elements

Shields:

Etching

Fringing fields Common-centroid

Wiring and interconnect parasitics

Ref.: Y. Tsividis, Mixed Analog-Digital VLSI Designand Technology, McGraw-Hill, 1996.

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Metal Capacitors

Available in all processes

(with at least 2 levels of metalization)

Large bottom plate parasitic

Often loads amplifier

increased load adds power dissipation

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MIM Capacitors

Many processes have add-on options such

as a MIM capacitor.

This is simply a metal-insulator-metal(MIM) structure situated in the oxide

layers. The insulator is a very thin layer

(~25 nm), resulting in high density and

relatively low back-plate parasitics.

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Custom MOM

Metal-Oxide-Metal capacitor. Free with modern CMOS.

Use lateral flux (~Lmin) and multiple metal layers to realizehigh capacitance values

Matching limited by layer thickness variations

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MOM Capacitor Cross

Use a wall of metal and

vias to realize high

density.

Use as many layers aspossible. Use fewer

layers to minimize back-

plate parasitics.

Reasonably good

matching and accuracy.

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Commercial BiCMOS Process

www.ibm.com/chips/techlib/techlib.nsf/techdocs/FE154539B8C4C01687256CD9007346D7/$file/180-nmCMOS3-24-04.pdf

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Typical 180nm CMOS

Leff < L

High volage IO

devices High voltage

device has

thick oxide


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Triple Well Option

Many modern process have a triple well (deepwell) option that allows NFETs to be isolated

from the substrate. Older notation: twin-well. This provides better immunity from digital noise

in a mixed signal circuit.

p-sub

n-well

deep n-well

p-well

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Isolation Options


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Bipolar Devices


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Passives


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Distributed Eects

Can model IC resistors as

distributed RC circuits.

Transmission line

analysis yields theequivalent 2-port

parameters.

Inductance negligible for

small IC structures up to

~10GHz.

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Eective Resistance

Rsh = 100 /, Cx=3.4510-5 F/m2

10k resistor drops to 5k at 1 GHz ! (W=5) High frequency resistance depends on W. Need

distributed model for accurate freq response.

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Capacitor Q

Current density in capacitor plates drops

due to vertical displacement current. Must analyze the distributed RC circuit

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Capacitor Impedance

For a capacitor contacted at one side, we

can show that

We can simplify this for small structures

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Double Contact Strucutre

Instead of doing distributed analysis, we can guess the

current distribution as linear and quickly calculate theeffective resistance.

For a double contact case, the resistance drops by 4 times.

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Once in the domain of RF circuits, now inductors

are finding applications in wideband design (e.g.

shunt peaking).

By proper design, the bandwidth of the RC circuit

can be boosted by 85% (20% peaking).

On-Chip Inductors

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Spiral Inductors

These inductors are small (0.1-10 nH) and are used widely

in RF circuits. Use top metal for high Q and high self resonance

frequencies. Very good matching and accuracy.

l d

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Multi-Layer Inductors

By taking advantage of multiple metal layers andmutual coupling, we can realize very largeinductors (~ 100 nH).

Top view 3D view (not to scale)

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