storage class memory: opportunities and...

© 2007 IBM Corporation© 2007 IBM Corporation

LETI Workshop on Innovative Memory Technologies 2009 © 2009 IBM Corporation

IBM Research

Storage Class Memory: Opportunities and Challenges

C.Lam Ph.D.Distinguished [email protected]

© 2009 IBM Corporation

IBM Research

2 LETI Workshop on Innovative Memory Technologies June 24, 2009

1 Introduction

2 Opportunities

3 Challenges

4 Emerging Memory Technologies

5 Summary

1 Introduction

2 Opportunities

3 Challenges


5 Summary


IBM Research


Definition of Storage Class Memory

� An IBM term for solid-state non-volatile memory technologies that are capable of replacing Hard Disk Drives and complementing DRAM.


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How SCM will change future computing systems

ArchivalActive StorageMemoryLogic

2013+RAM

Storage Class Memory Disk Tape

2008 RAMFlashSSD Disk Tape

1990 RAM Disk Tape


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1 Introduction

2 Opportunities

3 Challenges


5 Summary

1 Introduction

2 Opportunities

3 Challenges


5 Summary


IBM Research


Many Cores = Troubles for High Performance Computing

� Conventional architecture is practically broken

� Stacked memory architecture is of little or no utilities

Source: Multicore Is Bad News For Supercomputers, IEEE Spectrum November 2008

A cost/performance memory is needed to relieve memory bottle neck.


IBM Research


History of HDD is based on Areal Density Growth

Source: IBM Systems Journal, vol. 42, no.2, 2003. •Source: www.hitachigst.com/hdd/research/images/


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Hard Disk Drive Performance

0000

1111

2222

3333

4444

5555

6666

7777

8888

1985198519851985 1990199019901990 1995199519951995 2000200020002000 2005200520052005 2010201020102010

DateDateDateDate

Latency, [ms]

Latency, [ms]

Latency, [ms]

Latency, [ms]

1111

10101010

100100100100

1000100010001000

1998199819981998 2000200020002000 2002200220022002 2004200420042004 2006200620062006 2008200820082008

DateDateDateDate

Bandwidth [MB/s]

Bandwidth [MB/s]

Bandwidth [MB/s]

Bandwidth [MB/s]

Latency, [m

s]

Bandwidth, [M

B/s]

HDD performance specifications are most vulnerability targets.


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Hard Disk Drive Reliability & Cost of Ownership

E.Pinheiro et al, FAST’07Disk Age

Annualized Failure Rate [%]

Reliability & Power Consumption of HDD are critical issues.


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Evolution of NAND Flash

Charge storage capacity scales unfavorably with CD.


IBM Research


SCM SSD Market Opportunity


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Projected SCM Impact to Exascale ComputingStorage Bandwidth Disk PCM SCMRequirement

0.4 PB/s Devices 1.3M disks 406,000 modules

Space 6,192 sq.ft. 85 sq.ft.

Power 6 MW 41 KW

1.7 PB/s Devices 5.6M disks 1.7M modules


Power 25 MW 173 KW

2.0 Giga-SIO/s Devices 5M disks 8,000 modules


Power 22 MW 1 KW

8.4 Giga-SIO/s Devices 21M disks 35,000 modules


Power 93 MW 4 KW

Compute-centric

Data-centric

Note: SCM is used both as the main memory beyond giga-scale densities.Source: R.F. Freitas and W.W. Wilcke, IBM J Res & Dev Vol 92 No 4/5 p.439 2008


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1 Introduction

2 Opportunities

3 Challenges


5 Summary

1 Introduction

2 Opportunities

3 Challenges


5 Summary


IBM Research


Memory Cell Size is the Key

STORAGECLASS MEMORY


IBM Research


Cost

# of layers or bits

Succeeding SCM technology must be able to Multi-bit and/or Multi-layer.

Beyond Physical Scaling

MemoryElement

Diode

� Back End Multi-Layer Integration

� Large memory dynamic range

Source: Ovonyx Website


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Reliability: Endurance and Data Retention

Arbitrary units

Energy

Brute Force Write � Fatique/Damage � Endurance/Retention


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1 Introduction

2 Opportunities

3 Challenges


5 Summary

1 Introduction

2 Opportunities

3 Challenges


5 Summary


IBM Research


Memory Landscape


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FRAM

Array Efficiency

Write energy/bit [pJ]

Write time [ns]

Maximum Voltage Requirement

Cross Point

MOSFET Select

Data Signal

Storage Element

Multi-bits [bits/cell]

Retention [years]

Endurance

Erase energy/bit

Read energy/bit [pJ]

Erase time [ns]

Read Access [ns]

Embedded Integration [Masks]

Cell Size [F2]

Single Bit Signal Size

Cost

Pow

erB

asicR

eliabilityP

erformance

65%*

2.8

4

200

10

3

2

20@120C

1E12

n/a

75

n/a

10

2

>1000x

Reference

* Array Efficiency = 65% is typical of single level production NAND today.

34%

~15

n/a

500

50

3

V=Q/C

Capacitor

?

10

1E13

n/a

500

n/a

50

2-4

150 [mV]

FRAM

�Low voltage, low current operations

�Fast read/write for most applications

�Over writable without erase

Cell size and scaling

Single bit storage

Destructive read

Material and integration issues

128Mbit demonstrated, 4Mbit in production

No break through insight, a niche player though.


IBM Research


MRAM (Spin-Torque Transfer)

Array Efficiency


Write time [ns]


Cross Point

MOSFET Select

Data Signal

Storage Element


Retention [years]

Endurance

Erase energy/bit


Erase time [ns]

Read Access [ns]


Cell Size [F2]


Cost

Pow

erB

asicR

eliabilityP

erformance

65%*

2.8

4

200

10

3

2

20@120C

1E12

n/a

75

n/a

10

2

>1000x

Reference

�Low voltage operations

�Best read/write performance


�High endurance (need verification)

�Scales favorably

Single bit storage

Small data signal ratio

Bipolar high write operation

Material and integration issues

Potential for Instant-On computing, non-volatile cache applications. Needs a lot more development.

>50%

16

?

>500

<10

3

R

MTJ

?

10

>1E15 ?

n/a

>75

n/a

<10

4

~50%

MRAM


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RRAM (Metal Oxides)

Array Efficiency


Write time [ns]


Cross Point

MOSFET Select

Data Signal

Storage Element


Retention [years]

Endurance

Erase energy/bit


Erase time [ns]

Read Access [ns]


Cell Size [F2]


Cost

Pow

erB

asicR

eliabilityP

erformance

65%*

2.8

4

200

10

3

2

20@120C

1E12

n/a

75

n/a

10

2

1000x

Reference

�Fast read/write performance


�Multi-bit capability

�Possible unipolar write

Low Yield

Low endurance

64Mb array announced

Must solve yield issues.

>33%

~20

4

>500

>100

3

R

MTJ

>1

10

1E6

n/a

>75

n/a

>10

4

>100

RRAM


IBM Research


PRAM

Array Efficiency


Write time [ns]


Cross Point

MOSFET Select

Data Signal

Storage Element


Retention [years]

Endurance

Erase energy/bit


Erase time [ns]

Read Access [ns]


Cell Size [F2]

Single Bit Signal Size [Rratio]

Cost

Pow

erB

asicR

eliabilityP

erformance

65%*

2.8

4

200

10

3

2

20@120C

1E12

n/a

75

n/a

10

2

>1000

Reference

�Low voltage operations

�Fast enough read/write for most applications

�Multi-bit storage

�Compatible material

High reset current (but scalable)

Data reliability concerns with multi-bit storage

512Mb engineering samples available, 1Gb in the work

30%-65%

16

5

~500

100

2.5-3

R

Phase

>1

10@120C

1E12

n/a

~100

n/a

~20

2-5

>10

PCRAM


IBM Research


Face Change for Phase Change

Source: Bianlian.JPG Yongxinge, Wikimedia Commons 9/27/2007.

Phase Change Memory is the most probable choice for SCM.


IBM Research


Phase Change Materials

GST

GeSb

Nucleation dominated

Growth dominated

Large dynamic range storage parameter, tailorable performance.


IBM Research


Published Programming (Reset) Current Data

130nm

90nm

65nm

45nm

32nm

22nm

47332316118

Technology Node

<- Memory Element CD, nm

Structure A

Structure B

Structure C

Structure D


IBM Research


Sub-Lithographic Feature of Memory Element

� The reset current required to melt the minimum volume of memory material at a given technology node determines the size of the access device, thus the memory cell size.

� Sub-lithographic features generally inherit the same lithographic tolerance from the original features before shrink.


IBM Research


Access Device Scaling

�Considerations

�Ease of Process Integration

�Memory Array Efficiency

�Multi-bit Capability

./Fr FET lCylindrica-Semi

.FHW FET Gate-Tri

.Element Memory of ratio iclithograph-sub

and

Element Memory of area section-cross the is

)F(a

where

AaI

A/nm1 isdensity current FET

cm/A isdensity current BJT

sAssumption

Si

SiSi

.reset

2

2

102

2

750

27

===

=

=

=

×

−

α

α

µµ


IBM Research


Reliability Issues

� Composition drift leads to set and reset resistance drifts with cycling.

� Extensive memory array data and intensive modeling required to understand cause and statistics of anomalous cells.

� Resistance drift will limit the number of multi-bit storage.

Ielmini et al, IEEE TED v.54 p.308 2007

Resistance DriftComposition Drift

Rajendran et al, Sym VLSI Tech 2008 Mantegazza et al, IEEE LED v.54 p.308 2007

Anomalous Cells


IBM Research


Challenge in Memory Cell Reliability Modeling

�Reset operation in Phase Change Memory is a chaotic operation very much similar to rolling the dice

�Detailed understanding of the reset process can lead to solutions to data retention (resistance drift) and endurance issues associated with Phase Change Memory

a_GST with a medium size voidJ.Akola et al, PR B 76 2007BlueGene


IBM Research


PCM for SCM Development Time Line

High Performance SSD: 16/32GB SLC/MLC BEOL Diode AccessMain Memory: 8GB 4-bit MLC 3D Transistor Access

...


IBM Research


storage class memory: opportunities and...

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