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Stellaris® FamilyDevelopment Board

USER ’S MANUAL

2 February 6, 2007

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Stellaris® Family Development Board User’s Manual

Revision HistoryThis table provides a summary of the document revisions.

Date Revision Description

March 2006 00 Initial release of doc to customers.

May 2006 01 Release of DB48 daughterboard and documentation.

May 2006 02 Added missing DB48 schematics to board manual PDF.

July 2006 03 Switched DB48 Layout 1 and Layout 2 figures so most current board is first.

Added QEI text to Headers paragraph in Chapter 1.

February 2007 04 Release of revision 3 of motherboard, which adds two headers: JP34 and JP35.

February 6, 2007 3

4 February 6, 2007


Table of ContentsChapter 1: Stellaris® Family Development Board ......................................................................................... 9Features.............................................................................................................................................................. 9Block Diagram .................................................................................................................................................. 10Functional Description ...................................................................................................................................... 11

Daughterboard .............................................................................................................................................. 11UART ............................................................................................................................................................ 11Headers ........................................................................................................................................................ 11Potentiometer................................................................................................................................................ 11Photocell ....................................................................................................................................................... 11User LEDs..................................................................................................................................................... 11User Pushbutton ........................................................................................................................................... 11JTAG Debug Connector................................................................................................................................ 12USB Debug ................................................................................................................................................... 12I2C EEPROM Memory.................................................................................................................................. 12SPI Flash Memory ........................................................................................................................................ 12Buzzer........................................................................................................................................................... 12Real-Time Clock ........................................................................................................................................... 12External Reset .............................................................................................................................................. 12Prototype Area .............................................................................................................................................. 12Peripheral Device Controller (PDC) .............................................................................................................. 12Power Supply................................................................................................................................................ 13Motherboard Layout...................................................................................................................................... 13

Development Board Configuration.................................................................................................................... 14Daughterboard Installation............................................................................................................................ 14UART ............................................................................................................................................................ 14SPI Port (On-Board Peripherals) .................................................................................................................. 14I2C Port ......................................................................................................................................................... 14Buzzer........................................................................................................................................................... 14LCD Panel, DIP Switch, LEDs, and GPIOs .................................................................................................. 14User Pushbutton ........................................................................................................................................... 15User LEDs..................................................................................................................................................... 15Photocell ....................................................................................................................................................... 15Potentiometer................................................................................................................................................ 15JTAG Debug Connector................................................................................................................................ 15USB Debug ................................................................................................................................................... 1532.768-KHz Clock Oscillator ......................................................................................................................... 15Reset Switch ................................................................................................................................................. 16GPIO Headers .............................................................................................................................................. 16Power............................................................................................................................................................ 16

Peripheral Device Controller (PDC).................................................................................................................. 16Stellaris Microcontroller to PDC Interface ..................................................................................................... 17PDC I/O......................................................................................................................................................... 17PDC Registers .............................................................................................................................................. 18

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SPI Protocol .................................................................................................................................................. 19

Chapter 2: DB28 Daughterboard ................................................................................................................... 21Features............................................................................................................................................................ 21Block Diagram .................................................................................................................................................. 21Daughterboard Interface................................................................................................................................... 21Daughterboard Layout ...................................................................................................................................... 22Shunt Jumper ................................................................................................................................................... 23Development Board Signal Usage.................................................................................................................... 24

Chapter 3: DB48 Daughterboard ................................................................................................................... 27Features............................................................................................................................................................ 27Block Diagram .................................................................................................................................................. 27Daughterboard Interface................................................................................................................................... 27Daughterboard Layout ...................................................................................................................................... 28Shunt Jumpers.................................................................................................................................................. 30Development Board Signal Usage.................................................................................................................... 31

Appendix A: Contact Information ................................................................................................................. 35Appendix B: Schematics................................................................................................................................ 37

6 February 6, 2007


February 6, 2007 7

List of FiguresFigure 1-1. Stellaris® Family Development Board Block Diagram .................................................................. 10Figure 1-2. Stellaris Family Motherboard Layout ............................................................................................ 13Figure 1-3. PDC Timing Diagrams................................................................................................................... 20Figure 2-1. DB28 Daughterboard Block Diagram ............................................................................................ 21Figure 2-2. DB28 Daughterboard Layout......................................................................................................... 23Figure 3-1. DB48 Daughterboard Block Diagram ............................................................................................ 27Figure 3-2. DB48 Daughterboard Layout 1 (R3).............................................................................................. 29Figure 3-3. DB48 Daughterboard Layout 2 (R2).............................................................................................. 30

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List of TablesTable 1-1. Possible Board Power Sources..................................................................................................... 16Table 1-2. Stellaris Microcontroller to PDC Interface ..................................................................................... 17Table 1-3. Peripheral to PDC Interface .......................................................................................................... 17Table 1-4. PDC Registers............................................................................................................................... 18Table 2-1. DB28 Daughterboard Interface ..................................................................................................... 22Table 2-2. Jumper Settings for DB28 Daughterboard .................................................................................... 23Table 2-3. Development Board Signals Used by DB28 Daughterboard......................................................... 24Table 3-1. DB48 Daughterboard Interface ..................................................................................................... 28Table 3-2. Jumper Settings for DB48 Daughterboard .................................................................................... 30Table 3-3. Development Board Signals Used by DB48 Daughterboard......................................................... 31

C H A P T E R 1

Stellaris® Family Development BoardThe Stellaris® Family Development Board provides a platform for product development. Hardware and software engineers use this board for evaluation of Stellaris™ family microcontroller features and functionality, and for software development.

The development board includes the Stellaris motherboard and a daughterboard with a Stellaris family microcontroller. The DB28 daughterboard is available for 28-pin SOIC devices, and the DB48 daughterboard is available for 48-pin LQFP devices. These daughterboards are described in Chapter 2, “DB28 Daughterboard” on page 21 and Chapter 3, “DB48 Daughterboard” on page 27.

FeaturesThe Stellaris® Family Development Board includes the following features. Note that not all features are implemented on all Stellaris microcontrollers.

Daughterboards enable support for multiple package/pin-out options

Two UART transceivers and DB9 male connectors

All I/O available on headers

One potentiometer and one photocell for driving the Analog-to-Digital Converter (ADC) and comparator inputs

Eight user LEDs and one pushbutton for use with the Stellaris GPIOs

Standard ARM® 20-pin JTAG debug connector

USB 2.0 full speed interface allows JTAG/SWD debug without in-circuit emulator (ICE)

8-Kbit I2C EEPROM memory

1-Mbit SPI-based flash memory

One buzzer for PWM use

32.768-KHz oscillator for real-time clock

External reset switch and power-on reset supervisor

5-V and 3.3-V LED power indicators

User-prototype area

Peripheral Device Controller (PDC) CPLD for interface with the following:

– 16 character by 2-line LCD display

– 8 status LEDs

– 8-position dual-inline package (DIP) switch

– 24 GPIOs

February 6, 2007 9

Stellaris® Family Development Board

Block DiagramFigure 1-1. Stellaris® Family Development Board Block Diagram

Connectors

RESET

JTAG

3.3 V Regulator

PDC

EEPROMI2C BusPAPBPCPDPE

Port Headers

SPI Bus

Flash

UART0

UART1

User LEDs

User Pushbutton

ADC[0/2/4/6]

C0+/C1+/C2+

GPIOXGPIOYGPIOZ

DIP Switch

LCD Panel LEDs

GPIOs

Buzzer

ADC[1/3/5/7]

C0-/C1-/C2-

Stellaris

Daughterboard

Motherboard

Photocell

PotentiometerUSB

ExpansionHeaders

10 February 6, 2007


Functional DescriptionDaughterboard

The daughterboard contains the Stellaris microcontroller and connects to the motherboard with four 21-pin connectors. The Stellaris PLL clock is generated from a 6-MHz crystal provided on pin sockets for easy crystal changes. An optional SMA connector can be used to drive an external clock source.

UARTTwo UART transceivers and DB9 connectors are provided to connect with the Stellaris microcontroller UART peripherals. The UART0 peripheral (TX, RX) is included in all Stellaris microcontrollers; UART1 is available in all 48-pin microcontrollers except the LM3S301. On the LM3S101, LM3S102 and LM3S301, UART1 is available for external use.

HeadersAll Stellaris I/O signals are available on five 8-pin GPIO headers labeled Port A through Port E to match the Stellaris microcontroller GPIO ports. For each port header, pin 1 is bit 0 and pin 8 is bit 7 of the corresponding Stellaris GPIO. For example, Port B pin 1 is PB0 and Port B pin 8 is PB7 of the Stellaris microcontroller. Note that ports A and E have only six I/O signals, with the remaining two header pins connected to ground. Jumper shunts are used to connect Stellaris signals to on-board devices to allow connect/disconnect. Stellaris signals can be rewired with the included fly-wires.

There are also two 20-pin expansion headers (J9 and J22). Header J9 is intended primarily as an interface for a motor driver board, and includes all the Stellaris PWM outputs, QEI inputs, analog comparator inputs, and three ADC inputs. Header J22 has the remaining Stellaris signals, and includes UART, SSI, I2C, JTAG, and timer CCP input signals.

NOTE: PWM, QEI, ADC, I2C, and analog comparators are available on select Stellaris microcontrollers.

PotentiometerOne potentiometer is included to drive selected Analog-to-Digital Converter (ADC) inputs and/or analog comparator inputs. The voltage range is 0 to 3.0. Shunt headers are used for signal selection.

NOTE: ADC and analog comparators are available on select Stellaris microcontrollers.

PhotocellOne photocell is included to drive selected ADC inputs and/or analog comparator inputs. The voltage range is 0 to 3.0. Shunt headers are used for signal selection.


User LEDsEight user LEDs (ULED0-ULED7) are provided for general use. Headers are provided for connectivity.

User PushbuttonOne user pushbutton (SW3) is provided for general use. A header is provided for connectivity.

February 6, 2007 11


JTAG Debug ConnectorA standard 20-pin connector for JTAG debug is provided. This port is also used to access the Serial-Wire Debug (SWD) interface of the Stellaris microcontroller. When using this connector, the USB interface cannot be used for JTAG/SWD debug (USB can still be used for providing board power). A shunt jumper at location JP31 may be required when using this port.

USB DebugA USB 2.0 full-speed interface provides debug capability via JTAG or SWD without the need for an ICE. Note that use of this interface requires installation of the corresponding USB drivers. When using this interface, the 20-pin JTAG connector cannot be used for JTAG/SWD debug. Ensure that no shunt jumper is present at location JP31.

I2C EEPROM MemoryAn 8-Kbit I2C memory is included for use with the Inter-Integrated Circuit (I2C) bus interface. A jumper block is provided for connecting this memory.

NOTE: The I2C interface is available on select Stellaris microcontrollers.

SPI Flash MemoryA 1-Mbit SPI flash memory is included for use with the Serial Port Interface (SPI) port. A jumper block is provided for connecting this memory.

BuzzerA buzzer is provided for use with one of the PWM outputs.

Real-Time ClockA 32.768-KHz crystal oscillator generates a clock signal that can be used to drive the Stellaris real-time clock. Shunt jumpers on the daughterboard can be used to connect this clock source.

External ResetThe external reset is implemented with a reset switch SW2 connected to a reset supervisor circuit, and provides a system reset signal.

Prototype AreaA prototype area is provided for implementing user circuits. To supply power, there are power and ground rows. The prototype area is indicated on the board with a Luminary Micro logo (see Figure 1-2 on page 13).

Peripheral Device Controller (PDC)A Peripheral Device Controller (PDC) implemented with a CPLD is accessible via the SPI interface and provides access to several devices including a 16-character by 2-line LCD display, an 8-bit DIP switch, 8 general-purpose user LEDs, and 24 GPIOs.

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Power SupplyThe Stellaris® Family Development Board requires 5 volts at 500 mA for operation, and three options are provided for supply connection.

1. A USB connector can be used when connected to a high-power (500-mA) USB hub port.

2. A 5-V jack can be used with an external power supply.

3. A terminal block can be wired to a 5-V external bench supply.

A slide switch selects between USB power and the other two options (see Figure 1-2 on page 13). Table 1-1 on page 16 describes how to select the power supply.

Motherboard LayoutThe Stellaris™ family motherboard layout is shown in Figure 1-2. The gray squares show the location of pin 1 for all connectors and headers. (On the board silk-screen, white arrows indicate pin 1.) There are four ground test loops: TL1-TL4. TL5 is 5.0 V, and TL6 is 3.3 V.

NOTE: Two motherboard revisions are in production, Rev 2 and Rev 3. The revision is marked in the lower left corner of the board, as indicated in the figure. The only functional difference between these revisions is the addition in Rev 3 of headers JP34 and JP35 next to the GPIOZ headers to allow source selection for signals IDX (PD7 or PB2) and FAULT (PD6 or PB3). JP34 and JP35 are highlighted in the figure with a red box.

Figure 1-2. Stellaris Family Motherboard Layout

J1

J2

J3

J4

P2P1

J17

J14

SW2

R25

JP9

JP8

JP7

JP6

JP18

JP16

JP15

JP17

J9

J22

J15

PortA PortB PortC

PortD PortE Spare GPIOX GPIOY

GPIOZ

J21

J11

JP2JP3

JP4JP5

JP1JP11 JP12

JP13JP14 SCL

SDA

WP

JP19

BZ1JP21

JP26JP20

J20TL4

J18

S1

J19

POT1R3

SW3

ULED7

SW1

LED 7 JP30

LED 0 ULED 0JP22

GND

3.3V

5.0V

3.3V

R5

JP10JP

31JP

34JP

35

REV 3

NOTE: The gray squares indicate the location of pin 1 for all connectors and headers.

February 6, 2007 13


Development Board ConfigurationNOTE: In the descriptions that follow, reference designators are used to indicate locations on the

board layout (as shown in Figure 1-2). In addition, reference designators in parenthesis refer to parts in the schematics in Appendix B, “Schematics.

Daughterboard InstallationThe daughterboard connects to the motherboard header connectors J1-J4. With no power applied to the motherboard, place the daughterboard and align each connector of the motherboard with the corresponding daughterboard connector. Press the daughterboard down until the daughterboard is firmly seated, and visually inspect all four connectors to ensure proper connection before proceeding.

UARTTo connect the UART0 transceiver, connect shunt jumpers on headers JP6 and JP7. To connect UART1, connect shunt jumpers on headers JP8 and JP9.

SPI Port (On-Board Peripherals)To connect the Serial Peripheral Interface port, which is used to communicate with the PDC and the on-board flash memory, connect shunt jumpers to pins 1-2 of headers JP15, JP16, JP17, and JP18. To write-protect the SPI flash memory, place a shunt jumper on JP10.

NOTE: The Stellaris microcontroller’s SSI port can be programmed for one of three serial modes: Freescale SPI, National Semiconductor MICROWIRE™, or Texas Instruments synchronous serial. (The mode is set with the FRF bit in the SSI Control0 (SSICR0) register.) The Stellaris Family Development Board is designed for use with SPI mode although MICROWIRE and TI synchronous serial modes can be used when implementing user circuits in the prototype area. SPI mode must be set to use the board’s LCD, DIP switch, LEDs, and GPIOX, GPIOY, and GPIOZ ports.

I2C PortTo connect the I2C port for access to the on-board EEPROM, place shunt jumpers on JP13 and JP14. To write-protect the EEPROM memory, place a shunt jumper on JP12. Address line A2 for the EEPROM memory can be set to 0 by placing a shunt jumper on JP11. Removing the jumper sets A2 to 1.

NOTE: The I2C interface is available on select Stellaris microcontrollers.

BuzzerTo enable the buzzer BZ1, connect a shunt jumper to JP21. To connect the buzzer power driver to the Stellaris microcontroller PB0 port, place a shunt jumper on JP26. To use a different port to drive the buzzer, remove the shunt at JP26 and connect a fly-wire from the desired port to JP26-2.

LCD Panel, DIP Switch, LEDs, and GPIOsTo use the LCD panel, DIP switch, LEDs LED0-LED7 (D1-D8), and the GPIOs, the SPI port must be connected as described above. The SPI port connects to the PDC to control these devices.

The potentiometer R25 is used to adjust the contrast of the LCD panel. The LCD panel, DIP switch, LEDs, and GPIOs are controlled with the PDC registers (see Table 1-4 on page 18).

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User PushbuttonPushbutton SW3 is available for general use. To connect this switch to PB4, place a shunt jumper on JP19. To use a different port, remove shunt at JP19 and connect a fly-wire from the desired port to JP19-2.

User LEDsUser LEDs ULED0-ULED7 (D9, D10, D12, D13-D17) are available for general use. Each user LED has an associated header for connection to a Stellaris GPIO, PDC GPIO, or external circuitry.

To connect a user LED to its associated Stellaris GPIO, place a shunt jumper on the corresponding header (ULED0-ULED3 => PB0-PB3, ULED4-ULED7 => PD0-PD3). To use a different port, remove the shunt jumper from the header and connect a fly-wire from the desired port to pin 2 of the header.

PhotocellPhotocell R3 can be used to provide an analog signal to drive the ADC (analog-to-digital converter) and the analog comparator using headers JP2 (ADC0,ADC2,ADC4,ADC6) => (PE5,PE3,PD7,PD5), and JP3 (C0+,C1+,C2+) => (PB6,PC5,PC6). To connect the photocell to an ADC channel, place a shunt jumper on the corresponding JP2 header. To connect the photocell to a comparator channel, place a shunt jumper on the corresponding JP3 header.


PotentiometerPotentiometer R5 can be used to provide an analog signal to drive the ADC (analog-to-digital converter) and the analog comparator using headers JP4 (ADC1,ADC3,ADC5,ADC7) => (PE4,PE2,PD6,PD4), and JP5 (C0-,C1-,C2-) => (PB4,PB5,PC7). To connect the potentiometer to an ADC channel, place a shunt jumper on the corresponding JP4 header. To connect the potentiometer to a comparator channel, place a shunt jumper on the corresponding JP5 header.


JTAG Debug ConnectorFor JTAG debug with an external ICE, connect the ICE to connector J14 with a standard 20-pin JTAG debug cable. To link the motherboard reset to the JTAG emulator reset, place a shunt jumper on JP20. Depending on the ICE, a shunt jumper at location JP31 may be required if a USB driver conflict occurs.

USB DebugFor debug with USB, connect the USB cable to the USB device connector. Ensure that no shunt jumper is present at location JP31. Note that a corresponding USB driver must be installed on the host computer. The USB driver selects the mode of operation by controlling the USB_MOD signal from the FTDI part (ADBUS7). If USB_MOD is 1, JTAG mode is selected. If USB_MOD is 0, SWD mode is selected. JTAG/SWD signals are driven to the Stellaris microcontroller when the USB driver sets USB_DEN (ADBUS6) to 0.

32.768-KHz Clock OscillatorAn on-board 32.768-KHz oscillator can be used to drive the Stellaris real-time clock. To enable this oscillator, remove the shunt jumper on JP1. To disable the oscillator output, place a shunt jumper on JP1.

February 6, 2007 15


Reset SwitchReset switch SW2 generates a 140-ms (minimum) system reset signal. Powering up the board also generates a 140-ms system reset signal. A shunt jumper can be placed on JP20 to link the JTAG emulator reset with the system reset.

GPIO HeadersAll Stellaris GPIO ports are available on 8-pin headers labeled PortA (J5), PortB (J6), PortC (J7), PortD (J10), and PortE (J12). The 20-pin headers J9 and J22 include all the GPIOs and provide a convenient connection for expansion to another board. The 8-pin headers labeled GPIOX (J26), GPIOY (J27), and GPIOZ (J16) provide a connection to the GPIOs implemented in the PDC.

PowerThree options are available for board power, and only one should be connected to the board. These are described in Table 1-1. The two power indicators light once there is power to the board.

Peripheral Device Controller (PDC)The PDC provides access to a common set of peripherals across all Stellaris microcontrollers, since they all include an SSI port. The Stellaris SSI port is used in SPI mode for communications with the PDC. The PDC operates at 1 MHz.

Table 1-1. Possible Board Power Sources

Power Source Configuration

USB high-power hub (500 mA) Slide switch S1 towards the board edge. Connect a USB cable from the USB hub to the USB-B receptacle J18. Slide switch S1 towards the board center to turn on power.

5-V (500-mA) supply with 2.5-mm plug Slide switch S1 towards the center of the board. Connect a 5-V supply with a 2.5-mm plug to jack J19. Slide switch S1 towards the board edge to turn on power.

5-V (500-mA) bench supply Slide switch S1 towards the center of the board. Connect a 5-V supply with two wires to terminal block J21. Connect the 5-V wire to J21-1 (5V) and the ground wire to J21-2 (GND). Slide switch S1 towards the board edge to turn on power.

J21

5V GND

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Stellaris Microcontroller to PDC InterfaceThe Stellaris microcontroller connects to the PDC with a SPI port using the signals shown in Table 1-2.

PDC I/OThe PDC connects to supported peripherals with the following signals:

Table 1-2. Stellaris Microcontroller to PDC Interface

Board Signal Direction Description

SPI_CLK Input SPI clock signal, 1 MHz.

SPI_SEL Input SPI select signal, set high to enable SPI transfers. Set to low for reset of the PDC (minimum 200 nanoseconds). Note that with SPI_SEL low the SPI flash at location U3 is selected.

SPI_MOSI Input Master output, slave input data transfer signal.

SPI_MISO Output Master input, slave output data transfer signal.

Table 1-3. Peripheral to PDC Interface

Board Signal Direction Description

L_RS Out LCD register select

L_RW Out LCD read/write

L_CEN Out LCD chip enable

L_BLIGHT Out LCD backlight

LD[7:0] InOut LCD data bus

LED[7:0] Out LED select outputs

DSW[7:0] In DIP switch inputs

GPIOX_[7:0] InOut GPIOX I/O ports

GPIOY_[7:0] InOut GPIOY I/O ports

GPIOZ_[7:0] InOut GPIOZ I/O ports

February 6, 2007 17


PDC RegistersPDC registers are 8 bits, and there are three types: Read-Only (RO), Read/Write (R/W), and Read/Write delayed (RWD). A RWD transaction requires an additional dummy transfer due to peripheral device latency.

Table 1-4. PDC Registers

Register Address Type Description

VERSION 0x0 R0 The VERSION register contains the version of the PDC design programmed in the CPLD.

CSR 0x1 R/W The Command/Status (CSR) register is used to set special configuration options and read device status. Unused bits are reserved and should be written to 0. The following bits are defined:

Bit0 - LCBL: The LCD backlight bit controls the LCD panel backlight. Setting this bit to 1 turns on the LCD backlight. Setting this bit to 0 turns off the LCD backlight.

Bit7 - LCBSY: The LCD busy bit reflects the value of the LCD panel busy flag. When this bit is 1, the LCD panel is busy processing a command. When this bit is 0, a new command can be written to the LCD panel.

DIPSW 0x4 R0 The DIP Switch (DIPSW) register contains the value of the debug DIP switch at location SW1. Bit i corresponds to switch i+1. A switch in the OFF position is read as 0. A switch in the ON position is read as 1.

LED 0x5 R/W The LED Output (LED) register controls LED0-LED7. Bit i controls LEDi. Writing a bit to 1 turns on the corresponding LED. Writing a bit to 0 turns off the corresponding LED.

LCDCSR 0x6 RWD The LCD Command/Status (LCDCSR) register is used to write configuration and control commands and to read status information from the LCD panel. For more information, refer to the CFAH1602B LCD panel data sheet (available from www.crystalfontz.com).

LCDRAM 0x7 RWD The LCD RAM (LCDRAM) register is used to write and read the LCD display data RAM (DDRAM) and the character generator RAM (CGRAM). For more information, refer to the CFAH1602B LCD panel data sheet (available from www.crystalfontz.com).

GPXDAT 0x8 R/W The GPIOX Data (GPXDAT) register is used to access the general-purpose I/O port GPIOX at location J26. Bit i corresponds with the GPIOX_i port signal. Each bit can be configured for input or output in the GPXDIR register.

Writing a bit to 1 sets the corresponding GPIOX port signal to 1 if the port signal is configured as an output. Writing a bit to 0 sets the corresponding GPIOX port signal to 0 if the port signal is configured as an output.

Reading a bit reads the value of the corresponding GPIOX port signal. If the GPIOX port is 0, the bit will read as 0. If the GPIOX port signal is 1, the bit will read as 1. Note that a read of the GPXDAT register always reads the GPIOX port signals, not the internal register.

18 February 6, 2007


SPI ProtocolThe SPI slave interface is enabled when SPI_SEL goes High. All SPI commands and data are received via the SPI_MOSI input signal, with data sampled on the rising edge of the SPI clock. All SPI output data is transmitted on the SPI_MISO output signal, with data shifted out on the falling edge of the SPI clock. Set SPI_SEL Low for 200 nanoseconds to reset the PDC.

GPXDIR 0x9 R/W The GPIOX Direction (GPXDIR) register is used to select the data transfer direction for the GPXDAT register. Bit i corresponds to GPXDAT bit i. Writing a bit to 1 sets the corresponding GPXDAT bit as an output port. Writing a bit to 0 sets the corresponding GPXDAT bit as an input port.

GPYDAT 0xA R/W The GPIOY Data (GPYDAT) register is used to access the general-purpose I/O port GPIOY at location J27. Bit i corresponds with the GPIOY_i port signal. Each bit can be configured for input or output in the GPYDIR register.

Writing a bit to 1 sets the corresponding GPIOY port signal to 1 if the port signal is configured as an output. Writing a bit to 0 sets the corresponding GPIOY port signal to 0 if the port signal is configured as an output.

Reading a bit reads the value of the corresponding GPIOY port signal. If the GPIOY port is 0, the bit will read as 0. If the GPIOY port signal is 1, the bit will read as 1. Note that a read of the GPYDAT register always reads the GPIOY port signals, not the internal register.

GPYDIR 0xB R/W The GPIOY Direction (GPYDIR) register is used to select the data transfer direction for the GPYDAT register. Bit i corresponds with GPYDAT bit i. Writing a bit to 1 sets the corresponding GPYDAT bit as an output port. Writing a bit to 0 sets the corresponding GPYDAT bit as an input port.

GPZDAT 0xC R/W The GPIOZ Data (GPZDAT) register is used to access the general-purpose I/O port GPIOZ at location J16. Bit i corresponds with the GPIOZ_i port signal. Each bit can be configured for input or output in the GPZDIR register.

Writing a bit to 1 sets the corresponding GPIOZ port signal to 1 if the port signal is configured as an output. Writing a bit to 0 sets the corresponding GPIOZ port signal to 0 if the port signal is configured as an output.

Reading a bit reads the value of the corresponding GPIOZ port signal. If the GPIOZ port is 0, the bit will read as 0. If the GPIOZ port signal is 1, the bit will read as 1. Note that a read of the GPZDAT register always reads the GPIOZ port signals, not the internal register.

GPZDIR 0xD R/W The GPIOZ Direction (GPZDIR) register is used to select the data transfer direction for the GPZDAT register. Bit i corresponds with GPZDAT bit i. Writing a bit to 1 sets the corresponding GPZDAT bit as an output port. Writing a bit to 0 sets the corresponding GPZDAT bit as an input port.

Table 1-4. PDC Registers

Register Address Type Description

February 6, 2007 19


Every transaction is composed of at least two 8-bit SPI transfers. The first byte contains a 4-bit address on the lower bits (bits 3:0) and a read/write (R/W) bit to indicate transfer direction on the most significant bit (bit 7). The remaining bits (bits 6:4) are reserved and must be 0. The next byte is driven by the Stellaris microcontroller for write transfers (R/W bit=0), and by the PDC for read transfers (R/W bit=1). For read transfers to LCD registers, a dummy byte follows the first byte, with a valid data byte afterwards. Timing diagrams are shown in Figure 1-3.

Figure 1-3. PDC Timing Diagrams

PDC Read Transfer

D0D1D7 D2D3D6 D5 D4

LCD Read Transfer

017 236 5 4

SPI_SEL

SPI_CLK

SPI_MOSI

SPI_MISO

Dummy Byte

PDC/LCD Write Transfer

A0A1RW A2A30 0 0

A0A1RW A2A30 0 0

A0A1RW A2A30 0 0

D0D1D7 D2D3D6 D5 D4

D0D1D7 D2D3D6 D5 D4

SPI_SEL

SPI_CLK

SPI_MOSI

SPI_MISO

SPI_SEL

SPI_CLK

SPI_MOSI

SPI_MISO

20 February 6, 2007

C H A P T E R 2

DB28 DaughterboardThe DB28 daughterboard contains a 28-pin SOIC Stellaris microcontroller and connects to the motherboard with four 21-pin connectors.

NOTE: In the descriptions that follow, reference designators are used to indicate locations on the board layout (as shown in Figure 2-2 on page 23). In addition, reference designators in parenthesis refer to parts in the schematics in Appendix B, “Schematics.

FeaturesDesigned for 28-pin SOIC Stellaris microcontroller

6-MHz crystal mounted on pin sockets for easy crystal changes

SMA connector for external clock

Power and ground test loops

Jumper-selectable 32.768-KHz clock

All daughterboard connector signals accessible via headers on the daughterboard

Block DiagramFigure 2-1. DB28 Daughterboard Block Diagram

Daughterboard InterfaceThe DB28 daughterboard connects to the motherboard with four connectors: J1-J4 (see Figure 1-2 on page 13). Table 2-1 on page 22 lists the connections.

ConnectorsJP1

Stellaris

February 6, 2007 21

DB28 Daughterboard

Daughterboard LayoutThe DB28 daughterboard layout is shown in Figure 2-2 on page 23. A single Stellaris microcontroller is soldered at location U1. There are four ground test loops: TL1, TL4, TL5, and TL7. TL2 is connected to the LDO pin and TL3 is connected to VDD. The gray squares show the location of pin 1 for each connector. Note that TL6 and pin 1 of J2 and J4 are 3.3 V. A clock signal can be applied to SMA connector J6 after removing crystal Y1.

Table 2-1. DB28 Daughterboard Interface

Pin J1 J2 J3 J4

1 GND 3.3V 3.3V

2 GND

3

4

5 XPB1

6 PB0

7 CLK32K

8 GND

9 PB2

10 PB3

11 5V

12 RSTn

13 PA2

14 PA5

15 PA4

16 PC3/TDO PA3

17

18 PC0/TCK PB6

19 PC1/TMS PB5 PA0

20 PC2/TDI PB4 PA1

21 PB7/TRST GND GND

22 February 6, 2007


Figure 2-2. DB28 Daughterboard Layout

Shunt JumperThere is a single shunt jumper JP1 (see Figure 2-2) used for selecting the connection of port B1 (PB1) as shown in Table 2-2.

Table 2-2. Jumper Settings for DB28 Daughterboard

Shunt Description

No shunt PB1 is unconnected

Shunt 1-2 PB1 is connected to 32.768-KHz clock

Shunt 2-3 PB1 is connected to daughterboard connector J4-5 (XPB1)

Y1

J6

J1

J2

J3

J4

TL4

GND

TL1

GND

3.3V 3.3V

JP1

GND

TL7TL5

GND

TL6

3.3V

LDO

TL2

VDD

TL3

U2

U1

NOTE: The gray squares indicate the location of pin 1.

February 6, 2007 23

DB28 Daughterboard

Development Board Signal UsageTable 2-3 shows the signal connectivity and usage between the DB28 daughterboard and the motherboard. For the jumpers column, the numbers in brackets show the jumper position.

Table 2-3. Development Board Signals Used by DB28 Daughterboard

Stellaris Signal

DB28 Daughterboard Connection

MotherboardJumpers

Motherboard Signal Description

PA0 J4-19 JP7-[1][2] U0_RX Serial port 0 receive

PA1 J4-20 JP6-[1][2] U0_TX Serial port 0 transmit

PA2 J4-13 JP15-[2][1] SPI_CLK Serial peripheral interface clock

PA3 J4-16 JP18-[2][1] SPI_SEL Serial peripheral interface select

PA4 J4-15 JP17-[2][1] SPI_MISO Serial peripheral interface master-in/slave-out

PA5 J4-14 JP16-[2][1] SPI_MOSI Serial peripheral interface master-out/slave-in

PB0 J4-6JP26[1][2] PWM Buzzer signal

JP22[1][2] ULED0 User LED

PB1JP1-[2][1] (J3-7) CLK32K 32.768-KHz clock

JP1-[2][3] (J4-5) JP23-[1][2] ULED1 User LED

PB2 J4-9J4-9 I2C_SCL I2C clock signal to EEPROM


PB3 J4-10J4-10 I2C_SDA I2C data signal to EEPROM


PB4 J3-20 JP5-[2][1] C0- Connects to 10k potentiometer


PB6 J3-18 JP3-[2][1] C0+ Connects to photocell

PB7 J1-21 J14-3 TRST JTAG signal, used by emulator

PC0 J1-18 J14-9 TCK JTAG signal, used by emulator

PC1 J1-19 J14-7 TMS JTAG signal, used by emulator

PC2 J1-20 J14-5 TDI JTAG signal, used by emulator

PC3 J1-16 J14-13 TDO JTAG signal, used by emulator

RST J1-12 SYSRST_B Connects to reset supervisor

OSC0 J7, C4 Connects to pin socket and capacitor for crystal

OSC1 J8, C5 Connects to pin socket and capacitor for crystal

VDD-(U1)

TL6, J2-1, J4-1 3.3V Connects to 3.3-V plane

24 February 6, 2007


GND J1-1, J2-21

J3-8, J4-21

GND Connects to ground plane

LDO Connects to 1.3 microfarad capacitor and to test loop 2


Stellaris Signal


MotherboardJumpers


February 6, 2007 25

DB28 Daughterboard

26 February 6, 2007

C H A P T E R 3

DB48 DaughterboardThe DB48 daughterboard contains a 48-pin LQFP Stellaris microcontroller and connects to the motherboard with four 21-pin connectors.

NOTE: In the descriptions that follow, reference designators are used to indicate locations on the board layout (as shown in Figure 3-2 on page 29 and Figure 3-3 on page 30). In addition, reference designators in parenthesis refer to parts in the schematics in Appendix B, “Schematics.

FeaturesDesigned for 48-pin LQFP Stellaris microcontroller

6-MHz crystal mounted on pin sockets for easy crystal changes

SMA connector for external clock

Power and ground test loops

Jumper-selectable 32.768-KHz clock

All daughterboard connector signals accessible via headers on the daughterboard

Block DiagramFigure 3-1. DB48 Daughterboard Block Diagram

Daughterboard InterfaceThe DB48 daughterboard connects to the motherboard with four connectors: J1-J4 (see Figure 1-2 on page 13). Table 3-1 on page 28 lists the connections.

Connectors

JP3

Stellaris

JP2 JP1

February 6, 2007 27

DB48 Daughterboard

Daughterboard LayoutThere are two different layouts of the DB48 daughterboard. Layout 1 shown on Figure 3-2 on page 29 has the Stellaris microcontroller soldered at U1 on the center of the board. Layout 2 shown on Figure 3-3 on page 30 has the Stellaris microcontroller soldered at location U1 on the left side of the board.

Both layouts include four ground test loops: TL1-TL4 in Layout 1 and TL1, TL4, TL5, and TL7 in Layout 2. TL6 in Layout 1 and TL2 in Layout 2 are connected to the LDO pin. The gray squares show the location of pin 1 for each connector. Note that TL5 in Layout 1 and TL6 in Layout 2 as well as pin 1 of J2 and J4 are 3.3 V. A clock signal can be applied to SMA connector J6 after removing crystal Y1.

Table 3-1. DB48 Daughterboard Interface

Pin J1 J2 J3 J4

1 GND 3.3V 3.3V

2 PD7V GND

3 PC4 PE5

4 PC6 PE4

5 XPB1

6 PB0

7 CLK32K XPE2

8 GND

9 PB2

10 PD5 PB3

11 5V PE3

12 RSTn PD4

13 PA2

14 PA5

15 PE1 PA4

16 PC3/TDO PE0 XPC7 PA3

17 PD6 PD2

18 PC0/TCK PB6 PD3

19 PC1/TMS PD1 PB5 PA0

20 PC2/TDI PD0 PB4 PA1

21 PB7/TRST GND PC5 GND

28 February 6, 2007


Figure 3-2. DB48 Daughterboard Layout 1 (R3)


J1

J2

J3

J4

TL1

GND

3.3V 3.3V

TL5U1

J6

Y1

TL6

LDO GND

TL2

JP1JP2 JP3

TL4

GND

TL3

GND

3.3V

February 6, 2007 29

DB48 Daughterboard

Figure 3-3. DB48 Daughterboard Layout 2 (R2)

Shunt JumpersThere are three shunt jumpers for connection of a 32.768-KHz clock as shown in Table 3-2.

Table 3-2. Jumper Settings for DB48 Daughterboard

Jumper Shunt Description

JP1 No shunt PB1 is unconnected

Shunt 1-2 PB1 is connected to 32.768-KHz clock.

Shunt 2-3 PB1 is connected to daughterboard connector J4-5 (XPB1)

JP2 No shunt PC7 is unconnected

Shunt 1-2 PC7 is connected to 32.768-KHz clock.

Shunt 2-3 PC7 is connected to daughterboard connector J4-5 (XPC7)

JP3 No shunt PE2 is unconnected

Shunt 1-2 PE2 is connected to 32.768-KHz clock.

Shunt 2-3 PE2 is connected to daughterboard connector J4-5 (XPE2)

Y1

J6

J1

J2

J3

J4 U1

TL4

GND

TL1

GND

3.3V 3.3V

JP1JP2JP3

GND

TL7TL5

GND

TL6

3.3V

LDO

TL2

VDD

TL3

U1U2


30 February 6, 2007


Development Board Signal UsageTable 3-3 shows the signal connectivity and usage between the DB48 daughterboard and the motherboard. For the jumpers column, the numbers in brackets show the jumper position.


StellarisSignal


MotherboardJumpers


PA0 J4-19 JP7-[1][2] U0_RX Serial port 0 receive

PA1 J4-20 JP6-[1][2] U0_TX Serial port 0 transmit

PA2 J4-13 JP15-[2][1] SPI_CLK Serial peripheral interface clock

PA3 J4-16 JP18-[2][1] SPI_SEL Serial peripheral interface select

PA4 J4-15 JP17-[2][1] SPI_MISO Serial peripheral interface master-in/slave-out

PA5 J4-14 JP16-[2][1] SPI_MOSI Serial peripheral interface master-out/slave-in

PB0 J4-6JP26-[1][2] PWM Buzzer signal

JP22-[1][2] ULED0 User LED

PB1JP1-[2][1] (J3-7) CLK32K 32.768-KHz clock

JP1-[2][3] (J4-5) JP23-[1][2] ULED1 User LED

PB2 J4-9

JP14-[1][2] I2C_SCL I2C clock signal to EEPROM


JP34-[2][3]a IDX Motor index signal

PB3 J4-10

JP13-[1][2] I2C_SDA I2C data signal to EEPROM


JP35-[2][3]a FAULT Motor fault signal



PB6 J3-18 JP3-[2][1] C0+ Connects to photocell

PB7 J1-21 J14-3 TRST JTAG signal, used by emulator

PC0 J1-18 J14-9 TCK JTAG signal, used by emulator

PC1 J1-19 J14-7 TMS JTAG signal, used by emulator

PC2 J1-20 J14-5 TDI JTAG signal, used by emulator

PC3 J1-16 J14-13 TDO JTAG signal, used by emulator

PC4 J1-3 PC4 Not used

PC5 J3-21 JP3-[4][3] C1+ Connects to photocell

PC6 J1-4 JP3-[6][5] C2+ Connects to photocell

February 6, 2007 31

DB48 Daughterboard

PC7JP2-[2][1] (J3-7) JP5-[6][5] C2- 32.768-KHz clock

JP2-[2][3] (J3-16)

JP5-[6][5] C2- Connects to 10k potentiometer

PD0 J2-20 JP27-[1][2] ULED4 User LED

PD1 J2-19 JP28-[1][2] ULED5 User LED

PD2 J4-17JP9-[1][2] U1_RX Serial port 1 receive


PD3 J4-18JP8-[1][2] U1_TX Serial port 1 transmit


PD4 J2-12 JP4-[8][7] ADC7 Connects to 10k potentiometer

PD5 J2-10 JP2-[8][7] ADC6 Connects to photocell

PD6 J3-17 JP4-[6][5] ADC5 Connects to 10k potentiometer

JP35-[1][2]a FAULT Motor fault signal

PD7 J1-2 JP2-[6][5] ADC4 Connects to photocell

JP34-[1][2]a IDX Motor index signal

PE0 J2-16 PE0 Not used

PE1 J2-15 PE1 Not used

PE2JP3-[2][1] (J3-7) CLK32K 32.768-KHz clock

JP3-[2][3] (J4-7) JP4-[4][3] ADC3 Connects to 10k potentiometer

PE3 J2-11 JP2-[4][3] ADC2 Connects to photocell

PE4 J2-4 JP4-[2][1] ADC1 Connects to 10k potentiometer

PE5 J2-3 JP2-[2][1] ADC0 Connects to photocell

RST J1-12 SYSRST_B Connects to reset supervisor

OSC0 J7,C4 Connects to pin socket and capacitor for crystal

OSC1 J8,C5 Connects to pin socket and capacitor for crystal

VDD-(U1)

TL5 (Layout 1), TL6 (Layout 2), J2-1, J4-1

3.3V Connects to 3.3-V plane

GND J1-1,J2-21

J3-8,J4-21

GND Connects to ground plane


StellarisSignal


MotherboardJumpers


32 February 6, 2007


LDO Connects to 1.3 microfarad capacitor and to test loop 2

a. Jumpers 34 and 35 are only available on Rev3 or later boards.


StellarisSignal


MotherboardJumpers


February 6, 2007 33

DB48 Daughterboard

34 February 6, 2007

A P P E N D I X A

Contact Information

Company InformationFounded in 2004, Luminary Micro, Inc. designs, markets, and sells ARM Cortex-M3-based microcontrollers (MCUs). Austin, Texas-based Luminary Micro is the lead partner for the Cortex-M3 processor, delivering the world's first silicon implementation of the Cortex-M3 processor. Luminary Micro's introduction of the Stellaris® family of products provides 32-bit performance for the same price as current 8- and 16-bit microcontroller designs. With entry-level pricing at $1.00 for an ARM technology-based MCU, Luminary Micro's Stellaris product line allows for standardization that eliminates future architectural upgrades or software tool changes.

Luminary Micro, Inc.108 Wild Basin, Suite 350Austin, TX 78746Main: +1-512-279-8800Fax: +1-512-279-8879http://[email protected]

Support InformationFor support on Luminary Micro products, contact:

[email protected]+1-512-279-8800, ext. 3

February 6, 2007 35

36 February 6, 2007

A P P E N D I X B

SchematicsSchematics for the development board follow:

Stellaris Motherboard on page 39

DB28 Daughterboard on page 46

DB48 Daughterboard Layout 1 (board revision R3) on page 48

DB48 Daughterboard Layout 2 (board revision R2) on page 50

February 6, 2007 37

38 February 6, 2007

6

6

DescriptionPage

7 USB to JTAG / SWD

1

1

2

2

D D

C C

B B

A A

Document Number: Rev

SheetDate: of2/5/2007 1 7

R3

This document contains information proprietary to Luminary Micro, Inc. and shall not be used forengineering design, procurement of manufacture in whole or in part without the express writtenpermission of Luminary Micro, Inc. Copyright © 2007 Luminary Micro, Inc. All rights reserved.

108 Wild Basin Rd.Two Wild Basin Suite 350Austin, TX 78746

Luminary Micro, Inc.

Designer:

Drawn by:

Approved:

Drawing Title:

Page Title:

Size

Arnaldo Cruz

Arnaldo Cruz

* 0001

Stellaris Development Board

Table of Contents

C

Table of Contents / Revision Control1

Table of Contents

2

3 Board Connectors, GPIO, JTAG

Block Diagram

UART, SPI, I2C

Reset, Power

PDC, LCD Display, LEDs, DIP Switch

4

5

6

1

1

2

2

3

3

4

4

5

5

6

6

D D

C C

B B

A A



R3

Drawing Title:

Page Title:

SizeC

Block Diagram


0001

JTAG

SYSTEMReset

3.3V Regulator

Board Connectors

FLASH1Mbit

PORT0

LEDS [7:0]

SMA

32kHzOscillator

UARTXVER

I2CEEPROM 8kbit

J1, J2, J3, J4

Photocell

Potentiometer

Jumper blockADC[0/2/4/6]C0+/C1+/C2+

Jumper blockADC[1/3/5/7]C0-/C1-/C2-

Port HeadersPA[5:0]PB[7:0]PC[7:0]PD[7:0]PE[5:0]

PDC (Peripheral Device Controller)

GPIO Port HeadersGPIOX[7:0]GPIOY[7:0]GPIOZ[7:0]

LCD panel 16 char x 2 rows

DIP Switch [7:0]

User LEDS

User Pushbutton

Buzzer

Expansion Headers

I2C BUS

SPI BUS

JUMPERBLOCK

USB JTAG / SWD

JUMPERBLOCK

JUMPERBLOCK

JUMPERBLOCK

PORT1

JUMPERBLOCK

JUMPERBLOCK

JUMPERBLOCK

UARTXVER

1

1

2

2

3

3

4

4

5

5

6

6

D D

C C

B B

A A



R3

Drawing Title:

Page Title:

SizeC

Board Connectors, GPIO, JTAG


0001

3.3vA

CLK32KCLK32K

PA0PA1PA2PA3PA4PA5

PB0PB1PB2PB3PB4PB5PB6PB7

PC0PC1PC2PC3PC4PC5PC6PC7

PD0PD1PD2PD3PD4PD5PD6PD7

PE0PE1PE2PE3PE4PE5

PE5

PB6PC5PC6

PD0PD1PB0

PE4PE2PD6PD4

PB4PB5PC7

PB1PE0PE1

PC0PC1

SRST_B

PB7

PC3

DBGRQ

RTCK

PC2

POT

PC4PC6PD7X

PB4PB5PB6

PC5PC7

PD4

PD5PD6X

PCELL

DBGACK

PA0PA1PA2PA3PA4PA5PB2PB3PB7

PC0PC1PC2PC3PD2PD3PE2PE3PE4PE5

SYSRST_B

PD7PD5

PE3

C660.1uF

POT1

R510K

21FB1

39ohm @ 100 MHz

1 23 45 6

87

ADCJP4

2x4 HDR

1 23 45 6

JP3

2x3 HDR

12345678

PortE

J121X8HDR

1 23 45 6

JP5

2x3 HDR

12

32kEN

JP1

1x2 HDR

R1 22.1

12345678

PortA

J51X8HDR

123456789101112131415161718192021

J3

1X21HDR

123456789

101112131415161718192021

J4

1X21HDR

R910K

23

1

DNP

J11

SMA

Vcc 4

E/D1 OUT 3

GND2

U1

32.768KHz

R4511

1 23 45 6

87

ADCJP2

2x4 HDR

1 23 45 67 89 10

11 1213 1415 1617 1819 20

PWM/QEI/ADC/CMP

J9

2X10 HDR

PHOTOCELL

R3PHOTOCELL-P8102

R1110K

+

16VTANT

C110uF

R212.7K

C650.1uF

R1210K

R6610K

R710K

123456789101112131415161718192021

J1

1X21HDR

12345678

PortD

J101X8HDR

R7710K

R610K

R810K

12345678

PortC

J71X8HDR

1 23 45 67 89 10

11 1213 1415 1617 1819 20

JTAG

J14

2X10 HDR-SHRD

12345678

PortB

J61X8HDR

+

16VTANT

C310uF

R1010K

C60.1uF

+

16VTANT

C210uF

1 23 45 67 89 10

11 1213 1415 1617 1819 20

SERIAL/CCP

J22

2X10 HDR

123456789101112131415161718192021

J2

1X21HDR

3.3v 3.3v

5v

3.3v

3.3v

3.3v

3.3v 5v

3.3v

3.3v

3.3v

3.3v

3.3v

PWM0PWM1PWM2PWM3PWM4PWM5

ChAChBIDX

C0+C1+C2+

C0-C1-C2-

TRSTTDITMSTCK

TDO

RSTn

U0_RXU0_TXSSI_CLKSSI_FSSSSI_RXSSI_TX

M_CH_AM_CH_B

M_INDEX

PWM2PWM3I2CSCLI2CSDAC0-C1-C0+

TRSTTDITMSTCK

TDO

TRST

TCKTMSTDITDOChA

ChBC2-

C0o/C1+

PWM0PWM1U1_RXU1_TXCCP0CCP2FaultIDX

PWM4PWM5CCP4CCP1CCP3CCP5

C1+C2-

C0-C1-C0+

ADC7

ADC6ADC5

U0_RXU0_TXSSI_CLKSSI_FSSSSI_RXSSI_TX

TRST

I2CSCLI2CSDA

TCKTMSTDITDOU1_RXU1_TXCCP4CCP1CCP3CCP5

Board Connectors

0246

1357

123

IDX

JP34

1X3HDR

123

FAULT

JP35

1X3HDR

PD7

PB2

PD6

PB3

SYSRST_BDBGACK

DBGRQSRST_BPC3

RTCKPC0PC1PC2PB7

PB1PB0PE2

PB2PB3

PA2PA5PA4PA3PD2PD3PA0PA1

PC5PB4PB5PB6PD6PC7

PD7PC4PC6

PE5PE4

PD5PE3PD4

PE1PE0

PD1PD0

TILE_48

SRST_B

SMA_32k

Note: JP34 and JP35 are present only on the REV 3 board. Previous board versions have signal PD7 directly connected to J9-6 and signal PD6 directly connected to J9-14.

1

1

2

2

3

3

4

4

5

5

6

6

D D

C C

B B

A A



R3

Drawing Title:

Page Title:

SizeC

UART/SPI/I2C


0001

U0_TX

C_RXD0

C_TXD0

C_TXD1

C_RXD1

U0_RX

U1_RX

U1_TX

I2C_SDA

I2C_SCL

C9

0.47uF

1 2

U0_RXJP7

1x2 HDR

R1410K

1 2I2C_SCLJP14

1x2 HDR

C8

0.47uF

R1910K

C120.1uF

VCC 19

C2+5

C2-6

C1+2

C1-4

INVALID 11

V+ 3

V- 7

T1IN13 T1OUT 17

GND18

R1OUT15 R1IN 16

READY 1

T2OUT 8T2IN12

R2OUT10 R2IN 9

FORCEON14

FORCEOFF20

U2

MAX3224

CS1

SO2

WP3

GND4 SI 5SCK 6HOLD 7VCC 81MbitU3

AT25F1024AN

A01

A12

A23

GND4 SDA 5SCL 6WP 7VCC 8

8Kbits

U4

AT24C08A

R202.80K

R18330

TP1

R212.80K

R1510K

12I2CM_A2

JP11

1x2 HDR

C130.1uF

R1310K

R1610K

R6810K

C10

0.47uF

12

I2CM_WPJP12

1x2 HDR

C7

0.47uF

R6710K

C11 0.47uF

594837261

1011

SER1

P2DB9_M

1 2

U0_TXJP6

1x2 HDR

R1710K

12SPIM_WP

JP10

1x2 HDR

TP2

1 2

U1_TXJP8

1x2 HDR

1 2I2C_SDAJP13

1x2 HDR

1 2

U1_RXJP9

1x2 HDR

594837261

1011

SER0

P1DB9_M

3.3v

3.3v

3.3v

3.3v

3.3v

3.3v

3.3v

3.3v

3.3v

PA1

PA0

PD3

PD2

SPI_SEL

SPI_MOSISPI_CLK

PB3

PB2

SPI_MISO

1

1

2

2

3

3

4

4

5

5

6

6

D D

C C

B B

A A



R3

Drawing Title:

Page Title:

SizeC

PDC, LCD Display, LEDs, DIP Switch


0001

DSW0

DSW4DSW3DSW2

DSW7DSW6

DSW1

DSW5

LD0LD1LD2LD3LD4LD5LD6LD7

L_CONTRAST

CPLD_TDICPLD_TDO

DSW1DSW2DSW3DSW4

DSW5DSW6DSW7

DSW0

LED0LED1LED2LED3

LED4LED5

LED6LED7

LD0LD1

LD2LD3LD4LD5

LD6LD7

L_RSL_RWL_CEnL_BLIGHT

CLK_20M

GPIOZ_6

GPIOZ_4GPIOZ_5

SPARE_7SPARE_6SPARE_5SPARE_4SPARE_3SPARE_2SPARE_1SPARE_0

TEST

GPIOX_0GPIOX_1GPIOX_2GPIOX_3GPIOX_4GPIOX_5GPIOX_6GPIOX_7

GPIOY_0GPIOY_1GPIOY_2GPIOY_3GPIOY_4GPIOY_5GPIOY_6GPIOY_7

CPLD_TCK

CPLD_TDI

CPLD_TMS

CPLD_TDO

GPIOZ_7

GPIOZ_0

GPIOZ_3GPIOZ_2GPIOZ_1

CPLD_TMS

CPLD_TCK

123SPI_SEL

JP18

1X3HDR

VCC 35

VCC 90

TDI33

TCK28

TMS26

TDO31

GND84

VIO_0 60

VIO_0 74

VIO_1 10

VIO_1 24

GND40

GND_112

GND_125

GND_142

GND_062

GND_075

GND_093 VIO_0 92

VIO_1 41

PL2A1

PL2B2

PL3A3

PL3B4

PL3C5

PL3D6

PL4A7

PL4B8

PL5A9

PL5B11

PL5C13

PL5D/GSRN14

PL6A15

PL6B/TSALL16

PL7A17

PL7B18

PL7C19

PL7D20

PL8A21

PL8B22

PL9A23

PL9B27

PB2A 29

PB2B 30

PB2C 32

PB2D 34

PB3A/CLK1_1 36

PB3B 37

PB3C/CLK1_0 38

PB3D 39

PB4A 43

PB4B 44

PB4C 45

PB4D 46

PB5A 47

PB5C 49

PB5D 50

PR2A 76

PR2B 73

PR3A 72

PR3B 71

PR3C 70

PR3D 69

PR4A 68

PR4B 67

PR5A 66

PR5B 65

PR5C 64

PR5D 63

PR6A 61

PR6B 59

PR7A 58

PR7B 57

PR7C 56

PR7D 55

PR8A 54

PR8B 53

PR9A 52

PR9B 51

SLEEPN48

VAUX 88

PT2A100

PT2B99

PT2C98

PT2D97

PT2E96

PT2F95

PT3A94

PT3B91

PT3C89

PT3D87

PT4A/CLK0_086

PT4B/CLK0_185

PT4C83

PT4D82

PT4E81

PT4F80

PT5A79

PT5B78

PT5C77

U10

LCMXO256-T100C

R73

330

R45

10K

1

23

Q2MMBT3904

C210.1uF

U5

LCD Display 16x2

R31 330

12345678

GPIOY

J27

1X8HDR

OE1

GND2 VDD 4

OUT 3U7

20.000MHZ 3.3V

R72 2.80K

C150.1uF

R39

10K

12TEST

J25

1x2 HDR

123456789

10111213141516

J15

1X16HDR

C170.1uF

TP10

R22 40.2

R24 330

2 1

LED6

D7

GREEN LED

ON

18

12345678 9

10111213141516

DEBUGSW1

SW DIP-8 Rocker

C190.1uF

12345678

SPARE

J23

1X8HDR

R32 330C140.1uF

12CPLD_SLEEP

J24

1x2 HDR

R40

10K

123SPI_CLK

JP15

1X3HDR

R44

10K

R7610K

2 1

LED7

D8

GREEN LED

R42

10K

C310.1uF

R7410K

12345678

GPIOZ

J16

1X8HDR

R7110K

R276.8K

R6910K

C290.1uF

12345678

GPIOX

J26

1X8HDR

2 1

LED0

D1

GREEN LED

R37 330

123SPI_MOSI

JP16

1X3HDR

R6510K

R38

10K

C160.1uF

R364.75K

R7010K

C280.1uF

R28 330

1220MHz_OE

J20

1x2 HDR

R30 330

12345678

CPLD_JTAG

J17

1X8HDR

R3510K

R3410K

C300.1uF

C180.1uF

2 1

LED3

D4

GREEN LED

123SPI_MISO

JP17

1X3HDR

2 1

LED2

D3

GREEN LED

TP8 2 1

LED4

D5

GREEN LED

2 1

LED1

D2

GREEN LED

R41

10K

R263.18K

R29 330

CONTRAST

R2510K

DNP

R75330

C200.1uF

R43

10K

R23 330

2 1

LED5

D6

GREEN LED

R3310K

PA5

PA2

PA3

PC1PC2

3.3v

5v5v

3.3v

3.3v

3.3v

3.3v

3.3v

3.3v

3.3v

PDC

PA4

TILE_48

SYSRST_B

USB_MOD

SPI_MOSI

SPI_MISO

SPI_CLK

SPI_SEL

USB_DENFT_DIFT_DOFT_CS

PC3

LD[7

..0]

DS

W[7

..0]

1

1

2

2

3

3

4

4

5

5

6

6

D D

C C

B B

A A



R3

Drawing Title:

Page Title:

SizeC

Power, Reset


0001

1 4

2 3USER

SW3

R56 2.80K

100 Mil Mask

FID840 Mil Pad

+

16VTANT

C2422uF

R48 330

MR3 VCC 4

GND1 RESET 2

U8

MAX6386

C220.1uF

2 1

ULED6

D16

GREEN LED

C250.1uF

12USER_PBJP19

1x2 HDR

2 1

ULED0

D9

GREEN LED

R62 82.5K

R58 330

R5033.2

2 1

ULED1

D10

GREEN LED

1 2ULED1JP23

1x2 HDR

GNDTL1

12D21

1N5819

R63330

R64137K

5.0VTL5

C26470 pF

R59 330

1 2

PWM

JP26

1x2 HDR

R51 330

GNDTL2R47

10K

C230.1uF

100 Mil Mask

FID140 Mil Pad

1 2

LINK_SRST

JP20

1x2 HDR

1 4

2 3

SYSRST

SW2

21

3.3V

D19GREEN LED

2 1

ULED7

D17

GREEN LED

R49511

100 Mil Mask

FID540 Mil Pad

R60511

GNDTL3

R54 330

1

23

Q1MMBT3904

21

3

S1

1101M2S3CQE2

12

5.0V

GND

J21

Term_Block_V_2pos

R5582.5K

100 Mil Mask

FID240 Mil Pad

2 1

ULED2

D12

GREEN LED

1 2ULED4JP27

1x2 HDR

GNDTL4

R6110K

3.3VTL6

1235.0V

J19

RAPC722

100 Mil Mask

FID640 Mil Pad

R4610K

2 1

ULED4

D14

GREEN LED

R52 330

1 2ULED5JP28

1x2 HDR

+

16VTANT

C2722uF

100 Mil Mask

FID340 Mil Pad

2 1

ULED5

D15

GREEN LED

1 2ULED6JP29

1x2 HDR

21

PWM_LED

D11GREEN LED

1 2

PWM_BuzzerJP21

1x2 HDR

12D20

1N5819

2 1

ULED3

D13

GREEN LED

1 2ULED2JP24

1x2 HDR

100 Mil Mask

FID740 Mil Pad

VIN2 VOUT 4

GN

D3

TAB

TAB

EN1 ADJ 5

U9 MIC5209

R57 330

1 2ULED7JP30

1x2 HDR

21

5.0V

D18GREEN LED

1 2ULED3JP25

1x2 HDR

+

-2

1

BZ1

BUZZER CEM-1206S

R53 330

1 2ULED0JP22

1x2 HDR

100 Mil Mask

FID440 Mil Pad

PB0

PB0

PB1

PD0

PD1

PD2

PD3

PB2

PB3

3.3v

3.3v

3.3v5v

5v

USB_5v

Fiducials

Notes: 1. Power provided by external 5v DC supply or USB port, as selected by switch 2. Use of USB power requires a high power port (500mA).

SRST_B

SYSRST_B

PB4

1

1

2

2

3

3

4

4

5

5

6

6

D D

C C

B B

A A



R3

Drawing Title:

Page Title:

SizeC

USB to JTAG / SWD


0001

TP14

C370.1uF

R9110K

TP19

R92 0

TP26

CS 1

SK 2

DI 3

DO 4GND5 NC6 DC7 VCC8

1K 64X16

U12

AT93C46A-10SI-2.7

TP16

R8410K

C380.1uF

TP21

TP27

C350.1uF

TP13

C360.1uF

C340.1uF

TP15

R83 2.21K

TP18

C390.1uF

R9410K

TP22

R811.50K

R80 27

TP23

C3218pF

TP29

21FB2

39ohm @ 100 MHz

C3318pF

R8510K

R82 475

TP11TP12

R9320K

R8610K

GND18

GND25

GND34

ADBUS0 24

ADBUS1 23

ADBUS2 22

ADBUS3 21

ADBUS4 20

ADBUS5 19

ADBUS6 17

ADBUS7 16

ACBUS0 15

ACBUS1 13

ACBUS2 12

ACBUS3 11

BDBUS0 40

BDBUS1 39

BDBUS2 38

BDBUS3 37

BDBUS4 36

BDBUS5 35

BDBUS6 33

BDBUS7 32

BCBUS0 30

BCBUS1 29

BCBUS2 28

BCBUS3 27

SI/WUA 10

SI/WUB 26

GND9

AGND45

VCC 3

VCC 42

VCCIOA 14

VCCIOB 31

AVCC 46

PWREN# 41

XTOUT44 XTIN43

EECS48

EESK1

EEDATA2

TEST47

RESET#4

RSTOUT#5

3V3OUT6

USBDM8

USBDP7

U11

FT2232C

TP24

VD-

D+ G

SGND

SGND

3 2 4 1

5 6

USB

J18 USB_B

TP20

TP25

12

USB_OFF

JP31

1x2 HDR

R9510K

1 2Y1

6.000MHz

R87 0

21FB3

39ohm @ 100 MHz

R79 27

R88 0

PC3

3.3v

USB_5v

3.3v

5vUSB_5v

5v

TCK/SKTDI/DOTDO/DITMS/CS

SWO

FT_DOFT_DIFT_CS

USB_DENUSB_MOD

PC0

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Drawing Title:

Size Document Number Rev

Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:

Luminary Micro, Inc.2499 S. Capital of Texas HwyAustin, TX 78746

This document contains information proprietary to Luminary Micro Inc. and shall not be used forengineering design, procurement or manufacture in whole or in part without the express writtenpermission of Luminary Micro, Inc. Copyright © 2005 Luminary Micro, Inc. All rights reserved.

0001 R2

Stellaris DB28 Daughterboard

C

Saturday, March 18, 2006

Table of Contents

Arnaldo Cruz

<Approver>

Arnaldo Cruz

1 2

Drawing Title:


Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:



0001 R2


C


Table of Contents

Arnaldo Cruz

<Approver>

Arnaldo Cruz

1 2

Drawing Title:


Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:



0001 R2


C


Table of Contents

Arnaldo Cruz

<Approver>

Arnaldo Cruz

1 2


Table of Contents

2 LM3S1XX, Socket, Connectors

DescriptionPage

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LDOLDOLDOLDO

OSC0OSC1

PB2PB3

PA2PA5PA4PA3

PA0

PC0

PC2

PC3

PC1

PB7

PA1

PC0

PB3

PB0

PA4

PB7

RSTnLDO

OSC0OSC1PA0

PB6PB5PB4

PA1PA2PA3

PA5

PB1

PB2

PC1PC2PC3

PB4PB5PB6

PB0XPB1

CLK32K

RSTn

PA0PA1PA2PA3PA4

PC0PC1PC2PC3

PA5


RSTn3.3v

3.3v 3.3v

3.3v

5v

3.3v

3.3v

Drawing Title:


Date: Sheet of

Page Title:

0001 R2


C


LM3S1XX, Socket, Connectors

2 2

Drawing Title:


Date: Sheet of

Page Title:

0001 R2


C



2 2

Drawing Title:


Date: Sheet of

Page Title:

0001 R2


C



2 2

Fiducials

TRSTTDITMSTCK

TDO

FID240 Mil Pad

100 Mil Mask

FID240 Mil Pad

100 Mil Mask

TL63.3vTL63.3v

1J8

9548

J8

9548

C60.1uFC60.1uF

C718pF50V10%

C718pF50V10%

PA0/U0Rx11PA1/U0Tx12PA2/SSIClk13PA3/SSIFss14PA4/SSIRx15PA5/SSITx16

VDD 7VDD 17VDD 22

GND8GND18GND21

RST5 LDO 6

OSC09OSC110

PC0/TCK/SWCLK28PC1/TMS/SWDIO27PC2/TDI26PC3/TDO/SWO25

PB0/CCP0 19PB1/32KHz 20

PB2/I2CSCL 23PB3/I2CSDA 24

PB4/C0- 4PB5/C1-/C0o 3

PB6/C0+/CCP1 2PB7/TRST 1

U1

LM3S1XX_SOP28

U1

LM3S1XX_SOP28

123456789101112131415161718192021J1

21x1 SKT

J1

21x1 SKT

FID440 Mil Pad

100 Mil Mask

FID440 Mil Pad

100 Mil Mask

C110.1uFC110.1uF

TL4GNDTL4GND

1 2Y1

6.000MHz

Y1

6.000MHz

123456789101112131415161718192021

J3

21x1 SKT

J3

21x1 SKT

TL3VDDTL3VDD

R10.1 Ohm0.5%

R10.1 Ohm0.5%

C121uFC121uF

TL1GNDTL1GND

123456789

101112131415161718192021

J4

21x1 SKT

J4

21x1 SKT

23

1J6

SMA

J6

SMA

C100.1uFC100.1uF

C50.1uFC50.1uF

FID140 Mil Pad

100 Mil Mask

FID140 Mil Pad

100 Mil Mask

123456789101112131415161718192021

J2

21x1 SKT

J2

21x1 SKT

+ C210uF

16VTANT

+ C210uF

16VTANT

TL2LDOTL2LDO

FID340 Mil Pad

100 Mil Mask

FID340 Mil Pad

100 Mil Mask

1J7

9548

J7

9548

P11P22P33P44P55P66P77P88P99P1010P1111P1212P1313P1414

P25 25P26 26P27 27P28 28

P15 15P16 16P17 17P18 18P19 19P20 20P21 21P22 22P23 23P24 24

SOP28

U2

SOCKET_SOP28DNP

SOP28

U2

SOCKET_SOP28DNP

123

JP11X3HDR

PB1_MUX

JP11X3HDR

PB1_MUX

TL7GNDTL7GND

R2 22.11%

R2 22.11%

C40.1uFC40.1uF

+ C110uF

16VTANT

+ C110uF

16VTANT

C818pF50V10%

C818pF50V10%

C90.1uFC90.1uF

C130.33uF16V10%

C130.33uF16V10%

TL5GNDTL5GND

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Drawing Title:


Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:



0001 R3


C

Thursday, May 18, 2006

Table of Contents

Arnaldo Cruz

<Approver>

Arnaldo Cruz

1 2

Drawing Title:


Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:



0001 R3


C


Table of Contents

Arnaldo Cruz

<Approver>

Arnaldo Cruz

1 2

Drawing Title:


Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:



0001 R3


C


Table of Contents

Arnaldo Cruz

<Approver>

Arnaldo Cruz

1 2


Table of Contents

2 LM3SXXX, Connectors

DescriptionPage

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

OSC0OSC1

PB2PB3

PA2PA5PA4PA3

XPB1

PD2PD3PA0

PD5PE3PD4

PE5

PE1

PE4

PE0

PD1

PC0

PC2

PC3

PC1

PB7

PA1

PD7PC4

PD0

PC6

PB0

PC5

PB6PB5PB4

XPC7PD6

XPE2

CLK32KCLK32K

PB1XPB1

PE2

PC7

XPE2

XPC7

LDO



PA0PA1PA2PA3PA4PA5


PE0PE1PE2PE3PE4PE5

RSTn

RSTn

3.3v 3.3v

3.3v

5v

3.3v 5v

3.3v

Drawing Title:


Date: Sheet of

Page Title:

0001 R3


C


LM3SXXX, Connectors

2 2

Drawing Title:


Date: Sheet of

Page Title:

0001 R3


C


LM3SXXX, Connectors

2 2

Drawing Title:


Date: Sheet of

Page Title:

0001 R3


C


LM3SXXX, Connectors

2 2

Fiducials

RSTn

TRSTTDITMSTCK

TDO

Located on bottom layer

C180.1 uF

DNP

C180.1 uF

DNP

C150.01 uFC150.01 uF

FID140 Mil Pad

100 Mil Mask

FID140 Mil Pad

100 Mil Mask

123

JP11X3HDR

PB1

JP11X3HDR

PB1

C210.1 uF

DNP

C210.1 uF

DNP

123

JP21X3HDR

PC7

JP21X3HDR

PC7

23

1J6

SMA

J6

SMA

C90.1 uFC90.1 uF

FID240 Mil Pad

100 Mil Mask

FID240 Mil Pad

100 Mil Mask

+ C310uF

16VTANT

+ C310uF

16VTANT

+ C2310uF

16VTANT

DNP

+ C2310uF

16VTANT

DNP

C518pF50V10%

C518pF50V10%

C280.01 uFDNP

C280.01 uFDNP

+ C2210uF

16VTANT

DNP

+ C2210uF

16VTANT

DNP

C120.01 uFC120.01 uF

C241uFDNP

C241uFDNP

C418pF50V10%

C418pF50V10%

TL6LDOTL6LDO

TL3GNDTL3GND

1J8

9548

J8

9548

123456789101112131415161718192021

J3

21x1 SKT

J3

21x1 SKT

R1 22.11%

R1 22.11%

+ C210uF

16VTANT

+ C210uF

16VTANT

C250.33uF16V10%DNP

C250.33uF16V10%DNP

TL1GNDTL1GND


PC0/TCK/SWCLK40PC1/TMS/SWDIO39PC2/TDI38PC3/TDO/SWO37PC4/CCP5/PhA14PC5/C1+/C1o/C0o/CCP113PC6/C2+/C2o/CCP3/PhB12PC7/C2-/CCP411

PD0/PWM0 25PD1/PWM1 26

PD2/U1Rx 27PD3/U1Tx 28

PD4/ADC7/CCP0 45PD5/ADC6/CCP2 46PD6/ADC5/Fault 47

PD7/ADC4/C0o/IDX 48

VDD 7VDD 15VDD 23VDD 32

GND8GND16GND24GND31

RST5 LDO 6

OSC09OSC110

PB0/PWM2/CCP0 29PB1/PWM3/CCP2 30


PB4/C0- 44PB5/C1-/CCP5 43

PB6/C0+ 42PB7/TRST 41

PE0/PWM435PE1/PWM536PE2/ADC3/CCP44PE3/ADC2/CCP13PE4/ADC1/CCP32PE5/ADC0/CCP51

U1

LM3SXXX_QFP48

U1

LM3SXXX_QFP48

C200.1 uF

DNP

C200.1 uF

DNP

TL53.3vTL53.3v

TL4GNDTL4GND

C270.01 uFDNP

C270.01 uFDNP

TL2GNDTL2GND

C61uFC61uF

123456789101112131415161718192021

J2

21x1 SKT

J2

21x1 SKT

1 2Y1

6.000MHz

Y1

6.000MHz

FID340 Mil Pad

100 Mil Mask

FID340 Mil Pad

100 Mil Mask

C190.1 uF

DNP

C190.1 uF

DNP

C140.01 uFC140.01 uF

123456789101112131415161718192021J1

21x1 SKT

J1

21x1 SKT

FID440 Mil Pad

100 Mil Mask

FID440 Mil Pad

100 Mil Mask

+ C110uF

16VTANT

+ C110uF

16VTANT

+ C1610uF

16VTANT

+ C1610uF

16VTANT

C80.1 uFC80.1 uF

C100.1 uFC100.1 uF

C260.01 uFDNP

C260.01 uFDNP

1J7

9548

J7

9548

C130.01 uFC130.01 uF

C70.33uF16V10%

C70.33uF16V10%

+ C1710uF

16VTANT

+ C1710uF

16VTANT

C290.01 uFDNP

C290.01 uFDNP

123

JP31X3HDR

PE2

JP31X3HDR

PE2

C110.1 uFC110.1 uF

123456789

101112131415161718192021

J4

21x1 SKT

J4

21x1 SKT

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Drawing Title:


Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:



0001 R2


C


Table of Contents

Arnaldo Cruz

<Approver>

Arnaldo Cruz

1 2

Drawing Title:


Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:



0001 R2


C


Table of Contents

Arnaldo Cruz

<Approver>

Arnaldo Cruz

1 2

Drawing Title:


Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:



0001 R2


C


Table of Contents

Arnaldo Cruz

<Approver>

Arnaldo Cruz

1 2


Table of Contents

2 LM3SXXX, Socket, Connectors

DescriptionPage

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A AOSC0OSC1

PB2PB3

PA2PA5PA4PA3

XPB1

PD2PD3PA0

PD5PE3PD4

PE5

PE1

PE4

PE0

PD1

PC0

PC2

PC3

PC1

PB7

PA1

PD7PC4

PD0

PC6

PE1PE0PB3PB2

PB1PB0PD3PD2PD1PD0

PE5PE4PE3PE2RSTnLDO

OSC0OSC1PC7PC6

PC5

PC4

PA0

PA1

PA2

PA3

PA4

PA5

PB6

PB7

PC0

PC1

PC2

PC3

PD7

PD6

PD5

PD4

PB4

PB5

LDOLDOLDOLDO

PB0

PC5

PB6PB5PB4

XPC7PD6

XPE2

CLK32KCLK32K

PB1XPB1

PE2

PC7

XPE2

XPC7



PA0PA1PA2PA3PA4PA5


PE0PE1PE2PE3PE4PE5

RSTn

RSTn

3.3v 3.3v

3.3v

5v

3.3v 5v

3.3v

3.3v

Drawing Title:


Date: Sheet of

Page Title:

0001 R2


C


LM3SXXX, Socket, Connectors

2 2

Drawing Title:


Date: Sheet of

Page Title:

0001 R2


C



2 2

Drawing Title:


Date: Sheet of

Page Title:

0001 R2


C



2 2

Fiducials

RSTn

TRSTTDITMSTCK

TDO

FID240 Mil Pad

100 Mil Mask

FID240 Mil Pad

100 Mil Mask

C90.1uFC90.1uF

C418pF50V10%

C418pF50V10%

TL2LDOTL2LDO

1J8

9548

J8

9548

C150.1uFC150.1uF

TL63.3vTL63.3v

123456789101112131415161718192021J1

21x1 SKT

J1

21x1 SKT

C130.1uFC130.1uF

1J7

9548

J7

9548

TL4GNDTL4GND

FID440 Mil Pad

100 Mil Mask

FID440 Mil Pad

100 Mil Mask

1 2Y1

6.000MHz

Y1

6.000MHz

123456789101112131415161718192021

J3

21x1 SKT

J3

21x1 SKT

TL3VDDTL3VDD

TL1GNDTL1GND

C80.1uFC80.1uF

23

1J6

SMA

J6

SMA

123456789

101112131415161718192021

J4

21x1 SKT

J4

21x1 SKT

FID140 Mil Pad

100 Mil Mask

FID140 Mil Pad

100 Mil Mask

123

JP11X3HDR

PB1

JP11X3HDR

PB1

+ C310uF

16VTANT

+ C310uF

16VTANT

C110.1uFC110.1uF

123

JP21X3HDR

PC7

JP21X3HDR

PC7

+ C210uF

16VTANT

+ C210uF

16VTANT


PC0/TCK/SWCLK40PC1/TMS/SWDIO39PC2/TDI38PC3/TDO/SWO37PC4/CCP5/PhA14PC5/C1+/C1o/C0o/CCP113PC6/C2+/C2o/CCP3/PhB12PC7/C2-/CCP411

PD0/PWM0 25PD1/PWM1 26

PD2/U1Rx 27PD3/U1Tx 28

PD4/ADC7/CCP0 45PD5/ADC6/CCP2 46PD6/ADC5/Fault 47

PD7/ADC4/C0o/IDX 48

VDD 7VDD 15VDD 23VDD 32

GND8GND16GND24GND31

RST5 LDO 6

OSC09OSC110

PB0/PWM2/CCP0 29PB1/PWM3/CCP2 30


PB4/C0- 44PB5/C1-/CCP5 43

PB6/C0+ 42PB7/TRST 41

PE0/PWM435PE1/PWM536PE2/ADC3/CCP44PE3/ADC2/CCP13PE4/ADC1/CCP32PE5/ADC0/CCP51

U1

LM3SXXX_QFP48

U1

LM3SXXX_QFP48

123456789101112131415161718192021

J2

21x1 SKT

J2

21x1 SKT

P11P22P33P44P55P66P77P88P99P1010P1111P1212

P13

13P1

414

P15

15P1

616

P17

17P1

818

P19

19P2

020

P21

21P2

222

P23

23P2

424

P25 25P26 26P27 27P28 28P29 29P30 30P31 31P32 32P33 33P34 34P35 35P36 36

P37

37P3

838

P39

39P4

040

P41

41P4

242

P43

43P4

444

P45

45P4

646

P47

47P4

848

QFP48

U2

SOCKET_QFP48DNP

QFP48

U2

SOCKET_QFP48DNP

C140.1uFC140.1uF

C100.1uFC100.1uF

FID340 Mil Pad

100 Mil Mask

FID340 Mil Pad

100 Mil Mask

C70.33uF16V10%

C70.33uF16V10%

123

JP31X3HDR

PE2

JP31X3HDR

PE2

R2 22.11%

R2 22.11%

TL7GNDTL7GND

C518pF50V10%

C518pF50V10%

R10.1 Ohm0.5%

R10.1 Ohm0.5%

+ C110uF

16VTANT

+ C110uF

16VTANT

C61uFC61uF

C120.1uFC120.1uF

TL5GNDTL5GND

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