stellaris lm4f120h5qr microcontroller data sheet …wevans/lm4f120h5qr.pdftableofcontents....

Stellaris LM4F120H5QR Microcontroller

DATA SHEET

Copyr ight 2007-2012Texas Instruments Incorporated

DS-LM4F120H5QR-13200.2535SPMS294D

TEXAS INSTRUMENTS-ADVANCE INFORMATION

CopyrightCopyright 2007-2012 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas InstrumentsIncorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as theproperty of others.

ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specificationsare subject to change without notice.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductorproducts and disclaimers thereto appears at the end of this data sheet.

Texas Instruments Incorporated108 Wild Basin, Suite 350Austin, TX 78746http://www.ti.com/stellarishttp://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

August 29, 20122Texas Instruments-Advance Information

Table of ContentsRevision History ............................................................................................................................. 34About This Document .................................................................................................................... 39Audience .............................................................................................................................................. 39About This Manual ................................................................................................................................ 39Related Documents ............................................................................................................................... 39Documentation Conventions .................................................................................................................. 40

1 Architectural Overview .......................................................................................... 421.1 Stellaris LM4F Series Overview ..................................................................................... 421.2 LM4F120H5QR Microcontroller Overview ....................................................................... 431.3 LM4F120H5QR Microcontroller Features ........................................................................ 461.3.1 ARM Cortex-M4F Processor Core .................................................................................. 461.3.2 On-Chip Memory ........................................................................................................... 481.3.3 Serial Communications Peripherals ................................................................................ 501.3.4 System Integration ........................................................................................................ 541.3.5 Analog .......................................................................................................................... 601.3.6 JTAG and ARM Serial Wire Debug ................................................................................ 621.3.7 Packaging and Temperature .......................................................................................... 621.4 LM4F120H5QR Microcontroller Hardware Details ........................................................... 62

2 The Cortex-M4F Processor ................................................................................... 642.1 Block Diagram .............................................................................................................. 652.2 Overview ...................................................................................................................... 662.2.1 System-Level Interface .................................................................................................. 662.2.2 Integrated Configurable Debug ...................................................................................... 662.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 672.2.4 Cortex-M4F System Component Details ......................................................................... 672.3 Programming Model ...................................................................................................... 682.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 682.3.2 Stacks .......................................................................................................................... 692.3.3 Register Map ................................................................................................................ 692.3.4 Register Descriptions .................................................................................................... 712.3.5 Exceptions and Interrupts .............................................................................................. 872.3.6 Data Types ................................................................................................................... 872.4 Memory Model .............................................................................................................. 872.4.1 Memory Regions, Types and Attributes ........................................................................... 892.4.2 Memory System Ordering of Memory Accesses .............................................................. 902.4.3 Behavior of Memory Accesses ....................................................................................... 902.4.4 Software Ordering of Memory Accesses ......................................................................... 912.4.5 Bit-Banding ................................................................................................................... 922.4.6 Data Storage ................................................................................................................ 942.4.7 Synchronization Primitives ............................................................................................. 952.5 Exception Model ........................................................................................................... 962.5.1 Exception States ........................................................................................................... 972.5.2 Exception Types ............................................................................................................ 972.5.3 Exception Handlers ..................................................................................................... 1012.5.4 Vector Table ................................................................................................................ 101

3August 29, 2012Texas Instruments-Advance Information


2.5.5 Exception Priorities ...................................................................................................... 1022.5.6 Interrupt Priority Grouping ............................................................................................ 1032.5.7 Exception Entry and Return ......................................................................................... 1032.6 Fault Handling ............................................................................................................. 1062.6.1 Fault Types ................................................................................................................. 1072.6.2 Fault Escalation and Hard Faults .................................................................................. 1072.6.3 Fault Status Registers and Fault Address Registers ...................................................... 1082.6.4 Lockup ....................................................................................................................... 1082.7 Power Management .................................................................................................... 1092.7.1 Entering Sleep Modes ................................................................................................. 1092.7.2 Wake Up from Sleep Mode .......................................................................................... 1092.7.3 The Wake-Up Interrupt Controller ................................................................................. 1102.8 Instruction Set Summary .............................................................................................. 110

3 Cortex-M4 Peripherals ......................................................................................... 1173.1 Functional Description ................................................................................................. 1173.1.1 System Timer (SysTick) ............................................................................................... 1183.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................. 1193.1.3 System Control Block (SCB) ........................................................................................ 1203.1.4 Memory Protection Unit (MPU) ..................................................................................... 1203.1.5 Floating-Point Unit (FPU) ............................................................................................. 1253.2 Register Map .............................................................................................................. 1293.3 System Timer (SysTick) Register Descriptions .............................................................. 1323.4 NVIC Register Descriptions .......................................................................................... 1363.5 System Control Block (SCB) Register Descriptions ........................................................ 1513.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 1803.7 Floating-Point Unit (FPU) Register Descriptions ............................................................ 189

4 JTAG Interface ...................................................................................................... 1954.1 Block Diagram ............................................................................................................ 1964.2 Signal Description ....................................................................................................... 1964.3 Functional Description ................................................................................................. 1974.3.1 JTAG Interface Pins ..................................................................................................... 1974.3.2 JTAG TAP Controller ................................................................................................... 1994.3.3 Shift Registers ............................................................................................................ 1994.3.4 Operational Considerations .......................................................................................... 2004.4 Initialization and Configuration ..................................................................................... 2024.5 Register Descriptions .................................................................................................. 2024.5.1 Instruction Register (IR) ............................................................................................... 2034.5.2 Data Registers ............................................................................................................ 205

5 System Control ..................................................................................................... 2075.1 Signal Description ....................................................................................................... 2075.2 Functional Description ................................................................................................. 2075.2.1 Device Identification .................................................................................................... 2075.2.2 Reset Control .............................................................................................................. 2085.2.3 Non-Maskable Interrupt ............................................................................................... 2125.2.4 Power Control ............................................................................................................. 2135.2.5 Clock Control .............................................................................................................. 2145.2.6 System Control ........................................................................................................... 2215.3 Initialization and Configuration ..................................................................................... 224


Table of Contents

5.4 Register Map .............................................................................................................. 2255.5 System Control Register Descriptions ........................................................................... 2295.6 System Control Legacy Register Descriptions ............................................................... 386

6 System Exception Module ................................................................................... 4436.1 Functional Description ................................................................................................. 4436.2 Register Map .............................................................................................................. 4436.3 Register Descriptions .................................................................................................. 443

7 Hibernation Module .............................................................................................. 4517.1 Block Diagram ............................................................................................................ 4527.2 Signal Description ....................................................................................................... 4527.3 Functional Description ................................................................................................. 4537.3.1 Register Access Timing ............................................................................................... 4537.3.2 Hibernation Clock Source ............................................................................................ 4547.3.3 System Implementation ............................................................................................... 4557.3.4 Battery Management ................................................................................................... 4567.3.5 Real-Time Clock .......................................................................................................... 4577.3.6 Battery-Backed Memory .............................................................................................. 4597.3.7 Power Control Using HIB ............................................................................................. 4597.3.8 Power Control Using VDD3ON Mode ........................................................................... 4597.3.9 Initiating Hibernate ...................................................................................................... 4597.3.10 Waking from Hibernate ................................................................................................ 4607.3.11 Arbitrary Power Removal ............................................................................................. 4607.3.12 Interrupts and Status ................................................................................................... 4607.4 Initialization and Configuration ..................................................................................... 4607.4.1 Initialization ................................................................................................................. 4617.4.2 RTC Match Functionality (No Hibernation) .................................................................... 4617.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 4627.4.4 External Wake-Up from Hibernation .............................................................................. 4627.4.5 RTC or External Wake-Up from Hibernation .................................................................. 4627.5 Register Map .............................................................................................................. 4637.6 Register Descriptions .................................................................................................. 463

8 Internal Memory ................................................................................................... 4818.1 Block Diagram ............................................................................................................ 4818.2 Functional Description ................................................................................................. 4828.2.1 SRAM ........................................................................................................................ 4828.2.2 ROM .......................................................................................................................... 4838.2.3 Flash Memory ............................................................................................................. 4858.2.4 EEPROM .................................................................................................................... 4898.3 Register Map .............................................................................................................. 4948.4 Flash Memory Register Descriptions (Flash Control Offset) ............................................ 4968.5 EEPROM Register Descriptions (EEPROM Offset) ........................................................ 5148.6 Memory Register Descriptions (System Control Offset) .................................................. 530

9 Micro Direct Memory Access (DMA) ................................................................ 5399.1 Block Diagram ............................................................................................................ 5409.2 Functional Description ................................................................................................. 5409.2.1 Channel Assignments .................................................................................................. 5419.2.2 Priority ........................................................................................................................ 542



9.2.3 Arbitration Size ............................................................................................................ 5429.2.4 Request Types ............................................................................................................ 5429.2.5 Channel Configuration ................................................................................................. 5439.2.6 Transfer Modes ........................................................................................................... 5459.2.7 Transfer Size and Increment ........................................................................................ 5539.2.8 Peripheral Interface ..................................................................................................... 5539.2.9 Software Request ........................................................................................................ 5539.2.10 Interrupts and Errors .................................................................................................... 5549.3 Initialization and Configuration ..................................................................................... 5549.3.1 Module Initialization ..................................................................................................... 5549.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 5559.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 5569.3.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 5589.3.5 Configuring Channel Assignments ................................................................................ 5609.4 Register Map .............................................................................................................. 5609.5 DMA Channel Control Structure ................................................................................. 5629.6 DMA Register Descriptions ........................................................................................ 569

10 General-Purpose Input/Outputs (GPIOs) ........................................................... 60310.1 Signal Description ....................................................................................................... 60310.2 Functional Description ................................................................................................. 60510.2.1 Data Control ............................................................................................................... 60710.2.2 Interrupt Control .......................................................................................................... 60810.2.3 Mode Control .............................................................................................................. 60910.2.4 Commit Control ........................................................................................................... 61010.2.5 Pad Control ................................................................................................................. 61010.2.6 Identification ............................................................................................................... 61010.3 Initialization and Configuration ..................................................................................... 61010.4 Register Map .............................................................................................................. 61210.5 Register Descriptions .................................................................................................. 614

11 General-Purpose Timers ...................................................................................... 65711.1 Block Diagram ............................................................................................................ 65811.2 Signal Description ....................................................................................................... 65911.3 Functional Description ................................................................................................. 66011.3.1 GPTM Reset Conditions .............................................................................................. 66111.3.2 Timer Modes ............................................................................................................... 66111.3.3 Wait-for-Trigger Mode .................................................................................................. 67111.3.4 Synchronizing GP Timer Blocks ................................................................................... 67211.3.5 DMA Operation ........................................................................................................... 67311.3.6 Accessing Concatenated 16/32-Bit GPTM Register Values ............................................ 67311.3.7 Accessing Concatenated 32/64-Bit Wide GPTM Register Values .................................... 67311.4 Initialization and Configuration ..................................................................................... 67511.4.1 One-Shot/Periodic Timer Mode .................................................................................... 67511.4.2 Real-Time Clock (RTC) Mode ...................................................................................... 67611.4.3 Input Edge-Count Mode ............................................................................................... 67611.4.4 Input Edge Timing Mode .............................................................................................. 67711.4.5 PWM Mode ................................................................................................................. 67711.5 Register Map .............................................................................................................. 67811.6 Register Descriptions .................................................................................................. 679


Table of Contents

12 Watchdog Timers ................................................................................................. 72712.1 Block Diagram ............................................................................................................ 72812.2 Functional Description ................................................................................................. 72812.2.1 Register Access Timing ............................................................................................... 72912.3 Initialization and Configuration ..................................................................................... 72912.4 Register Map .............................................................................................................. 72912.5 Register Descriptions .................................................................................................. 730

13 Analog-to-Digital Converter (ADC) ..................................................................... 75213.1 Block Diagram ............................................................................................................ 75313.2 Signal Description ....................................................................................................... 75413.3 Functional Description ................................................................................................. 75513.3.1 Sample Sequencers .................................................................................................... 75513.3.2 Module Control ............................................................................................................ 75613.3.3 Hardware Sample Averaging Circuit ............................................................................. 75913.3.4 Analog-to-Digital Converter .......................................................................................... 76013.3.5 Differential Sampling ................................................................................................... 76313.3.6 Internal Temperature Sensor ........................................................................................ 76513.3.7 Digital Comparator Unit ............................................................................................... 76613.4 Initialization and Configuration ..................................................................................... 77013.4.1 Module Initialization ..................................................................................................... 77013.4.2 Sample Sequencer Configuration ................................................................................. 77113.5 Register Map .............................................................................................................. 77113.6 Register Descriptions .................................................................................................. 773

14 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 84214.1 Block Diagram ............................................................................................................ 84314.2 Signal Description ....................................................................................................... 84314.3 Functional Description ................................................................................................. 84414.3.1 Transmit/Receive Logic ............................................................................................... 84414.3.2 Baud-Rate Generation ................................................................................................. 84514.3.3 Data Transmission ...................................................................................................... 84614.3.4 Serial IR (SIR) ............................................................................................................. 84614.3.5 ISO 7816 Support ....................................................................................................... 84714.3.6 Modem Handshake Support ......................................................................................... 84714.3.7 LIN Support ................................................................................................................ 84814.3.8 9-Bit UART Mode ........................................................................................................ 85014.3.9 FIFO Operation ........................................................................................................... 85014.3.10 Interrupts .................................................................................................................... 85114.3.11 Loopback Operation .................................................................................................... 85214.3.12 DMA Operation ........................................................................................................... 85214.4 Initialization and Configuration ..................................................................................... 85214.5 Register Map .............................................................................................................. 85314.6 Register Descriptions .................................................................................................. 855

15 Synchronous Serial Interface (SSI) .................................................................... 90515.1 Block Diagram ............................................................................................................ 90615.2 Signal Description ....................................................................................................... 90615.3 Functional Description ................................................................................................. 90715.3.1 Bit Rate Generation ..................................................................................................... 90715.3.2 FIFO Operation ........................................................................................................... 908



15.3.3 Interrupts .................................................................................................................... 90815.3.4 Frame Formats ........................................................................................................... 90915.3.5 DMA Operation ........................................................................................................... 91615.4 Initialization and Configuration ..................................................................................... 91715.5 Register Map .............................................................................................................. 91815.6 Register Descriptions .................................................................................................. 919

16 Inter-Integrated Circuit (I2C) Interface ................................................................ 94816.1 Block Diagram ............................................................................................................ 94916.2 Signal Description ....................................................................................................... 94916.3 Functional Description ................................................................................................. 95016.3.1 I2C Bus Functional Overview ........................................................................................ 95016.3.2 Available Speed Modes ............................................................................................... 95416.3.3 Interrupts .................................................................................................................... 95616.3.4 Loopback Operation .................................................................................................... 95716.3.5 Command Sequence Flow Charts ................................................................................ 95716.4 Initialization and Configuration ..................................................................................... 96516.5 Register Map .............................................................................................................. 96716.6 Register Descriptions (I2C Master) ............................................................................... 96816.7 Register Descriptions (I2C Slave) ................................................................................. 98316.8 Register Descriptions (I2C Status and Control) .............................................................. 993

17 Controller Area Network (CAN) Module ............................................................. 99617.1 Block Diagram ............................................................................................................ 99717.2 Signal Description ....................................................................................................... 99717.3 Functional Description ................................................................................................. 99817.3.1 Initialization ................................................................................................................. 99917.3.2 Operation ................................................................................................................... 99917.3.3 Transmitting Message Objects ................................................................................... 100017.3.4 Configuring a Transmit Message Object ...................................................................... 100117.3.5 Updating a Transmit Message Object ......................................................................... 100217.3.6 Accepting Received Message Objects ........................................................................ 100217.3.7 Receiving a Data Frame ............................................................................................ 100317.3.8 Receiving a Remote Frame ........................................................................................ 100317.3.9 Receive/Transmit Priority ........................................................................................... 100317.3.10 Configuring a Receive Message Object ...................................................................... 100417.3.11 Handling of Received Message Objects ...................................................................... 100517.3.12 Handling of Interrupts ................................................................................................ 100717.3.13 Test Mode ................................................................................................................. 100817.3.14 Bit Timing Configuration Error Considerations ............................................................. 101017.3.15 Bit Time and Bit Rate ................................................................................................. 101017.3.16 Calculating the Bit Timing Parameters ........................................................................ 101217.4 Register Map ............................................................................................................ 101517.5 CAN Register Descriptions ......................................................................................... 1016

18 Universal Serial Bus (USB) Controller ............................................................. 104618.1 Block Diagram ........................................................................................................... 104718.2 Signal Description ..................................................................................................... 104718.3 Functional Description ............................................................................................... 104718.3.1 Operation .................................................................................................................. 1047


Table of Contents

18.3.2 DMA Operation ......................................................................................................... 105218.4 Initialization and Configuration .................................................................................... 105318.4.1 Endpoint Configuration .............................................................................................. 105418.5 Register Map ............................................................................................................ 105418.6 Register Descriptions ................................................................................................. 1057

19 Analog Comparators .......................................................................................... 110319.1 Block Diagram ........................................................................................................... 110419.2 Signal Description ..................................................................................................... 110419.3 Functional Description ............................................................................................... 110519.3.1 Internal Reference Programming ................................................................................ 110619.4 Initialization and Configuration .................................................................................... 110819.5 Register Map ............................................................................................................ 110819.6 Register Descriptions ................................................................................................. 1109

20 Pin Diagram ........................................................................................................ 111821 Signal Tables ...................................................................................................... 111921.1 Signals by Pin Number .............................................................................................. 112021.2 Signals by Signal Name ............................................................................................. 112521.3 Signals by Function, Except for GPIO ......................................................................... 113021.4 GPIO Pins and Alternate Functions ............................................................................ 113421.5 Possible Pin Assignments for Alternate Functions ....................................................... 113721.6 Connections for Unused Signals ................................................................................. 1139

22 Operating Characteristics ................................................................................. 114123 Electrical Characteristics .................................................................................. 114223.1 Maximum Ratings ...................................................................................................... 114223.2 Recommended Operating Conditions ......................................................................... 114323.3 Load Conditions ........................................................................................................ 114423.4 JTAG and Boundary Scan .......................................................................................... 114523.5 Power and Brown-Out ............................................................................................... 114623.6 Reset ........................................................................................................................ 114723.7 On-Chip Low Drop-Out (LDO) Regulator ..................................................................... 114823.8 Clocks ...................................................................................................................... 114923.8.1 PLL Specifications ..................................................................................................... 114923.8.2 PIOSC Specifications ................................................................................................ 115023.8.3 Internal 30-kHz Oscillator Specifications ..................................................................... 115023.8.4 Hibernation Clock Source Specifications ..................................................................... 115023.8.5 Main Oscillator Specifications ..................................................................................... 115123.8.6 System Clock Specification with ADC Operation .......................................................... 115423.8.7 System Clock Specification with USB Operation .......................................................... 115423.9 Sleep Modes ............................................................................................................. 115523.10 Hibernation Module ................................................................................................... 115523.11 Flash Memory and EEPROM ..................................................................................... 115623.12 Input/Output Characteristics ....................................................................................... 115723.13 Analog-to-Digital Converter (ADC) .............................................................................. 115823.14 Synchronous Serial Interface (SSI) ............................................................................. 116023.15 Inter-Integrated Circuit (I2C) Interface ......................................................................... 116223.16 Universal Serial Bus (USB) Controller ......................................................................... 116223.17 Analog Comparator ................................................................................................... 1162



23.18 Current Consumption ................................................................................................. 116423.18.1 Preliminary Current Consumption ............................................................................... 1164

A Register Quick Reference ................................................................................. 1166B Ordering and Contact Information ................................................................... 1208B.1 Ordering Information .................................................................................................. 1208B.2 Part Markings ............................................................................................................ 1208B.3 Kits ........................................................................................................................... 1208B.4 Support Information ................................................................................................... 1209

C Package Information .......................................................................................... 1210C.1 64-Pin LQFP Package ............................................................................................... 1210C.1.1 Package Dimensions ................................................................................................. 1210


Table of Contents

List of FiguresFigure 1-1. Stellaris Blizzard-class Block Diagram ................................................................ 43Figure 1-2. Stellaris LM4F120H5QR Microcontroller High-Level Block Diagram ........................ 45Figure 2-1. CPU Block Diagram ............................................................................................. 66Figure 2-2. TPIU Block Diagram ............................................................................................ 67Figure 2-3. Cortex-M4F Register Set ...................................................................................... 70Figure 2-4. Bit-Band Mapping ................................................................................................ 94Figure 2-5. Data Storage ....................................................................................................... 95Figure 2-6. Vector Table ...................................................................................................... 102Figure 2-7. Exception Stack Frame ...................................................................................... 105Figure 3-1. SRD Use Example ............................................................................................. 123Figure 3-2. FPU Register Bank ............................................................................................ 126Figure 4-1. JTAG Module Block Diagram .............................................................................. 196Figure 4-2. Test Access Port State Machine ......................................................................... 199Figure 4-3. IDCODE Register Format ................................................................................... 205Figure 4-4. BYPASS Register Format ................................................................................... 205Figure 4-5. Boundary Scan Register Format ......................................................................... 206Figure 5-1. Basic RST Configuration .................................................................................... 210Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 210Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 211Figure 5-4. Power Architecture ............................................................................................ 214Figure 5-5. Main Clock Tree ................................................................................................ 217Figure 5-6. Module Clock Selection ...................................................................................... 224Figure 7-1. Hibernation Module Block Diagram ..................................................................... 452Figure 7-2. Using a Crystal as the Hibernation Clock Source with a Single Battery Source ...... 454Figure 7-3. Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON

Mode ................................................................................................................ 455Figure 7-4. Using a Regulator for Both VDD and VBAT ............................................................ 456Figure 8-1. Internal Memory Block Diagram .......................................................................... 481Figure 8-2. EEPROM Block Diagram ................................................................................... 482Figure 9-1. DMA Block Diagram ......................................................................................... 540Figure 9-2. Example of Ping-Pong DMA Transaction ........................................................... 546Figure 9-3. Memory Scatter-Gather, Setup and Configuration ................................................ 548Figure 9-4. Memory Scatter-Gather, DMA Copy Sequence .................................................. 549Figure 9-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 551Figure 9-6. Peripheral Scatter-Gather, DMA Copy Sequence ............................................... 552Figure 10-1. Digital I/O Pads ................................................................................................. 606Figure 10-2. Analog/Digital I/O Pads ...................................................................................... 607Figure 10-3. GPIODATA Write Example ................................................................................. 608Figure 10-4. GPIODATA Read Example ................................................................................. 608Figure 11-1. GPTM Module Block Diagram ............................................................................ 658Figure 11-2. Reading the RTC Value ...................................................................................... 665Figure 11-3. Input Edge-Count Mode Example, Counting Down ............................................... 667Figure 11-4. 16-Bit Input Edge-Time Mode Example ............................................................... 668Figure 11-5. 16-Bit PWM Mode Example ................................................................................ 670Figure 11-6. CCP Output, GPTMTnMATCHR > GPTMTnILR ................................................... 670Figure 11-7. CCP Output, GPTMTnMATCHR = GPTMTnILR ................................................... 671



Figure 11-8. CCP Output, GPTMTnILR > GPTMTnMATCHR ................................................... 671Figure 11-9. Timer Daisy Chain ............................................................................................. 672Figure 12-1. WDT Module Block Diagram .............................................................................. 728Figure 13-1. Implementation of Two ADC Blocks .................................................................... 753Figure 13-2. ADC Module Block Diagram ............................................................................... 754Figure 13-3. ADC Sample Phases ......................................................................................... 758Figure 13-4. Doubling the ADC Sample Rate .......................................................................... 758Figure 13-5. Skewed Sampling .............................................................................................. 759Figure 13-6. Sample Averaging Example ............................................................................... 760Figure 13-7. ADC Input Equivalency Diagram ......................................................................... 761Figure 13-8. ADC Voltage Reference ..................................................................................... 762Figure 13-9. ADC Conversion Result ..................................................................................... 763Figure 13-10. Differential Voltage Representation ..................................................................... 765Figure 13-11. Internal Temperature Sensor Characteristic ......................................................... 766Figure 13-12. Low-Band Operation (CIC=0x0) .......................................................................... 768Figure 13-13. Mid-Band Operation (CIC=0x1) .......................................................................... 769Figure 13-14. High-Band Operation (CIC=0x3) ......................................................................... 770Figure 14-1. UART Module Block Diagram ............................................................................. 843Figure 14-2. UART Character Frame ..................................................................................... 845Figure 14-3. IrDA Data Modulation ......................................................................................... 847Figure 14-4. LIN Message ..................................................................................................... 849Figure 14-5. LIN Synchronization Field ................................................................................... 850Figure 15-1. SSI Module Block Diagram ................................................................................. 906Figure 15-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 910Figure 15-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 910Figure 15-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 911Figure 15-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 911Figure 15-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 912Figure 15-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 913Figure 15-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 913Figure 15-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 914Figure 15-10. MICROWIRE Frame Format (Single Frame) ........................................................ 915Figure 15-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 916Figure 15-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 916Figure 16-1. I2C Block Diagram ............................................................................................. 949Figure 16-2. I2C Bus Configuration ........................................................................................ 950Figure 16-3. START and STOP Conditions ............................................................................. 951Figure 16-4. Complete Data Transfer with a 7-Bit Address ....................................................... 951Figure 16-5. R/S Bit in First Byte ............................................................................................ 952Figure 16-6. Data Validity During Bit Transfer on the I2C Bus ................................................... 952Figure 16-7. High-Speed Data Format ................................................................................... 956Figure 16-8. Master Single TRANSMIT .................................................................................. 958Figure 16-9. Master Single RECEIVE ..................................................................................... 959Figure 16-10. Master TRANSMIT of Multiple Data Bytes ........................................................... 960Figure 16-11. Master RECEIVE of Multiple Data Bytes ............................................................. 961Figure 16-12. Master RECEIVE with Repeated START after Master TRANSMIT ........................ 962Figure 16-13. Master TRANSMIT with Repeated START after Master RECEIVE ........................ 963Figure 16-14. High Speed Mode Master Transmit ..................................................................... 964


Table of Contents

Figure 16-15. Slave Command Sequence ................................................................................ 965Figure 17-1. CAN Controller Block Diagram ............................................................................ 997Figure 17-2. CAN Data/Remote Frame .................................................................................. 998Figure 17-3. Message Objects in a FIFO Buffer .................................................................... 1007Figure 17-4. CAN Bit Time ................................................................................................... 1011Figure 18-1. USB Module Block Diagram ............................................................................. 1047Figure 19-1. Analog Comparator Module Block Diagram ....................................................... 1104Figure 19-2. Structure of Comparator Unit ............................................................................ 1105Figure 19-3. Comparator Internal Reference Structure .......................................................... 1106Figure 20-1. 64-Pin LQFP Package Pin Diagram .................................................................. 1118Figure 23-1. ESD Protection on GPIOs and XOSCn Pins ...................................................... 1143Figure 23-2. ESD Protection on Non-Power, Non-GPIO, and Non-XOSCn Pins ...................... 1143Figure 23-3. Load Conditions ............................................................................................... 1144Figure 23-4. JTAG Test Clock Input Timing ........................................................................... 1145Figure 23-5. JTAG Test Access Port (TAP) Timing ................................................................ 1146Figure 23-6. Power-On and Brown-Out Reset and Voltage Parameters .................................. 1147Figure 23-7. Brown-Out Reset Timing .................................................................................. 1147Figure 23-8. External Reset Timing (RST) ............................................................................ 1148Figure 23-9. Software Reset Timing ..................................................................................... 1148Figure 23-10. Watchdog Reset Timing ................................................................................... 1148Figure 23-11. MOSC Failure Reset Timing ............................................................................. 1148Figure 23-12. Hibernation Module Timing ............................................................................... 1156Figure 23-13. ADC Input Equivalency Diagram ....................................................................... 1160Figure 23-14. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing

Measurement .................................................................................................. 1161Figure 23-15. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............... 1161Figure 23-16. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................... 1161Figure 23-17. I2C Timing ....................................................................................................... 1162Figure C-1. Stellaris LM4F120H5QR 64-Pin LQFP Package ................................................ 1210



List of TablesTable 1. Revision History .................................................................................................. 34Table 2. Documentation Conventions ................................................................................ 40Table 1-1. Stellaris LM4F Device Series ................................................................................ 43Table 1-2. Stellaris LM4F120H5QR Microcontroller Features ................................................. 44Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 69Table 2-2. Processor Register Map ....................................................................................... 70Table 2-3. PSR Register Combinations ................................................................................. 76Table 2-4. Memory Map ....................................................................................................... 87Table 2-5. Memory Access Behavior ..................................................................................... 90Table 2-6. SRAM Memory Bit-Banding Regions .................................................................... 92Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................... 92Table 2-8. Exception Types .................................................................................................. 98Table 2-9. Interrupts ............................................................................................................ 99Table 2-10. Exception Return Behavior ................................................................................. 106Table 2-11. Faults ............................................................................................................... 107Table 2-12. Fault Status and Fault Address Registers ............................................................ 108Table 2-13. Cortex-M4F Instruction Summary ....................................................................... 110Table 3-1. Core Peripheral Register Regions ....................................................................... 117Table 3-2. Memory Attributes Summary .............................................................................. 121Table 3-3. TEX, S, C, and B Bit Field Encoding ................................................................... 123Table 3-4. Cache Policy for Memory Attribute Encoding ....................................................... 124Table 3-5. AP Bit Field Encoding ........................................................................................ 124Table 3-6. Memory Region Attributes for Stellaris Microcontrollers ........................................ 125Table 3-7. QNaN and SNaN Handling ................................................................................. 128Table 3-8. Peripherals Register Map ................................................................................... 129Table 3-9. Interrupt Priority Levels ...................................................................................... 159Table 3-10. Example SIZE Field Values ................................................................................ 187Table 4-1. JTAG_SWD_SWO Signals (64LQFP) ................................................................. 196Table 4-2. JTAG Port Pins State after Power-On Reset or RST assertion .............................. 197Table 4-3. JTAG Instruction Register Commands ................................................................. 203Table 5-1. System Control & Clocks Signals (64LQFP) ........................................................ 207Table 5-2. Reset Sources ................................................................................................... 208Table 5-3. Clock Source Options ........................................................................................ 215Table 5-4. Possible System Clock Frequencies Using the SYSDIV Field ............................... 218Table 5-5. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 218Table 5-6. Examples of Possible System Clock Frequencies with DIV400=1 ......................... 219Table 5-7. System Control Register Map ............................................................................. 225Table 5-8. RCC2 Fields that Override RCC Fields ............................................................... 249Table 6-1. System Exception Register Map ......................................................................... 443Table 7-1. Hibernate Signals (64LQFP) ............................................................................... 452Table 7-2. Counter Behavior with a TRIM Value of 0x8003 ................................................... 458Table 7-3. Counter Behavior with a TRIM Value of 0x7FFC .................................................. 459Table 7-4. Hibernation Module Clock Operation ................................................................... 461Table 7-5. Hibernation Module Register Map ....................................................................... 463Table 8-1. Flash Memory Protection Policy Combinations .................................................... 486Table 8-2. User-Programmable Flash Memory Resident Registers ....................................... 489


Table of Contents

Table 8-3. Flash Register Map ............................................................................................ 494Table 9-1. DMA Channel Assignments .............................................................................. 541Table 9-2. Request Type Support ....................................................................................... 543Table 9-3. Control Structure Memory Map ........................................................................... 544Table 9-4. Channel Control Structure .................................................................................. 544Table 9-5. DMA Read Example: 8-Bit Peripheral ................................................................ 553Table 9-6. DMA Interrupt Assignments .............................................................................. 554Table 9-7. Channel Control Structure Offsets for Channel 30 ................................................ 555Table 9-8. Channel Control Word Configuration for Memory Transfer Example ...................... 555Table 9-9. Channel Control Structure Offsets for Channel 7 .................................................. 556Table 9-10. Channel Control Word Configuration for Peripheral Transmit Example .................. 557Table 9-11. Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 558Table 9-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive

Example ............................................................................................................ 559Table 9-13. DMA Register Map .......................................................................................... 561Table 10-1. GPIO Pins With Non-Zero Reset Values .............................................................. 604Table 10-2. GPIO Pins and Alternate Functions (64LQFP) ..................................................... 604Table 10-3. GPIO Pad Configuration Examples ..................................................................... 611Table 10-4. GPIO Interrupt Configuration Example ................................................................ 611Table 10-5. GPIO Pins With Non-Zero Reset Values .............................................................. 613Table 10-6. GPIO Register Map ........................................................................................... 613Table 10-7. GPIO Pins With Non-Zero Reset Values .............................................................. 624Table 10-8. GPIO Pins With Non-Zero Reset Values .............................................................. 630Table 10-9. GPIO Pins With Non-Zero Reset Values .............................................................. 632Table 10-10. GPIO Pins With Non-Zero Reset Values .............................................................. 635Table 10-11. GPIO Pins With Non-Zero Reset Values .............................................................. 641Table 11-1. Available CCP Pins ............................................................................................ 658Table 11-2. General-Purpose Timers Signals (64LQFP) ......................................................... 659Table 11-3. General-Purpose Timer Capabilities .................................................................... 661Table 11-4. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes .......... 662Table 11-5. 16-Bit Timer With Prescaler Configurations ......................................................... 663Table 11-6. 32-Bit Timer (configured in 32/64-bit mode) With Prescaler Configurations ............ 663Table 11-7. Counter Values When the Timer is Enabled in RTC Mode .................................... 664Table 11-8. Counter Values When the Timer is Enabled in Input Edge-Count Mode ................. 666Table 11-9. Counter Values When the Timer is Enabled in Input Event-Count Mode ................ 667Table 11-10. Counter Values When the Timer is Enabled in PWM Mode ................................... 669Table 11-11. Timeout Actions for GPTM Modes ...................................................................... 672Table 11-12. Timers Register Map .......................................................................................... 679Table 12-1. Watchdog Timers Register Map .......................................................................... 730Table 13-1. ADC Signals (64LQFP) ...................................................................................... 754Table 13-2. Samples and FIFO Depth of Sequencers ............................................................ 755Table 13-3. Differential Sampling Pairs ................................................................................. 763Table 13-4. ADC Register Map ............................................................................................. 771Table 14-1. UART Signals (64LQFP) .................................................................................... 844Table 14-2. Flow Control Mode ............................................................................................. 848Table 14-3. UART Register Map ........................................................................................... 854Table 15-1. SSI Signals (64LQFP) ........................................................................................ 907Table 15-2. SSI Register Map .............................................................................................. 918



Table 16-1. I2C Signals (64LQFP) ........................................................................................ 949Table 16-2. Examples of I2C Master Timer Period versus Speed Mode ................................... 955Table 16-3. Examples of I2C Master Timer Period in High-Speed Mode .................................. 955Table 16-4. Inter-Integrated Circuit (I2C) Interface Register Map ............................................. 967Table 16-5. Write Field Decoding for I2CMCS[3:0] Field ......................................................... 973Table 17-1. Controller Area Network Signals (64LQFP) .......................................................... 998Table 17-2. Message Object Configurations ........................................................................ 1003Table 17-3. CAN Protocol Ranges ...................................................................................... 1011Table 17-4. CANBIT Register Values .................................................................................. 1011Table 17-5. CAN Register Map ........................................................................................... 1015Table 18-1. USB Signals (64LQFP) .................................................................................... 1047Table 18-2. Remainder (MAXLOAD/4) ................................................................................ 1053Table 18-3. Actual Bytes Read ........................................................................................... 1053Table 18-4. Packet Sizes That Clear RXRDY ...................................................................... 1053Table 18-5. Universal Serial Bus (USB) Controller Register Map ........................................... 1054Table 19-1. Analog Comparators Signals (64LQFP) ............................................................. 1104Table 19-2. Internal Reference Voltage and ACREFCTL Field Values ................................... 1106Table 19-3. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and

RNG = 0 .......................................................................................................... 1107Table 19-4. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and

RNG = 1 .......................................................................................................... 1107Table 19-5. Analog Comparators Register Map ................................................................... 1108Table 21-1. GPIO Pins With Default Alternate Functions ...................................................... 1119Table 21-2. Signals by Pin Number ..................................................................................... 1120Table 21-3. Signals by Signal Name ................................................................................... 1125Table 21-4. Signals by Function, Except for GPIO ............................................................... 1130Table 21-5. GPIO Pins and Alternate Functions ................................................................... 1134Table 21-6. Possible Pin Assignments for Alternate Functions .............................................. 1137Table 21-7. Connections for Unused Signals (64-Pin LQFP) ................................................. 1139Table 22-1. Temperature Characteristics ............................................................................. 1141Table 22-2. Thermal Characteristics ................................................................................... 1141Table 22-3. ESD Absolute Maximum Ratings ...................................................................... 1141Table 23-1. Maximum Ratings ............................................................................................ 1142Table 23-2. Recommended DC Operating Conditions .......................................................... 1143Table 23-3. GPIO Current Restrictions ................................................................................ 1144Table 23-4. GPIO Package Side Assignments ..................................................................... 1144Table 23-5. JTAG Characteristics ....................................................................................... 1145Table 23-6. Power Characteristics ...................................................................................... 1146Table 23-7. Reset Characteristics ....................................................................................... 1147Table 23-8. LDO Regulator Characteristics ......................................................................... 1148Table 23-9. Phase Locked Loop (PLL) Characteristics ......................................................... 1149Table 23-10. Actual PLL Frequency ...................................................................................... 1149Table 23-11. PIOSC Clock Characteristics ............................................................................ 1150Table 23-12. 30-kHz Clock Characteristics ............................................................................ 1150Table 23-13. HIB Oscillator Input Characteristics ................................................................... 1150Table 23-14. Main Oscillator Input Characteristics ................................................................. 1151Table 23-15. Crystal Parameters .......................................................................................... 1153Table 23-16. Supported MOSC Crystal Frequencies .............................................................. 1153


Table of Contents

Table 23-17. System Clock Characteristics with ADC Operation ............................................. 1154Table 23-18. System Clock Characteristics with USB Operation ............................................. 1154Table 23-19. Sleep Modes AC Characteristics ....................................................................... 1155Table 23-20. Hibernation Module Battery Characteristics ....................................................... 1155Table 23-21. Hibernation Module AC Characteristics ............................................................. 1155Table 23-22. Flash Memory Characteristics ........................................................................... 1156Table 23-23. EEPROM Characteristics ................................................................................. 1156Table 23-24. GPIO Module Characteristics ............................................................................ 1157Table 23-25. ADC Electrical Characteristics .......................................................................... 1158Table 23-26. SSI Characteristics .......................................................................................... 1160Table 23-27. I2C Characteristics ........................................................................................... 1162Table 23-28. Analog Comparator Characteristics ................................................................... 1162Table 23-29. Analog Comparator Voltage Reference Characteristics ...................................... 1163Table 23-30. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and

RNG = 0 .......................................................................................................... 1163Table 23-31. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and

RNG = 1 .......................................................................................................... 1163Table 23-32. Preliminary Current Consumption ..................................................................... 1164Table B-1. Part Ordering Information ................................................................................. 1208



List of RegistersThe Cortex-M4F Processor ........................................................................................................... 64Register 1: Cortex General-Purpose Register 0 (R0) ........................................................................... 72Register 2: Cortex General-Purpose Register 1 (R1) ........................................................................... 72Register 3: Cortex General-Purpose Register 2 (R2) ........................................................................... 72Register 4: Cortex General-Purpose Register 3 (R3) ........................................................................... 72Register 5: Cortex General-Purpose Register 4 (R4) ........................................................................... 72Register 6: Cortex General-Purpose Register 5 (R5) ........................................................................... 72Register 7: Cortex General-Purpose Register 6 (R6) ........................................................................... 72Register 8: Cortex General-Purpose Register 7 (R7) ........................................................................... 72Register 9: Cortex General-Purpose Register 8 (R8) ........................................................................... 72Register 10: Cortex General-Purpose Register 9 (R9) ........................................................................... 72Register 11: Cortex General-Purpose Register 10 (R10) ....................................................................... 72Register 12: Cortex General-Purpose Register 11 (R11) ........................................................................ 72Register 13: Cortex General-Purpose Register 12 (R12) ....................................................................... 72Register 14: Stack Pointer (SP) ........................................................................................................... 73Register 15: Link Register (LR) ............................................................................................................ 74Register 16: Program Counter (PC) ..................................................................................................... 75Register 17: Program Status Register (PSR) ........................................................................................ 76Register 18: Priority Mask Register (PRIMASK) .................................................................................... 80Register 19: Fault Mask Register (FAULTMASK) .................................................................................. 81Register 20: Base Priority Mask Register (BASEPRI) ............................................................................ 82Register 21: Control Register (CONTROL) ........................................................................................... 83Register 22: Floating-Point Status Control (FPSC) ................................................................................ 85

Cortex-M4 Peripherals ................................................................................................................. 117Register 1: SysTick Control and Status Register (STCTRL), offset 0x010 ........................................... 133Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014 .............................................. 135Register 3: SysTick Current Value Register (STCURRENT), offset 0x018 ........................................... 136Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 137Register 5: Interrupt 32-63 Set Enable (EN1), offset 0x104 ................................................................ 137Register 6: Interrupt 64-95 Set Enable (EN2), offset 0x108 ................................................................ 137Register 7: Interrupt 96-127 Set Enable (EN3), offset 0x10C ............................................................. 137Register 8: Interrupt 128-138 Set Enable (EN4), offset 0x110 ............................................................ 138Register 9: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 139Register 10: Interrupt 32-63 Clear Enable (DIS1), offset 0x184 ............................................................ 139Register 11: Interrupt 64-95 Clear Enable (DIS2), offset 0x188 ............................................................ 139Register 12: Interrupt 96-127 Clear Enable (DIS3), offset 0x18C .......................................................... 139Register 13: Interrupt 128-138 Clear Enable (DIS4), offset 0x190 ........................................................ 140Register 14: Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 141Register 15: Interrupt 32-63 Set Pending (PEND1), offset 0x204 ......................................................... 141Register 16: Interrupt 64-95 Set Pending (PEND2), offset 0x208 ......................................................... 141Register 17: Interrupt 96-127 Set Pending (PEND3), offset 0x20C ....................................................... 141Register 18: Interrupt 128-138 Set Pending (PEND4), offset 0x210 ...................................................... 142Register 19: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 143Register 20: Interrupt 32-63 Clear Pending (UNPEND1), offset 0x284 .................................................. 143Register 21: Interrupt 64-95 Clear Pending (UNPEND2), offset 0x288 .................................................. 143


Table of Contents

Register 22: Interrupt 96-127 Clear Pending (UNPEND3), offset 0x28C ............................................... 143Register 23: Interrupt 128-138 Clear Pending (UNPEND4), offset 0x290 .............................................. 144Register 24: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 145Register 25: Interrupt 32-63 Active Bit (ACTIVE1), offset 0x304 ........................................................... 145Register 26: Interrupt 64-95 Active Bit (ACTIVE2), offset 0x308 ........................................................... 145Register 27: Interrupt 96-127 Active Bit (ACTIVE3), offset 0x30C ........................................................ 145Register 28: Interrupt 128-138 Active Bit (ACTIVE4), offset 0x310 ....................................................... 146Register 29: Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 147Register 30: Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 147Register 31: Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 147Register 32: Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 147Register 33: Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 147Register 34: Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 147Register 35: Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 147Register 36: Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 147Register 37: Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 147Register 38: Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 147Register 39: Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 147Register 40: Interrupt 44-47 Priority (PRI11), offset 0x42C ................................................................... 147Register 41: Interrupt 48-51 Priority (PRI12), offset 0x430 ................................................................... 147Register 42: Interrupt 52-55 Priority (PRI13), offset 0x434 ................................................................... 147Register 43: Interrupt 56-59 Priority (PRI14), offset 0x438 ................................................................... 147Register 44: Interrupt 60-63 Priority (PRI15), offset 0x43C .................................................................. 147Register 45: Interrupt 64-67 Priority (PRI16), offset 0x440 ................................................................... 149Register 46: Interrupt 68-71 Priority (PRI17), offset 0x444 ................................................................... 149Register 47: Interrupt 72-75 Priority (PRI18), offset 0x448 ................................................................... 149Register 48: Interrupt 76-79 Priority (PRI19), offset 0x44C .................................................................. 149Register 49: Interrupt 80-83 Priority (PRI20), offset 0x450 ................................................................... 149Register 50: Interrupt 84-87 Priority (PRI21), offset 0x454 ................................................................... 149Register 51: Interrupt 88-91 Priority (PRI22), offset 0x458 ................................................................... 149Register 52: Interrupt 92-95 Priority (PRI23), offset 0x45C .................................................................. 149Register 53: Interrupt 96-99 Priority (PRI24), offset 0x460 ................................................................... 149Register 54: Interrupt 100-103 Priority (PRI25), offset 0x464 ............................................................... 149Register 55: Interrupt 104-107 Priority (PRI26), offset 0x468 ............................................................... 149Register 56: Interrupt 108-111 Priority (PRI27), offset 0x46C ........................