star pixel detector readout prototyping status
DESCRIPTION
STAR Pixel Detector readout prototyping status. Talk Outline. Quick review of requirements and system design Status at last meeting at IPHC RDO hardware status RDO firmware and software status Future development path. 2. RDO Requirements and Design. - PowerPoint PPT PresentationTRANSCRIPT
STAR Pixel Detectorreadout prototyping status
LBNL-IPHC-06/2009 - LG 22
Talk Outline
• Quick review of requirements and system design
• Status at last meeting at IPHC
• RDO hardware status
• RDO firmware and software status
• Future development path
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RDO Requirements and DesignIn addition to the detailed requirements imposed by the interface to the
sensors, the RDO system shall:
• Triggered detector system fitting into existing STAR infrastructure (Trigger, DAQ, etc.)
• Deliver full frame events to STAR DAQ for event building at approximately the same rate as the TPC (1 kHz for DAQ1000).
• Have live time characteristics such that the Pixel detector is live whenever the TPC is live.
• Reduce the total data rate of the detector to a manageable level (< TPC rate of ~1MB / event).
• Reliable, robust, cost effective, etc.
Furthermore, this RDO system will be the basis of the future sensor testing including production probe testing so additional functionality will be included to enable this system to have the needed additional capabilities.
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Pixel Detector Design
Ladder with 10 MAPS sensors (~ 2×2 cm each)
MAPSRDObuffers/drivers
4-layer kapton cable with aluminium traces
Mechanical support with kinematic mounts
Cabling and cooling infrastructure
Detector extraction at one end of the cone
New beryllium beam pipe (800 µm thick, r = 2 cm)
2 layers10 modules4 ladders/module
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Functional Data Path – One Ladder
buffer
JTAG, CLK, CTL, markers
buffer
This is a highly parallel readout system. 4 ladders per module (RDO motherboard). 10 modules in the PIXEL detector.
LU protected power
Digital hit data
10 sensors
After power-on and configuration, the sensors are run continuously. Triggering is handled in the next stage of the RDO.
1 Ladder
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Functional Data Path – Phase 1
Each received trigger enables an event buffer for one frame.
The system is dead-time free up to the hardware limit of the number of buffers.
Highly Parallel FPGA based RDO system
AddressCounter(zero-
suppression)
EventBuffer
EventBuffer
EventBuffer
1
2
10
EventBuilder
RDOBuffer
SIU
DAQPC
Disk
160 MHzBinary Data
(4 chains per sensor) * (10 sensors per ladder) *(4 ladders per RDO board) = 160 chains per RDO board
160 independent sensor data chains
One per RDO board
FPGA Block RAM
•40 sensor outputs/ladder•4 ladders/module•1 RDO board/module•3 RDO boards for Phase-1 prototype test system
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Functional Data Path – Final (Ultimate)
•20 sensor outputs/ladder•4 ladders/module•1 RDO board/module•10 RDO boards for system
Each received trigger enables an event buffer for one frame. Triggered event boundaries are determined by data order.
Highly Parallel FPGA based RDO system
EventBuffer
EventBuffer
EventBuffer
1
2
10
EventBuilder
RDOBuffer
SIU
DAQPC
Disk
160 MHz Address only data
(2 chain per sensor) * (10 sensors per ladder) *(4 ladders per RDO board) = 80 chains per RDO board
80 independent sensor data chains
One per RDO board
Same hardware with reconfigured firmware
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RDO System Design – Physical Layout
1-2 mLow mass twisted pair
6 m - twisted pair
Sensors, Ladders, Modules(interaction point)
LU Protected Regulators,Mass cable termination
RDO BoardsDAQ PCs
(Low Rad Area)
DAQ Room
PowerSupplies
Platform
30 m
100 m - Fiber optic
30 m
Control PCs
Platform
30 m
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RDO Status as of 04/2008 LBNL-IPHC meeting
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RDO Status - Hardware
Hardware – RDO motherboard – Fabricated, tested for individual sensor readout (analog and digital). 3 RDO systems loaded and tested.Mass termination board – Fabricated – under test. Full testing will commence with the readout of a 10 sensor ladder. 1 board loaded.LU protected power boards – Fabricated and tested. 5 boards loaded and tested. Low mass cable – Separate presentation.
LBNL-IPHC-06/2009 - LG 1111
RDO Status – Firmware and Software
Control Logic State Machine
JTAG
TCD Interface / logic
SRAM controller
ADC Controller
Address counter
Event FIFOs
Header Builder
Event Builder
Clk / Marker / START /logic and monitor
LU monitor / control
Temp. ADC controller
Internal Monitoring
Control Interface
SIU Interface
USB Interface
Soft CPU
•Status as shown above. •Software is on a parallel path
See http://rnc.lbl.gov/hft/hardware/docs/Phase1/index.html for full documentation
Mimostar-3 Testing
Phase-1 ladder Testing
Same for all
Phase-1 Testing
LBNL-IPHC-06/2009 - LG 1212
RDO Status – Firmware and Software
•Phase-1 readout firmware and software are complete and working for analog and digital data for individual sensor testing.•DDL optical link and USB based data paths are both functional.•Analysis software for Phase-1 data is mostly complete. We are using both Root and Labview based analysis paths.•Scripting needed for automated testing of sensors is complete and working.•The analysis path for 10 sensor ladders is expected to be a simple extension of the existing framework.
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• Adaptation of the existing individual testing system for use in automated probe testing.
• Development of the 10 sensor ladder readout firmware and software.
• Design and implementation of a slow control system for the detector.
• Extension of the system into multi-ladder / multi-sector readout.
RDO Status – Future Development
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end
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Parameters and Data Rates
Item Number
Bits/address 20
Integration time 200 µs
Luminosity 8 × 1027
Hits / frame on Inner sensors (r=2.5 cm)
246
Hits / frame on Outer sensors (r=8.0 cm)
24
Final sensors (Inner ladders) 100
Final sensors (Outer ladders) 300
Event format overhead TBD
Average Pixels / Cluster 2.5
Average Trigger rate 1 kHz
Item Number
Bits/address 20
Integration time 640 µs
Luminosity 3 × 1027
Hits / frame on Inner sensors (r=2.5 cm)
295
Hits / frame on Outer sensors (r=8.0 cm)
29
Phase-1 sensors (Inner ladders) 100
Phase-1 sensors (Outer ladders) 300
Event format overhead TBD
Average Pixels / Cluster 2.5
Average Trigger rate 1 kHz
Phase-1 Final (Ultimate)
Raw data rate from sensors = 32 GB/secData rate to storage = 237 MB/sec(Scaled to full size detector)
Data rate to storage = 199 MB/sec
Note: Data rates for hit data only for Au-Au central collisions including peripheral collision electrons. Sensor noise is not included.
Item Number
Bits/address 20*
Integration time 640 µs
Luminosity 3 × 1027
Hits / frame on Inner sensors (r=2.5 cm) 295
Hits / frame on Outer sensors (r=8.0 cm) 29
Phase-1 sensors (Inner ladders) 100
Phase-1 sensors (Outer ladders) 300
Event format overhead TBD
Average Pixels / Cluster 2.5
Average Trigger rate 1 kHz
Item Number
Bits/address 20*
Integration time 200 µs
Luminosity 8 × 1027
Hits / frame on Inner sensors (r=2.5 cm) 246
Hits / frame on Outer sensors (r=8.0 cm) 24
Final sensors (Inner ladders) 100
Final sensors (Outer ladders) 300
Event format overhead TBD
Average Pixels / Cluster 2.5
Average Trigger rate 1 kHz
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DDLController
USBController
Command decoder
Event builder
Frame FIFO
ADC LVDS SPARE IO
SRAM controller
Global control register(access every module)
TemperatureADC
Internal processor(contact outside by SPARE IO)
TCD
This is the block diagram of firmware structure of pixel readout boardThick arrow means connection to outside of FPGABlock which connects to outside of FPGA includes IO pins and controller.Cross lines denotes NO connection.
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