sprinkler buddy presentation #5: “transistor level schematics and another floor plan” 2/21/2007...
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![Page 1: Sprinkler Buddy Presentation #5: “Transistor Level Schematics and Another Floor Plan” 2/21/2007 Team M3 Sasidhar Uppuluri Kalyan Kommineni Kartik Murthy](https://reader030.vdocuments.us/reader030/viewer/2022032800/56649d395503460f94a13344/html5/thumbnails/1.jpg)
Sprinkler Buddy
Presentation #5:
“Transistor Level Schematics
and Another Floor Plan”
2/21/2007
Team M3Sasidhar UppuluriKalyan Kommineni
Kartik Murthy Panchalam Ramanujan
Design Manager: Bowei Gai
“Low Cost Irrigation Management For Everyone ! ”
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Current Status Determine Project Develop Project Specifications Plan Architectural Design
Determination of all components in design Detailed logical flowchart
Design a Floor Plan (refined again)
Create Structural Verilog Make Transistor Level Schematic (some control issues)
Layout Testing (Extraction, LVS, and Analog Sim.)
![Page 3: Sprinkler Buddy Presentation #5: “Transistor Level Schematics and Another Floor Plan” 2/21/2007 Team M3 Sasidhar Uppuluri Kalyan Kommineni Kartik Murthy](https://reader030.vdocuments.us/reader030/viewer/2022032800/56649d395503460f94a13344/html5/thumbnails/3.jpg)
Floor Plan Old (Naïve) Floor Plan
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Somewhat Better Floor Plan
![Page 5: Sprinkler Buddy Presentation #5: “Transistor Level Schematics and Another Floor Plan” 2/21/2007 Team M3 Sasidhar Uppuluri Kalyan Kommineni Kartik Murthy](https://reader030.vdocuments.us/reader030/viewer/2022032800/56649d395503460f94a13344/html5/thumbnails/5.jpg)
Last Week’s Floor Plan
![Page 6: Sprinkler Buddy Presentation #5: “Transistor Level Schematics and Another Floor Plan” 2/21/2007 Team M3 Sasidhar Uppuluri Kalyan Kommineni Kartik Murthy](https://reader030.vdocuments.us/reader030/viewer/2022032800/56649d395503460f94a13344/html5/thumbnails/6.jpg)
This Week’s First Try
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Current Floor Plan
![Page 8: Sprinkler Buddy Presentation #5: “Transistor Level Schematics and Another Floor Plan” 2/21/2007 Team M3 Sasidhar Uppuluri Kalyan Kommineni Kartik Murthy](https://reader030.vdocuments.us/reader030/viewer/2022032800/56649d395503460f94a13344/html5/thumbnails/8.jpg)
Individual Modules:
Block Metal Layers That Can be Used
40:20 Muxes M1 & M2
60:20 Muxes M1 & M2
Counters M1 & M2
KC ROM M1 & M2 & M3 & M4
P ROM M1 & M2 & M3 & M4
Metric Storage SRAMS M1 & M2 & M3 & M4
Constant Storage ROM M1 & M2 & M3 & M4
Floating Point Adders M1 & M2 & M3
Floating Point Multipliers M1 & M2 & M3 & M4
10 Bit Registers M1 & M2
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Transistor Count …
Block (# used) Old TC New TC
40:20 Muxes (6) ~480 362
60:20 Muxes (2) ~720 644
Counter (2) ~250 220
KC ROM (1) ~778 1256
P ROM (1) ~82 122
Metric Storage SRAMS (2)
~2522 2430
Constant Storage ROM (1)
~202 428
Floating Point Adder (4)
~3000 3210
Floating Point Multiplier (2)
~2800 1398
10 Bit Registers (9)
~140 210
Datapath Logic / Misc.
~2000 2305
Total =
30,397
![Page 10: Sprinkler Buddy Presentation #5: “Transistor Level Schematics and Another Floor Plan” 2/21/2007 Team M3 Sasidhar Uppuluri Kalyan Kommineni Kartik Murthy](https://reader030.vdocuments.us/reader030/viewer/2022032800/56649d395503460f94a13344/html5/thumbnails/10.jpg)
New Design SizeBlock (# used) Size Estimate (um)
40:20 Muxes (4) 20 x 80
60:20 Muxes (2) 20 x 120
Counter (2) 12 x 17
KC ROM (4 parts) 181 x 8
P ROM (1) 70 x 8
Metric Storage SRAMS (2)
181 x 60
Constant Storage ROM (1)
181 x 8
Floating Point Adder (4)
100 x 100
Floating Point Multiplier (2)
95 x 125
10 Bit Registers (8) 50 x 10
• 457um x 391 um• ~ 1 : 1.16 aspect ratio• .178 mm^2 area• .168 Transistor Density
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Schematics: SRAM
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Schematics: Flip Flops
![Page 13: Sprinkler Buddy Presentation #5: “Transistor Level Schematics and Another Floor Plan” 2/21/2007 Team M3 Sasidhar Uppuluri Kalyan Kommineni Kartik Murthy](https://reader030.vdocuments.us/reader030/viewer/2022032800/56649d395503460f94a13344/html5/thumbnails/13.jpg)
Schematics: Read & Write to SRAM
Read
Write
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Schematics: ROMs
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Schematics: FP Units
Multiplier Adder
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Schematics: Control
Hourly Update FP Adder
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Design Challenges and Implementation
DecisionsFor The Past Week
Design Challenge
Translation to HW
Low Power Design
• Logic Reduction • Sizing of Gates According to Logical Effort
![Page 18: Sprinkler Buddy Presentation #5: “Transistor Level Schematics and Another Floor Plan” 2/21/2007 Team M3 Sasidhar Uppuluri Kalyan Kommineni Kartik Murthy](https://reader030.vdocuments.us/reader030/viewer/2022032800/56649d395503460f94a13344/html5/thumbnails/18.jpg)
Problems/QuestionsSmall Problems with Control Logic in
Schematic Can we reduce more transistors with
better logic ? Any way to move the SRAM from the
middle of our chip?
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For Next WeekPerfect our Control Logic in the
Schematic Continue to reduce and optimize gates Start Layout !
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Some Other SlidesFor Reference…
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Block Size Estimates
Block (# used) Size Estimate (um)
40:20 Muxes (4) 20 x 80
60:20 Muxes (2) 20 x 120
Counter (2) 12 x 17
KC ROM (4 parts) 181 x 8
P ROM (1) 70 x 8
Metric Storage SRAMS (2) 181 x 60
Constant Storage ROM (1) 181 x 8
Floating Point Adder (4) 100 x 100
Floating Point Multiplier (2) 95 x 125
10 Bit Registers (8) 50 x 10