George Mason University Volgenau School of Engineering

Senior Design Project 2012

JACOB DILLES, PM!JASON HARTMAN!MARY HATFIELD!KEVIN NICOTERA!ELTON WILLIAMS!

DR. QILIANG LI, ECE SUPERVISOR!DR. MINGZHEN TIAN, PHYSICS SUPERVISOR!DR. PIOTR PACHOWICZ, COURSE COORDINATOR!DR. PELIN KURTAY, ASSOCIATE CHAIR!

Senior Design Project 2012

TEAM SPECTRUM!

In Progress Presentation

!" OSA = Optical Spectrum Analyzer !" We have spectrum analyzers to show:

!" Audio: up to !40kHz (10^4) !" RF: up to several GHz (10^9)

!" Optical frequencies: THz (10^15!) !" Can’t transduce these frequencies directly !" Need to shift optically

Can’t transduce these frequencies directly Need to shift optically

!" Scanning Fabry-Pérot Interferometer !" Two Mirrors = Optical Resonance !" Distance between sets 0

!" Piezoelectric motor (AKA PZT) “tuning”

!" ‘Q’ " ‘Finesse’ , Photo detector out

!" FSR mirror distance, c/2L !" Fixed mirror distance: peaks every FSR !" Moving mirrors (L): peaks every FSR

!" Fabry-Pérot OSA components: 1." SFPI: Maps I(!) " V(V) 2." Controller Ramps the SFPI 3." Measures and Display Output

The Digital OSA Controller (DSC) provides !" Numeric control over PZT voltage (DAC) !" Sampled photo detector signal (ADC)

Benefits include: !" No oscilloscope required, lower cost !" Computers are fast:

!" Real time DSP to clean up signal !" Convert units on the fly for display

!" Modernize the user experience.

1." Replicate existing functionality 2." Provide additional value !" Accuracy !" Data capture !" Usability

3." Reduce cost

Revision 5 2012 03 02 1647

Top Level Functions

• SFPI Control and Input Amplification• Signal Conditioning and Processing• Handle User Interaction:

- Select Displayed Data - Display Selected Data - Store Selected Data

• Automate: - Gain Control (AGC) - Window stabilization (anti-drift) - Unit conversion (FSR calculations)

SFPI Cavity

Piez

oele

ctric

Mot

or

Phot

odio

de

0-500V DC RampHV-BNC-F

BNC-FSmall Signal

OSA Controller - Level 0

Display PlotUser Input

Human

Persistant Storage

.CSV

!" USER INTERFACE MODULE (UIM) – USB to computer and hardware GUI

!" DATA CONTROL MODULE (DCM) – System controller; connects other modules, produces output, processes input.

!" INPUT PROCESSING MODULE (IPM) – Transimpedance amplifier for photodiode detector, 20 MHz ADC & filter.

!" SFPI OUTPUT MODULE (SOM) – Low noise, high accuracy DAC converter, HV (500V) supply & amplifier.

!" CHASSIS – Hardware and enclosure, mains power supply. Study, compact package suitable for daily use in a lab environment.

SOM(SFPI OUTPUT MODULE)

- Low noise DAC - HV (500V) amplifier - Safety Interlocks

IPM(INPUT PROCESSING MODULE)

- Detector amplification - High speed ADC - AGC hardware

UIM (USER INTERFACE MODULE)

- Handle user input - Plot selected data - Export CSV data - Unit conversion calculations - Window stabilization - Store configuration settings

AC Mains

Revision 3 2012 03 02 1648

CHASSIS

- Power supply - Enclosure Hardware - User Interface Mounting

Motor Position& Control

Detector Amplitude Processed Data

Power Supply

0-500V DC Ramp

HV-BNC-F

BNC-F

Small Signal

SFPI Motor

SFPI Detector

Status

Control

Control

DCM(DATA CONTROL MODULE)

- Function generation - Sample Aggregation - Real time preprocessing - Data buffering

Display PlotUser Input

Human

Persistant Storage

.CSV

OSA Controller - Level 1

Our project covers a wide range of technologies: HV DAC, RF Small Signal ADC, GTK/C Embedded DSP, USB, GUI and FS Storage

Human

0-500V DC Ramp

HV-BNC-F

BNC-F

Small Signal

OSA Controller - Level 2

PD Amp Analog to Digital (ADC)

HV Amp Digital to Analog (DAC)

Ramp & FunctionGenerator

Sample Processing

Unified ClockDivider

Sample Aggregation

Scan Buffer

Window Selection

DSP/ Render

AA LPF

LPFCrowbar andDisconnect

Gain Selection

GUI

Persistant Storage

CalibrationReference/Disconnect

ModeSelectionSFPI Motor

SFPI Detector

Revision 5 2012 03 02 1658

SOM

IPM

HV Monitoring

DCM UIM

Human

Window Selection

DSP/ Render

Gain Selection

GUI

Persistant Storage

ModeSelection

UIM

Kevin Nicotera, Module Manager

#"Embedded User Interface (UIM-E) #" LCD, LCDA #" Numerical Keypad, Five Buttons #" Two Rotary Encoders #" SD/MMC reader, and USB port #" Propeller Microcontroller, Raspberry Pi #" Sturdy, standard 19” rack mount enclosure #" Power: 12VDC @ 2A

!" 30-second hardware demo of what the UIM-E does

#"Software User Interface (UIM) #"1385 SLOC in C, gtk GUI interface #"Multithreaded GTK GUI #"USB communication w/UIM-E via libFTDI #"USB communication w/DCM via

libFPGAlinkData #"Real-time graph manipulation w/gtkDataBox #"Configuration and Settings windows #"Cross-platform code: tested x86 and ARM

architectures

Design

REV 0 - 2012.02.26

MODE AUTOOFF 312VEXP 63VCONF 94%FSR 1.5G

RUN - 5 Hz40 MHz / DIV

RUN/STOP

50µA / DIV

AUTO FSR

PEAK SNAP

CURSOR

AQUIRE

Implementation

!" UIM-E interface has been extensively tested !" All buttons are responsive and de-bounced !" Communication protocol is reliable over

extended durations !" Proof-of-concept test with FPGA

communication !" Need DCM implementation for actual testing

!" Development testing of software !" Timing simulations of graphing system

!" Interface Raspberry Pi with Hardware !" Used a Parallax Propeller Microcontroller to

handle low-level chores !" Communicate with Propeller via USB

!" Plot large amounts of data quickly !" Found GTKDatabox library, designed

specifically for this purpose !" Interfacing was a challenge, large effort

required

!" Scaled rotary encoder movement !" Fixed by each rotary encoder click equates

to one pixel on the graph (always constant movement no matter how many points of data)

!" CPU usage on Raspberry Pi !" Overclocking Raspberry Pi and

multithreading the user interface helped (still needs work)

!" Required: !" Save user defined settings and data !" Implement/test FPGA communication !" Improve real-time graphing algorithm !" Improve overall performance

!" Optional: !" Save user defined settings and data to USB/

SD card

Analog to Digital (ADC)

Digital to Analog (DAC)

Ramp & FunctionGenerator

Sample Processing

Unified ClockDivider

Sample Aggregation

Scan Buffer

Window Selection

DSP/ Render

ModeSelection

DCM UIM

IPM

SOM

Jason Hartman, Module Manager, DCM

#"Spartan 6 on Digilent Atyls board #"Integrated USB Connection to UIM #"16-bit Parallel connection to IPM on VHCDI

breakout board #"8-pin PMOD connection to SOM (blackbox) #"Power: 5VDC @ 4A

Hardware Breakdown

VHCDI Breakout

IPM ADC

Spartan 6 FPGA

#"Phase I/II Control Implementation #"2542 VHDL SLOC (including test benches) #"B-RAM based FIFO #"Register-based control #"FX2 USB interface to UIM

!" UIM and DCM connection has been tested with libFPGAlink sample code

!" Each component, including the top-level, was individually test benched in Xilinx ISE

!" Top-level component synthesized, and loaded

!" libFPGAlink poorly documented on the VHDL side !" Have not had successful communication with

“real” UIM !" Needs work

!" Memory Controller is Very complex !" Using B-RAM FIFO as a stop-gap until DDR2

FIFO is implemented

!" Memory Controller !" Requires interfacing Spartan 6 DDR2

memory with the current developed modules for the FPGA

!" Should take approximately 10 hours, very feasible

!" No alternatives exist due to the fact that the amount of data we will be dumping to the FPGA memory exceed the Spartan 6’s non memory resource allocation

Elton Williams, Module Manager, IPM

BNC-F

Small SignalPD Amp Analog to

Digital (ADC)AA LPFCalibrationReference/Disconnect

SFPI Detector

IPM

Sample Processing

!" LTC2203 (25 MSPS) Demo Board !" Came with DS919 USB test interface !" Works as specified

!" Photodiode (Transimpedance) Amplifier !" 4-bit 65-122dB Variable Gain !" End-to-end Original Design: !" Theory, Calculations, Simulation, PCB

!" All the stuff you teach us… actually works!?!

!" Original design from S12 (LT1226) did not function as expected !" Completely unstable under all conditions !" Back to the drawing board!

!" No good reference design exists for what we are trying to build !" Extensive research was required to

synthesize a solution from scratch

Three prototypes did not operate as predicted by SPICE Three prototypes did not operate as predicted by SPICE

!" Several issues were identified: !" Unexpected capacitive loading of the input:

RG-58 cable, BNC connectors, even the metal optics table. Order of magnitude off of initial estimate (600pF vs. 20pF)

!" PCB Parasitic are a HUGE concern for high-gain, high-bandwidth amplifiers

!" Required a more accurate SPICE model

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!" Arduino was used to set gain steps !" Diode laser and IR photodiode !" Test Results Indicate:

!" Predicted gain exceeded by 47%. Could be due to inaccurate current measurement

!" Very linear gain – R2 99.8%+ !" MSBit on V+ burned out !" Have extra PCB/Switches

y = 90048x + 18833 R" = 0.99887

0.00

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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Gai

n, k

V/A

Gain Step (4-bit)

kV/A+

kV/A-

kV/A(V#)

SPICE

Linear (kV/A(V#))

!" Mount in enclosure: !" Test RF shielding

!" Low Priority: !" Build second PCB for working V+ Bit 3

!" Integrate control with FPGA

Mary Hatfield, Module Manager, SOM

0-500V DC Ramp

HV-BNC-FHV Amp Digital to

Analog (DAC)LPFCrowbar andDisconnectSFPI Motor

SOM

HV Monitoring

Ramp & FunctionGenerator

!" LV circuit hardware completed !" PCB layout from last semester built !" On-board voltage supplies operational

!" HV unit 90% completed !" HV-HV section wired, HV-LV in progress

!" Several problems identified with PCB, after it arrived

!" Major issue was power supply trace in contact with ground plane !" Fix was to cut around the area with Dremel tool

and use a jumper wire to connect the trace !" Pad layout for DAC was too narrow

!" Fix was to fold leads under SOIC before soldering

!" Resistor numbering not consistent !" Fix: verify layout against schematic and note

errata to assist during soldering

!" Surface mount LED package polarization was different for each color. !" Each datasheet was printed and marked with

the corresponding color. !" Takeaways:

!" Triple check PCB before shipping it out! !" Triple check datasheet, assume nothing!

Implemented Safety Features: !" “Deadman” 5kV-rated vacuum relay physically

disconnects HV output from amplifier and shunts to ground

!" SCR Crowbar to discharge stray capacitance faster than relay (up to 50A/µS)

!" HV Best Practices used throughout construction – 1000% safety margin minimum

!" Low voltage fusing to protect 48V DC supply

!" Op amp section of LV circuit simulated in software

!" HV amplifier tested prior to constructing HV assembly

!" Need to develop software for microcontroller or develop alternative control solution before progress can continue !" Must implement I2C for programming DAC !" Must specify and implement protocol for

communication with DCM !" This is a challenging task

!" One transistor remains in the HV circuit !" Needs to be installed before HV testing

!" Testing SOM-LV

Jacob Dilles, Project Manger

#" Mount Points for Modules: #"UIM (&Screen/buttons) #"DCM (Demo board) #" IPM (custom PCB) #"SOM (custom PCB)

#" Provide DC power #"UIM – 12V 120W #"DCM – 5V 20W #" IPM – +5V 1.5A #"SOM - +12, +5, 48V

#" Fabricated Enclosure #"Rugged #"Bench Equipment “Feel”

#" COTS 48V 500W SMPS #" Linear regulators for

analog small signal #" COTS ATX Power for

all other needs

!" Total Labor: 400-420 Hours !" 5 Team Members !" 8 Team Meetings After & Including 31 August !" 5-8 Hours per meeting, plus individual time

!" Budget: !" $3,174.13 Spent !" $1,825.87 Remaining !" Under budget

Requirement Definition

P1

System Design/

Functional Partitioning

P2

Interface Deffinition/

Module Identitfication

P3

Research/Component Evaluation

P4

Module Design Documentaiton

P5

Design Review

P6

Project Proposal

P7

Initial Test Plan

T1

Test Design Docs

T2

Spring

Subo

ptim

al D

esig

n

Inte

r-mod

ule

issu

es

Technical Design

P8

Simulation/Verification

P9

PCB Layout/BOM

P10

Final Review

P11

Acquisition/Fabrication

P12

Test Tech Design

T3

Test Build

T4

Test Review

T5

Module Testing

I1

Integration

I2

System Testing

I3

Deliverable Prototype

I4

Fall

Epic

Failu

re

Fail

Layo

ut E

rror

Fab

Erro

r

Build

Erro

r

Integration

I2

System Testing

I3

!" Integration !" IPM to DCM !" SOM-HV to SOM-LV !" SOM-LV to DCM !" DCM to UIM

!" Testing !" DCM !" SOM-LV

!" Documentation

JACOB DILLES, PM!JASON HARTMAN!MARY HATFIELD!KEVIN NICOTERA!ELTON WILLIAMS!

DR. QILIANG LI, ECE SUPERVISOR!DR. MINGZHEN TIAN, PHYSICS SUPERVISOR!DR. PIOTR PACHOWICZ, COURSE COORDINATOR!DR. PELIN KURTAY, ASSOCIATE CHAIR!

TEAM SPECTRUM!

THANK YOU!!