spatially lowpass 2d filter
TRANSCRIPT
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FPGA implementationof a rst order 2-D IIR
beam lterSIJI P V
AECENo!"
G#ided $%&
Dr' (an)#(an#el
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IN*R+D,C*I+N
• Signals emitted from sources far away from thereceiver can be approximated as spatio temporal plane
waves (STPW) at the receiver.
Beamforming
• ighly selective enhancement of desired STPWs
according to their directions of arrival (!"#).
• Spatio$temporal plane wave filters are used .
• as applications in wireless communications% biomedical imaging% seismic signal processors%
directional audio systems.
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Spatio-temporal plane wave filters
• &$! '' beam filter
• an be reali*ed using a first$order resistively terminated
passive prototype &$! networ+.
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C+N*ND''
(i) &$! s$domain transfer function
&$! fre,uency response transfer function
&$! z $domain transfer function
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C+N*ND''
(iv) -agnitude fre,uency response
• 2-D Input–Output Difference Equation
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Filter Ar./ite.t#re
• The &$! space$time input$output direct form differencee,uation is used for real$time hardware implementation.
• ardware implementation Systolic array architecture
Why systolic array architecture/• igh$speed plane$wave filtering re,uires a throughput of
one frame per cloc+ cycle ("0P) and very low critical
path (P) delays for fast real$time operation.
• Systolic array architecture has a throughput of "ne0rame Per loc+ ycle much lower critical path delay .
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C+N*ND''
(i) Overview of the architecture
(•)consists of an array of identical parallel processing
core$modules ( PP-s).
(•)1ach PP- is capable of producing an output sample
in one cloc+ cycle% therefore leading to a total
throughput of "0P.
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C+N*ND''
PP- hardware architecture
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S%stoli. Arra% Ar./ite.t#re
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REA0 *I(EI(P0E(EN*A*I+N
• !evice to be used 2ilinx 3irtex 4 2430256T$
7008779: (-;465) 0P8# device.
• 0P8# design tool $ 2ilinx System 8enerator (2S8)
• 3erification
• The correct operation of the &! '' filter is verified
by exciting the inputs of the filter by a &$! unitimpulse function and measuring the impulse response
from the onchip reali*ations
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DESIGN F0+1
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PR+P+SA0S
• ardware reali*ation of first order &$! '' beamfilter on 2ilinx 3irtex 4 2430256T$7008779:
(-;465)0P8# device .
• omputational complexity reduction by representingmultipliers in Signed Power of Two (SPT) space.
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C+NC0,SI+N
• Systolic implementation of a &$! '' fre,uency beam
filter transfer function has promising engineering
applications for the directional enhancement of a
propagating broadband space$time plane wavereceived on an array of sensors.
• Systolic array architecture is capable of processing
one frame per cloc+ cycle("0P) and has low P
(enables high$ speed real$time operation).
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REFERENCES
• #. -adanaya+e and ;. T. Bruton% 49?7>::% #ug. &66@.
• -. 8havami and . Aohno%
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Contnd'
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C+N*D''