sony dx 1a troubleshooting manual

S® Training Manual

Circuit Description and Troubleshooting

Course: DTV-02

Direct ViewTelevisionDX-1A ChassisModels: KV-32XBR400

KV-36XBR400

Introduction 2

DTV Converter Boxes 3

USA Analog Transmission Format 3

USA Digital Transmission Formats 5

Digital TV (DTV) Converter Boxes 5

New Features 9

Overall Block 11

SD to HD Conversion Concept 15

Video Block 21

Picture with Picture 27

Power ON Block 29

Power Supplies 29

Standby Power Supply 29

Primary & Secondary Power Supplies 29

Primary Power Supply 31

Start Up 31

Regulation 31

Testing 33

Secondary Power Supply 35

Start Up 35

Regulation 35

Table of Contents

Testing 35

Horizontal Drive / H Pincushion Correction /Filament Voltage 37

Basic Horizontal Drive Circuit 37

PMW Circuit 37

Filament Voltage 39

G2 Circuit 41

HV Converter Block 43

Start Up 43

Protection / Shutdown 43

HV Adjustment 43

Testing 45

Communications 47

Dynamic Focus Block 51

Static Focus Concept 51

Dynamic Focus Concept 51

Circuitry 51

Adjustment 55

DQP Circuit Corner Focus Correction 57

Convergence Circuit 61

Concept 61

Circuitry 61

Adjustment 61

Picture Tilt Correction 63

Vertical Pincushion Correction Circuit 65

Concept 65

Adjustment 65

Vertical Process 67

Audio Block Diagram 71

Features 71

Signal Path 71

Self Diagnostic Block 73

Self Diagnostic Circuit 75

Appendix

Service Mode Display i

Digital Satellite System Converter Box ii

DTV Set Top Box iii

IEEE-1394 iv

DX-1A Chassis Assembly vii

Board Replacement viii

HV Adj. check Bulletin 492 ixi

1

NOTES

2

IntroductionThis model KV32XBR400 is a high resolution TV designed to bridge thegap between the current analog TV sets and the forthcoming high defini-tion digital TV (HDTV) sets. This set can accept the current standardresolution NTSC TV transmissions, DVD, VHS, and Camcorder video sig-nals, convert them, and display them on a high-resolution TV screen. Anexternal set top converter box is necessary to receive Digital TV pro-grams.Related Models

DX-1A TV Chassis Models

Model Screen size AspectRatio

MSRP

KV32XBR400 32 diagonal 4:3 $1999.99

KV36XBR400 36 diagonal 4:3 $2499.99

Higher Resolution Inputs

This TV can also accept standard resolution 480p or high resolution 1080ivideo signal formats from an external HDTV, satellite, or cable converterbox as component video (Y, Pb, Pr) inputs. These 480p and 1080i sig-nals can have a wide 16:9 aspect ratio. If they do, the display will be inletterbox format with black above and below the picture on the 4:3 aspectratio picture tube of these TV sets.

Only the Digital TV’s 720p resolution video format cannot be displayed onthis set. The picture will not be synchronized.

KV32XBR400 / KV36XBR400Inputs

Name Format Source

RF NTSC VHF, UHF, Cable

Video 1-4 +

Stereojacks

S or Composite video:

Standard resolution 480interlaced lines (480i).

Video tape recorder,camcorder, DVDplayer, TiVOrecorder

Video 5-6 +StereoJacks

Component video: StandardResolution 480i, 480p orHigh Resolution 1080i format

DTV, Satellite, orCable Converter box

Control S Sony Audio Equipment

Circuitry Information

The power consumption and self-diagnostics remain the same as otherSony TVs. This set’s change to high-resolution video results in circuitrychanges to the video processing, horizontal frequency (fixed at 33.75kHz),and high voltage generation.

Power Consumption at 120Vac

Snow Dark screen/video 1 Surge

1.2 A 1.1 A 6 A (degaussing)

General Servicing Information

Item Location Comments

SelfDiagnostics

Circuits on A & Dboards. Indicator onfront panel.

Standby/Timer LEDblinks to ID problemarea.

FilamentVoltage

From 7V, A Bd(Primary PS) and HOTtransformer, D Bd.

The CRT filamentvoltage comes from 2sources.

High VoltageConverter

D board near flyback AFC signal from HOTturns ON HV Converter.

G2 (Screenadjustment)

On the CRT board Adjustment is in theboard replacementguide (appendix).

Focus Control On the FBT Adjust for sharp picturecenter and sides

Filament Voltage - This CRT voltage comes from two sources:• Unregulated 7V supply from the Primary Power Supply on the A board(used as a preheat).

• The HOT (horizontal output transformer) after a 6Vdc regulator on theD board (main filament voltage supply).

High Voltage Generation - An independent HV oscillator circuit with aspecial high frequency flyback transformer regulates the HV to 31.5kV.The HV converter stage is turned on only after the Horizontal drive signalfrom the HOT is detected.

3

MonitorSpec

1024

1800

1024 x 1800 pixels

X

TVSpec

1080 x 1920 lines

X

Interlaced Scan

Field 1 + Field 2 = Frame

Progressive Scan

Field 1 =Frame

DTV Converter BoxesIn order to compare converter box specifications you need to understandhow resolution is measured in the interlaced and progressive scan meth-ods. With this information you can also determine which one of the 18digital formats offers better resolution.

ResolutionThe two most popular methods of measuring picture resolution are inpixels (dots) or in lines. Incremental dots called pixels are often associ-ated with monitors. Lines of resolution is a measurement for TVs. In themonitor specifications, the number of vertical pixels is listed first. In theTV specifications, the number of horizontal lines is listed first. For theseexamples of specifications, a high-resolution monitor and (digital) TV stan-dard were chosen:

Although the semantics are different (vertical pixels/horizontal lines), thefirst number in both specifications is the maximum number of black towhite transitions that can occur as you count from the top of the screen tothe bottom.

In the current NTSC (National Television Standards Committee) TV trans-mission standard, 525 horizontal lines are transmitted but only about 480lines are visible. This is because the vertical blanking area above the

picture is not seen and the picture is normally over-scanned (larger thanthe TV screen). Therefore, the TV resolution is said to be “480” (horizon-tal) lines instead of the transmitted 525 lines.

USA Analog Transmission FormatInterlaced and Progressive ScanningIn the NTSC television transmission format a complete picture (frame)consists of two pictures (fields) interlaced together. Each half picture is afield of 262.5 scanned lines. Therefore a complete picture is 262.5 x 2 =525 lines. The two scanned fields are interlaced so the second field of262.5 lines fits in-between the first field.

If a picture is not interlaced, it is a progressive scan image (not NTSCformat). This means the entire picture frame is presented in the first scanand a second picture is presented in the second scan.

30 or 60 Frames?

In the NTSC standard the first field takes 1/60 second to scan a screen of262.5 lines. Then a slightly smaller vertical sync pulse in the second fieldis created and the second picture field is shifted lower than the first to fitin-between. The second field also takes 1/60 sec., completing the entirepicture frame in 1/60 + 1/60 = 2/60 sec = 1/30 sec.

4

Analog

Mfg. Model

Ch 1-99 D

igital TV

Ch 1-125 C

able DT

V *

Ch 2-69 A

nalog TV

Sm

all dish Satellite

RF

(Ch 3/4)

Com

p Video

S V

ideo

Y, P

r, Pb

RG

B,H

,V **

Form

at (# Horiz lines)

L & R

Optical

Coax

IEE

E 1394

RCA DTC-100 X X X X X X X VGA 1080i/540p X XPanasonic TU-HDST50 X X ? X X X 720p X X

TU-HDS20 X X X X ? X X X BNC ? X XPioneer SH-DO7 X ? X 1080i *** X X X

SH-D505 X X ? X X X BNC 1080i/ X X X720p/480p

Mitsubishi SR-HD400 X X X X X X X X ? X XSR-HD500 X X X X X X X X ? X X

Sony DTR-HD1 X X X phono 1080i X XSAT-HD100 X X X X X X VGA 1080i/480p X X

Sharp TUDTV1000 X X X X X VGA/ 1080i/480p X X XBNC

Proscan PSHD105 X ? ? X X X X VGA 1080i/540p X XSamsung SIRT100 X ? ? X X X X ? 1080i/480p X X

* DTV must be 8VSB modulation (like terrestrial ATSC DTV transmissions)X = Yes ** VGA = computer monitor jack (15 pin D type) ? = insufficient information BNC = BNC connectors, one for each of the signalsblank = No *** Connection to Pioneer model PRO-700HD TV only.

Digital Audio Output

DTV Set Top Converter Boxes (as of July, 2000)

Standard Resolution High ResolutionVideo Output

RF Inputs

5

Method 2Letterbox

Entire16x9Picture

��

��

30I Picture Format

= 2/60second or1/30

1/60 sec.Field 1

1/60 sec.Field 2

+

4

3

16

9

Method 1Cropping

ShadedareaCropped/removed

Centerof 16 x 9picture

��

��

The NTSC format is commonly written as “30i” picture format because ittakes 1/30 of a second to complete an interlaced picture.

Aspect Ratio

Although the first pictures were round, later TV pictures adopted a rectan-gular shape. The aspect ratio of these pictures is the same as they aretoday, 4 x 3 ratio.

Movie theaters show films in a wider 16x9 aspect ratio. This 16x9 pictureis also the way most films are shot. To present the original 16x9 pictureon a 4x3 TV screen, one of two common methods is adopted to fit thepicture:

In method 1, the 16x9 picture is cropped or cut off at the left and right. Themain action part of the picture (usually the center or near center) is theonly part transmitted.

In method 2, the 16x9 picture is shrunken and placed on the TV screen.The entire picture is seen but with black areas above and below the pic-ture. This method of viewing the entire 16x9 picture on a 4x3 set is calleda Letterbox picture. Letterbox pictures can be selected on some DVDplayers and TV sets from the menu if the DVD or TV transmissions offerit.

USA Digital Transmission FormatsThere are 18 digital transmission formats approved by the ATSC (Ad-vanced Television Standards Committee) in the USA. The first six offerHD (high definition/resolution) signals in a 16x9 aspect ratio. The remain-ing 12 formats are SD (standard definition) signals in progressive (p) orinterlaced (i) scan. Note that the 480p signal can be a 4:3 or 16:9 aspectratio transmission.

18 Digital Transmission Formats

Resolution AspectRatio

Frame Resolution AspectRatio

Frame

1. 1080x1920 16:9 30 i 10. 480x 704 16:9 24 p

2. 16:9 30 p 11. 4:3 60 p

3. 16:9 24 p 12. 4:3 30 i

4. 720 x 1280 16:9 60 p 13. 4:3 30 p

5. 16:9 30 p 14. 4:3 24 p

6. 16:9 24 p 15. 480x 640 4:3 60 p

7. 480x 704 16:9 60 p 16. 4:3 30 i

8. 16:9 30 i 17. 4:3 30 p

9. 16:9 30 p 18. 4:3 24 p

A standard definition transmission contains less data, permitting spacefor another digital video stream to coexist on the same frequency (chan-nel). Therefore, a station can have more than one program stream on adigital channel. The maximum number of programs is six.

Digital TV (DTV) Converter BoxesTV broadcasters are transmitting their analog signals on one channel andtheir DTV signals on another. A list of their analog and digital channelassignments by state is located at www.transmitter.com.To receive a DTV station on an analog TV, a set top converter box isused. The box receives digital RF and outputs analog composite video tothe TV. The boxes can also output higher resolution video signals to ahigh-resolution analog TV. These cable boxes are flexible at their inputand outputs:

6

RF inputs:Channels 1-99 Digital TV

The TV converter boxes listed in the chart all decode DTV signals from offthe air (terrestrial) in the USA and Canada. These TV stations conform tothe DTV ATSC format that approves an 8VSB modulation method. Thenew digital channel numbers are frequencies within the current analogChannels 2-69.

Ch 1-125 Cable DTV

At this time some cable TV companies are providing DTV service using8VSB modulation and other cable companies sell DTV service using QAMmodulation. The 8VSB modulation means this method is probably thesame as the off the air ATSC (DTV) signal. This means if the DTV con-verter boxes can receive the cable band, they can decode the cable DTVsignal. Cable companies using a QAM (Quadrature Amplitude) Modula-tion method require their DTV boxes for processing.

950-1.45GHz Satellite

In competition with cable companies are Direct Broadcast System (DBS)companies that provide satellite TV channels. The larger analog signalDBS dishes that operate on the ”C” band were not as popular as thesmaller “Ku” band digital signal dishes. A satellite manufacture can eitherprovide the TV service directly to the consumer, rent transponders (space)to other providers, or both. Some of the larger companies are:

Satellite Manufactures Providers

GM Hughes Electronics

EchoStar/Dish Network (HD 1080i) Direct TV

DBSC (Direct Broadcast Satellite Corp) PrimeStar

Direct Sat

Tempo

ACC (advanced Communications Corp)

Satellite reception is vulnerable to rain scattering the signal and the sun’smicrowave energy overpowering the satellite signal. The solar outagesmay occur only for minutes during the time span of a week or two duringthe spring and fall equinoxes. At these times the sun is behind the targetsatellite adding noise to the signal.

A few converter boxes can receive digital satellite signals. This combina-tion of DTV and satellite decoding in one box is feasible because thedecoding circuitry is similar. It is uncertain if these converter boxes candecode the new satellite high definition DTV signals.

Video OutputsThe converter boxes output standard resolution and high-resolution sig-nals. All the boxes can down convert a 1080, 720 or 480 line input signalinto a standard resolution 480i picture for an analog TV. This standardresolution output comes from the S or composite video jacks of the box.

For the higher resolution TVs that are coming out now, there is a compo-nent (Y, Pr, Pb) and/or RGB output from the box. The RGB +sync outputcould be five individual BNC jacks or a single VGA connector, such as theones found on the back of a home computer for its monitor.

After the correct mechanical connection is made, the signal format fromthe box must match that of the high resolution TV. The box’s outputsignal formats are menu selectable for box to TV compatibility. For ex-ample if the TV accepts 1080i signal format, the box’s output must corre-spond with the same output signal format.

If a 1080 format DTV signal is received, the box will convert it from an RFsignal, unscramble it, separate the audio, video and data, and thenuncompress the audio and video. The video will be changed into compo-nent video or RGB voltages that are input to the TV. The sync is on the Yline in the component video signal.

If a standard resolution 480 format DTV signal is received, the same sig-nal processing occurs but there is an additional scan converter to doublethe information before leaving as a 1080i format signal for the hich scanTV.

Audio OutputsAll the converter boxes have composite video output and correspondinganalog audio L&R channel outputs. Some boxes have digital optical and/or coax outputs for a Dolby AC-3 decoder (often in a receiver). Oneconverter box has an IEEE 1394 output for decoding the signal in a SVHS

7

recorder. The IEEE-1394 format is also called i.LINK, or Firewire ”because of the convenience or high speed. Customarily, both video andaudio is sent on this 4-wire cable. More about the IEEE-1394 format isfound in the appendix of this book.

Dolby is a registered trademark of Dolby laboratories.

Fire Wire is a trademark of Apple Computer Inc.

i.LINK is a trademark of Sony.

8

NOTES

9

Sony

FD

Glassscreen

Electron beam

Non-SonyPicture Tube

Main Pix

Favorite Channel Display

Preview

Channel Numbers

Letterboxpicture 16:9 Pix Black

border

New Features

FD Wega Picture TubeThe Sony flat screen picture tube is a full flat screen inside and outside.

Favorite Channel PreviewPressing the Favorites remote button reduces the main picture and dis-plays a small picture of another (favorite) station. As you move the joy-stick down the list of numbers, the preview picture changes to that station.Select that station by pressing enter.

New Picture Mode = ProThe basic video modes are Vivid for use in bright daylight, Standard forreduced brightness in the home, and Movie for evenings. The Pro videomode is new. This mode darkens the picture and centers its dark to brightoperating range for the widest dynamic picture swing. This mode is meantfor pro movie watchers in a darkened room where the subtle dark to graychanges are made evident. The video settings (picture, brightness, color,etc) can be changed in any mode.

Parent MenuThis allows the owner to block TV programs according to their content.Entering the owner’s four-number password enables viewing of the blockedprograms. The owner’s password can be cleared with the master pass-word 4357 (“HELP”). The owner’s password can also be reset from theservice mode by pressing 8, then enter.

Set Up Menu - 16:9 EnhancedA 480p input signal can be in 4:3 or 16:9 video format.

The wide 16:9 video format produces a picture on a 4:3 picture tube thatis too tall. From the Auto/ON/OFF selections of the set up menu, choose16:9 Enhanced = ON to reduce the vertical size of the picture so thepicture is the correct aspect ratio.

The “Auto” selection reduces the picture size if there is an ID-1 signal inthe vertical blanking area of the input signal. The ID-1 signal identifies thevideo signal as 4:3 or 16:9 format. Sony 16:9 camcorders insert the ID-1information into the video during recording.

Video Menu - DRC-MFSelect an Interlace or Progressive mode display from the Video menuunder “DRC-MF”. Interlace is selected when watching moving images.The Progressive mode is selected only when many non-moving imagesare displayed, such as text or a still photograph. Selecting the Progres-sive mode stops the flickering that occurs in an interlaced picture whenthe two interlaced fields are not exactly the same. This interlace/progres-sive is not an option with a 1080i input

10

NOTES

11

Top & bottomlines bowed in(exaggerated)

V PinDistortion

Overall BlockThe only conventional block within this TV is the vertical block. The re-maining blocks are different because this TV is a high-resolution type witha “Wega”® flat screen. Therefore, changes to the power supply, horizon-tal frequency, convergence, focus, and video processing support the im-proved picture.

Power Supply

The power supply is in three parts to divide the load on the boards:

Power Supplies

Board Purpose

Standby A Outputs Standby 15V, 7V, & 5V.

Primary PowerSupply

A Outputs Set 9V, Set 5V, & Set 3.3V to localparts on the A, B, & BD boards. OutputsPri-Pre 15V to start the Secondary PS.

SecondaryPower Supply

D Outputs +200V, +135V, +24V (audio), Main12V, Main 9V, & Main 5V to the D board.

The Primary power supply starts the secondary supply using a Pri-Pre15V line. Once the Secondary power supply operates, Main 9V outputsto start the horizontal and vertical oscillators in Y/C CRT Drive IC201.

Vertical Deflection

In some Sony TV sets, there is no V Drive output the Y/C IC until data andclock are input. Unlike these TV sets, this IC201’s vertical will outputwhen power is applied. The sync source is dependent upon whetherprogressive, interlace or a sub picture is chosen. The vertical oscillatoroutput is amplified by IC5004 on the “D” deflection board to drive the DYdeflection yoke.

Vertical Pincushion Correction

As the TV screen becomes larger, the yoke can not perfectly control thebeam at the screen perimeter. An additional coil on the top and bottom ofthe CRT neck assembly is fed V Pin correction signal from IC201 andIC5514. The additional coil eliminates any minor inward/outward bow atthe top and bottom of the picture.

Horizontal Deflection

The higher 33.75kHz horizontal frequency is made by IC201 and fed tothe H Drive/Output stage on the D board. The output stage is fed regu-lated voltage from the +135V Secondary power supply via the PWM cir-cuit of IC5002.

The horizontal drive stage not only supplies the H Deflection yoke (H DY)with scan voltage, but also supplies G2 and filament voltage for the CRT.A regulated +200V is also output to supply the RGB output amplifiers onthe C board.

Horizontal AFC pulses from this stage are needed by the convergenceand dynamic focus stages for sync. The AFC pulses are used to start theHV Converter.

HV Converter

Regulated HV and focus voltage is made by the HV Converter stage. Ituses +200V from the secondary power supply to run and AFC pulsesfrom the horizontal deflection stage to start.

Horizontal Pincushion Correction

To keep the lines at the left and right of the screen straight, an east/west(E/W) H pincushion correction signal is made in IC201. The E/W signal isused to modulate the PWM IC5002 that controls picture width. By chang-ing the width line-by-line, the left and right sides in the large picture can bestraightened.

H PinDistortion

Sides bowed in(exaggerated)

12

OVERALL BLOCK 19/2/00

IC3414SW

IC3303/IC3408

DRC/MID

IC3048SW

TUNERS

VIDEO 1-4

VIDEO 5-6

IC201Y/CCRT

DRIVE

Q5026-8,Q5035-6,

Q5030H DRIVE

H OUTPUT

IC5514V PINOUT

IC5004V OUT

IC5002PWM

IC5513,IC5515CONV.

IC5511DF/DQPCOILS

IC9001-3RGBOUT

IC8002HV

CONV.

PRIMARYP.S

IC701MAINuCOM

STANDBY

+135V

VTIM

E/W

CYINDY

VPIN

VID

SYNC480i

AFC

CRTFILAMENT

200VC BD.

COIL ONCRT

NECK

VDY FOCUS

VTIM(IC5513)

CRTCATHODES

PRE15V

SYNC

B BD.

200V

HDY

POWERON

+200V(HOT)

MAIN9V

480p

1080i

5V7V

C BD.

D BD.

A BD.

A BD.

IK

MAIN VOLTAGES12V,9V,5V,24V

+- 15V

SET VOLTAGES

9V5V3.3V

G2

48DTV02 1273

STBY15V

100V HV

SECONDARYP.S

IC707NVM

IC5501NVM

(D BD.)

D6530

340VDC

RGB

V DRIVE

H DRIVE = 33.75kHz

13

Convergence of the Three Beams

The good news is that the complex convergence signal is made in oneIC5513 and the signal is amplified in the second IC5515. The outputsignal drives a convergence yoke inside the main horizontal and verticaldeflection yoke. The convergence stage affects the beams at the perim-eter of the screen.

Dynamic Focus Correction

As a beam is deflected, the points of focus form a curve. The focus pointshave to be moved to match the flat screen of the TV. A signal from DFIC5511 modulates the DC focus voltage to prevent poor focus at the leftand right sides of the screen.

Video Processing

Standard Resolution Input – A standard resolution NTSC signal can beselected from either tuner or any video input. However, this high resolu-tion TV runs at a different horizontal frequency of 33.75kHz. To accept astandard NTSC signal (480i) that runs at 15,734 Hz, the video signal isimproved and the horizontal sync more than doubled.

The Digital Reality Creation Circuit (IC3303) analyzes each pixel of a lineto add another line. Therefore the DRC circuit doubles the number ofvideo lines of a standard NTSC signal. The DRC also doubles the hori-zontal sync frequency before passing the signal onto the MID circuit onthe same board.

The Multi Image Driver (MID) Circuit (IC3408) stores the lines and out-puts the signal based on a new horizontal frequency that matches the TV.At the higher frequency, the picture finishes before the scan. Blank linesare added as filler by this MID stage before leaving the board.

High Resolution Input - Video inputs 5 and 6 are for Y, Pr and Pb compo-nent signals only. They can be standard (480i) or high resolution (480p or1080i). The 480p signal is already high resolution at double the H freq soit need not go through the DRC circuit. It is switched directly into the MIDcircuit.

The high-resolution 1080i picture is at the same horizontal frequency asthe TV set (33.75kHz), so it does not go into the DRC or the MID circuit.The 1080i signal is switched directly to the Y/C CRT Drive IC201 on the Aboard.

Since the 1080i signal is a wide 16:9 ratio picture, it looks squeezed in ona 4:3 aspect ratio picture tube. To make the picture look correct, thevertical can be reduced using a “16:9 enhanced” menu command. Verti-cal reduction can be automatically done if there is a code in the verticalblanking area of the input signal called ID-1. This signal identifies theaspect ratio of the picture.

14

OVERALL BLOCK 19/2/00

IC3414SW

IC3303/IC3408

DRC/MID

IC3048SW

TUNERS

VIDEO 1-4

VIDEO 5-6

IC201Y/CCRT

DRIVE

Q5026-8,Q5035-6,

Q5030H DRIVE

H OUTPUT

IC5514V PINOUT

IC5004V OUT

IC5002PWM

IC5513,IC5515CONV.

IC5511DF/DQPCOILS

IC9001-3RGBOUT

IC8002HV

CONV.

PRIMARYP.S

IC701MAINuCOM

STANDBY

+135V

VTIM

E/W

CYINDY

VPIN

VID

SYNC480i

AFC

CRTFILAMENT

200VC BD.

COIL ONCRT

NECK

VDY FOCUS

VTIM(IC5513)

CRTCATHODES

PRE15V

SYNC

B BD.

200V

HDY

POWERON

+200V(HOT)

MAIN9V

480p

1080i

5V7V

C BD.

D BD.

A BD.

A BD.

IK

MAIN VOLTAGES12V,9V,5V,24V

+- 15V

SET VOLTAGES

9V5V3.3V

G2

48DTV02 1273

STBY15V

100V HV

SECONDARYP.S

IC707NVM

IC5501NVM

(D BD.)

D6530

340VDC

RGB

V DRIVE

H DRIVE = 33.75kHz

15

Field 1 Field 2

"6i" Interlaced Picture consisting ofalternating lines from fields 1 & 2

SD to HD Conversion ConceptThis TV has features designed to bridge the gap between the currentanalog sets and newer higher resolution digital TV sets. The KV32XBR400TV is a high resolution set capable of receiving the current standard defi-nition (SD) NTSC signal. The NTSC standard resolution of 480i lines isupgraded to a 960i (interlaced) or 480p (progressive) line picture, to becompatible with this TV. The user selects interlaced scan if there is mo-tion in the picture or progressive scan if there is a still picture signal inorder to stop interlace flicker. A higher resolution (480p or 1080i) signalthat does not need to be upgraded can be input to video 5 or 6 for ad-vanced placement in the video chain.

Interlaced or Progressive Scan

Most technical people do not know how many horizontal lines are presenton the screen in a single scan from the top of the screen to the bottom.The confusion about the number of lines shown at one time relates to thedifferent interlace/progressive scan modes.

In the progressive scan mode the entire picture is presented in one scanof the picture tube (left to right, top to bottom). In an interlaced scan theentire picture consists of two fields so the picture is presented in twoscans of the picture tube. The second field is displaced from the first sothe lines fit in-between each other making the completed picture:

The resolution of the TV picture is measured in horizontal lines of a com-plete picture followed by the letter for the type of scan (i or p). For ex-ample, the NTSC signal contains 525 horizontal lines. The number ofviewable lines is reduced to 480 because of the time required for V & Hretrace, creating a blanking area above and below the picture. Thereforethe standard resolution NTSC signal displays a 480i picture. 480 is the

number of lines in the total picture. The i suffix identifies an interlacedpicture. Since the picture is interlaced, there is only half the number oflines presented in a single scan. In this case, there are 240 lines dis-played in a single scan. This is equivalent to a 240p picture that displays240 lines in a single scan (480i is the same as 240p).

Similarly a 480p picture is like a 960i picture because both these picturespresent 480 horizontal lines per scan. This is important to understand asthe standard resolution NTSC picture is changed to a higher resolution inthe “DRC” video processing stage of this TV.

Standard Definition Video Input

The Tuner and Video 1-4 inputs accept only the NTSC 480i-line standarddefinition signal identified by the 15.75kHz horizontal frequency. The 480iinput signal is interlaced (i), consisting of two 240-line fields presented/scanned one at a time that total the 480 lines. Therefore a 480i NTSCpicture normally displays 240 lines each time the picture is scanned. TheNTSC signal passes through the DRC and MID circuits.

DRC Circuit

In this model KV32XBR400 high resolution TV, a single scan must con-tain 540 lines, more than double of a NTSC signal. The DRC circuit al-most bridges the gap between the 240 line input signal and the 540 lineTV requirement. The DRC circuit doubles the number of horizontal linesby analyzing the pixel data to construct new lines. Therefore the DRCcircuit brings the total line count from 240 to 480. The DRC circuit alsodoubles the horizontal frequency to 31.5kHz to support these lines.

In a single scan

=12i Interlaced scanpicture is 6 lines per field

6p Progressivescan picture

123456

16

SD TO HD CONVERSION CIRCUIT

IC9001-3RGB

OUTPUT

IC3303DRC

CIRCUIT

IC3048SW

IC3408,IC3410MID-XACIRCUIT

IC3414YUV

SWITCH

IC3603ID-1

DECODE

IC201Y/CCRT

DRIVE

TUNER/VIDEO

1-4STANDARD

NTSCRESOLUTION

VIDEO 5VIDEO 6

480i480p1080i

H + VSYNC

480i

480i

H + V

CRTCATHODES

VERTOUTPUTIC5004(D BD.)

OSD

CONT

Y, Pb, Pr

Y, Pb, Pr

DATA/CLKIICBUS

IICBUS

DATA/CLK

B BD. A BD.

C BD.

12DTV02

1080i

480p

10/2/00

VIDEO

Yo -7Cr-7Cb-7

17

Tuner

Video 1-4

480i

A/VSwitches

Progressive orinterlaced output

DRCcircuit

MIDcircuit

480p

960i

240/480lines

15.75kHz/31.5kHz

480lines

33.75kHz

ExpandVertical

480 active lines

540 lines

DRCcircuit

MID Circuit

480p

480i

960i

Progressive480p + 60 = 540p lines

ExpandVertical

960 active lines (2 fields)

1080 lines

540p

1080i

960i + 120 = 1080i lines

Interlaced

Adds 60blank lines/scan

Progressive Scan - In this example of the progressive scan video pro-cessing, an NTSC still picture signal is input from a DVD player (in pause).The user chooses progressive scan from the menu to reduce picture flicker.Flicker occurs in an interlaced picture when the two fields are not exactlythe same images. The flicker is more noticeable in the movement area(s)of the picture where the fields are different.

In the progressive scan mode the DRC circuit doubles the number of linesfrom 480i (actually 240 lines) to 480p to make the NTSC signal compat-ible with the TV.

Interlace Scan - In a second example of the video processing, an NTSCsignal with live pictures is input from an antenna. The user chooses theinterlace scan mode from the menu because of the moving images. Eachinterlaced field displays a slightly different transitioning picture makingmovement seem smoother.

In the interlaced scan mode the DRC circuit still must double the numberof lines to meet the TV’s 480-line/scan requirement. The resolution ischanged from 480i (actually 240 lines) to 960i (actually 480 lines) by theDRC circuit.

MID Circuit

Fortunately, the model KV32XBR400 TV’s horizontal deflection stage scansat a 33.75kHz rate to display high definition (1080i) video signals. How-ever The horizontal frequency output the DRC circuit is double that ofNTSC at 31.5kHz. This is slower than the KV32XBR400’s 33.75kHz rate.Since the TV scans at a faster rate than what is input, the picture is fin-ished faster, leaving blank lines at the bottom.

The MID circuit centers the picture by adding 30 blank lines above andbelow the picture (60 lines total). This simple method permits the TV tokeep the vertical frequency at 60Hz. Therefore the MID circuit increasesthe number of lines from 480p to 540p but these extra lines are blank.There are still only 480 active (picture) lines.

Vertical Expansion

To keep the 60 blank lines invisible, the vertical size is expanded slightly(picture overscaned) so the 480 lines fill the 4:3 aspect ratio screen. Thisis seen in the previous diagram where the 60 blank lines are shown (ex-aggerated) in black.

18


IC9001-3RGB

OUTPUT

IC3303DRC

CIRCUIT

IC3048SW


IC3414YUV

SWITCH

IC3603ID-1

DECODE

IC201Y/CCRT

DRIVE

TUNER/VIDEO

1-4STANDARD

NTSCRESOLUTION

VIDEO 5VIDEO 6

480i480p1080i

H + VSYNC

480i

480i

H + V

CRTCATHODES


OSD

CONT

Y, Pb, Pr

Y, Pb, Pr

DATA/CLKIICBUS

IICBUS

DATA/CLK

B BD. A BD.

C BD.

12DTV02

1080i

480p

10/2/00

VIDEO

Yo -7Cr-7Cb-7

19

MIDCircuitry

540p

480p4:3 pix

Adds 60blank lines

Vert sizeincreased

480 lines

High Definition 1080ipicture on the 4:3aspect ratioKV32XBR400 TV

16 : 9 ENHANCED (VERT REDUCTION)

High Definition Video Input

The Video 5 and 6 inputs can be standard or high definition format sig-nals. The MID circuit distinguishes the video format by their horizontalfrequencies:

Video 5 or Video 6 Input Formats Horizontal Frequency480i 15.734kHz480p (4:3 aspect ratio) 31.50kHz480p (16:9 aspect ratio) 31.50kHz1080i (16:9 aspect ratio) 33.75kHz

480p Picture Process

A high-resolution 480p-video format is detected by its horizontal frequencyand selected by the MID circuit for video processing. The resultant pic-ture appearance will depend upon whether the video format of the inputsignal is a 4:3 or 16:9 aspect ratio.

4:3 aspect ratio - The MID circuit processes a 480p, 4:3 picture the sameas the 4:3 NTSC picture. The MID circuit adds 60 blank lines to the sig-nals. The picture is normally overscanned so the 60 blank lines are notseen.

16:9 aspect ratio - The MID circuit does have to add 60 lines to the 480p,16:9 picture when the horizontal frequency is changed. When this 16:9picture is placed on a 4:3 screen, the picture is too tall (screen width wasreduced).

To maintain the aspect ratio of the picture, the vertical size must be manu-ally reduced so the picture looks normal on the TV’s 4:3 screen.

1080i Picture Process

The 1080i-video format is a high-resolution picture with a 16:9 aspectratio at a 33.75kHz horizontal frequency. The 1080i picture actually has540 lines/scan (half 1080). Although 540 lines would fill this picture tubevertically, the picture tube is the wrong aspect ratio. The 16:9 picture isthe correct width on the TV, but is too tall because it is displayed on a 4:3picture tube. To compensate, the vertical size is automatically reducedwhen a 33.75kHz input signal is detected. The final 1080i picture is a“letterbox” on the KV32XBR400:

Aspect Ratio Detection

The picture’s aspect ratio is always 4:3 for a standard 480i input and 16:9for a 1080I input. Unfortunately a 480p signal can be in either aspect ratioso the TV must be adjusted manually. The MID circuit monitors the hori-zontal frequency of the input signal when video 5 or 6 is selected. If the H.input frequency is 15.734kHz or 31.5kHz, blank lines are added and thepicture is normally over-scanned vertically for a 4:3 picture. If the H. inputfrequency is 33.75kHz, IC201’s (A board) vertical oscillator signal is am-plitude reduced to maintain the correct aspect ratio for a 1080i, 16:9 pic-ture on a 4:3 picture tube. Vertical reduction must be manually selectedfrom the user’s setup menu when a 480p 16:9 signal is input.

Picture Compensation using Horizontal FrequencyResolution Aspect

RatioHoriz Freq Vertical

CompensationLinesadded

480i 4:3 15.734kHz Normal Overscan Yes

480p 4:3 31.50kHz Normal Overscan Yes480p 16:9 31.50kHz Manual Reduction Yes1080i 16:9 33.75kHz Automatic Reduction No

540p480p16:9 pix

Verticalsizereduced

540pMIDCircuitry

4 : 3Pix Tube

20


IC9001-3RGB

OUTPUT

IC3303DRC

CIRCUIT

IC3048SW


IC3414YUV

SWITCH

IC3603ID-1

DECODE

IC201Y/CCRT

DRIVE

TUNER/VIDEO

1-4STANDARD

NTSCRESOLUTION

VIDEO 5VIDEO 6

480i480p1080i

H + VSYNC

480i

480i

H + V

CRTCATHODES


OSD

CONT

Y, Pb, Pr

Y, Pb, Pr

DATA/CLKIICBUS

IICBUS

DATA/CLK

B BD. A BD.

C BD.

12DTV02

1080i

480p

10/2/00

VIDEO

Yo -7Cr-7Cb-7

21

ch3

ch2

ch1

C H 1!2.00 V~

C H 2!2.00 V= STOP

C H 3!2.00 V= C H P MTB20.0us line ch1p

1

2

3

Video BlockThis Video Block Diagram will show the video signal processing as itchanges from an NTSC composite video signal to separate Y & C, com-ponent Y, Pb, Pr and finally to RGB for the CRT cathodes.

Composite Signal Input (B Board)The NTSC format video from one of the two tuners or video inputs 1-4 isselected by composite video switch IC3201. The user makes the selec-tion from the remote to the Main uCom IC701 through the I2C bus intoIC3201 (not shown).

There are three outputs from IC3201:

IC3201 Outputs

Name Location Output Type Destination

Main CN3201/pin 1 Composite or Y (if Svideo input TV)

3D Comb filterIC3501

Sub IC3201/pin56, 58

Separate Y / C Y/C Subprocessor

Monitor IC3201/pin Composite Rear panel output

Y & C Separation (B Board)The main composite signal enters the BC board that plugs into the largerB board. The 3D Comb filter separates the luminance from the chroma,pixel by pixel to output Y and C signals. The input and outputs of theComb filter are accessible and shown as 2Vp-p signals with a DC compo-nent in this scope shot:

3D Comb Filter - Color Bar input

Channel Name Location Comments

1 Input CN3201/pin 1 2Vp-p

2 Y Output CN3201/pin 3 2Vp-p

3 C Output CN3201/pin 5 1.7Vp-p

Time base = 20usec/div

Component Video Conversion (B Board)The separate Y & C main signal is matrixed into component Y, Pb, and Prsignals inside IC3048. This IC3048 can therefore act as a switch to choosebetween the component video input from Video 5, Video 6 or the mainsignal from the 3D Comb filter.

An additional RGB signal from the closed caption / V Chip IC3602 can bematrixed into the signal path by IC3048 if these features are selected bythe user.

There are three outputs from IC3048:IC3048 Outputs

Name Output Type Destination

Main Signal Component Main/Sub selector

H & V Sync 1Vp-p Sync selector IC3004

Comp Video 1Vp-p CCD/V Chip IC3602,ID-1 IC3603

Comp Video / ID-1 Concept

ID-1 Concept

ID-1 is a relatively new concept. The ID-1 signal is hidden in the verticalblanking area of the picture. This ID-1 signal identifies the aspect ratio ofthe picture. IC3603 finds the signal and outputs data to the microproces-sor. The micro can change the vertical or horizontal size to present thepicture properly. Recently, an ID-2 signal containing the aspect ratio andcopy guard information has been proposed.

Main Signal Path

The main component video and sync signals are sent to switches IC3002(video) and IC3004 (sync). They switch between the main and sub pic-tures. The outputs go to the Digital Reality Creation IC3303.

22

IC3201A/V

SW - 1

VIDEO BLOCK 1/2 10/2/00

IC35013D COMBFILTER63

IC3003SUB

COMB

6

A25 41

A8

A10

44 1 76

83 84

5 3

IC3048YCTMAIN

48 46

1IC3602

CLOSE CAPV CHIP

IC3002YCTSEL

IC3603ID - 1 DEC

IC3001COMP J - F

IC3004DRCSYNSEL

BC BOARD

Y,Pb, Pr

MAINY,Pb,Pr

MAINY,Pb,Pr

DRC CDSEL/

SYNC-SELMID-uCOM

IC3090

MAINTUNER

SUBTUNER

VIDEO 1 - 4480i FORMAT

MONITOR OUT

VIDEO5 - 6480i/480p/1080i

A BD.

B BD.

U BD.

SUB OUT

Y/C TO:YCT SUB(IC3110)

CN003/CN3203

HD - SVD - S

(IC3110)SUB

VIN

VIN

RGBHTIM,VTIM

HTIM/VTIM SYNCTO IC3413

MAIN

YC

Y

C

DATA CLKI2C/ BUS (TO MID

uCOM IC3090)VID 5,6

COMPONENTVIDEO TO IC3414

SUBY,Pb,Pr(IC3110)

HD,VD

C YCN3500/CN3201

CN3201/CN3500

TODRC - MF

IC3303

4ADTV02 1254

SUB PIXCOMPOSITE

VIDEOIC3110

961547C

(S VIDEO)

COMPOSITE/ Y

23

Digital Reality Creation

This 3rd generation device has three main purposes:

• Doubles the number of pixels on each scanning line after analyzingthe pixels in the immediate area.

• Creates double the number of scanning lines by prediction.

• Doubles the horizontal frequency to match the new image.The input is analog component video and the output is an 8 bit parallelport for each of the three component lines - Y, Pb and Pr. The digitaloutput goes to the MID circuit IC3408.

Multi Image Driver (MID) Circuit

The purpose of the MID circuit is to:

• Displays two images on the same screen (Main and Sub or Main andHigh resolution).

• Add 60 blank lines to the picture.

• Change the input signal’s horizontal frequency from 31.5kHz to33.75kHz.

• Instruct the related MID uCom IC3090 what the input horizontal fre-quency is so it can control the sync path and aspect ratio.

Any input signal selected is present at the MID-XA signal processor IC3408,so it knows what the input horizontal frequency is. Using this information,the interconnected MID-uCom IC3090 can control the signal and syncrouting as well as send information to the Y/C CRT Drive IC201 for verti-cal reduction.

MID-uCom IC3090 Outputs

Name Destination Purpose

DO, CO (data, clock) MID-XA IC3408 Add 60 blank lines

IIC data bus Y/C, CRT Drive Vertical Reduction

Sync Sel Sync Sw IC3413 Sync for IC201

To summarize the MID functions, 60 lines are added to the picture by theMID-XA main signal processor IC3408 when the horizontal frequency isnot 33.75kHz. MID-uCom IC3090 instructs oscillator IC201 to reduce thevertical amplitude when the sync is 33.75kHz (High Definition signal).

Signal and Sync Switches

Using control signal from MID-uCom IC3090, switches IC3414 and IC3413select final signal and sync for the Y/C CRT Drive IC201.

The component video that leaves the B board is shown in the waveform:

Component Video leaving the B board - Color Bar input


1 MID Y CN3203/pin B8 0.7Vp-p

2 MID Cb CN3203/pin B9 0.7Vp-p

3 MID Cr CN3203/pin B10 0.7Vp-p


The following waveforms show the horizontal sync compared to the Ysignal. After the MID circuit, the frequency is 33.75lkHz.

P M 3 3 9 4 , F LU K E & P H IL IP S

c h3

c h2

c h1

1

2

24


IC3413SYNCSW.

IC3303DRC - MF

IC3408MID - XA

B10B9B8

B15B14

IC3402 64MSDRAM

MID-uCOMIC3090

35

1

8

10

IC9001,IC9002IC9003RGBOUT

IC201Y/CCRT

DRIVE

RGBTO CRT

CONT.MID-uCOM

IC3090

HIGH DEFINITIONVIDEO 5 OR 6

MAIN H,

CONT:TO IC3414(YUV SW)

II C BUS DO,CODATA/CLK

Y,Pb,Cr

VIDEO

SYNCSEL SYNC

G2MUTE

II C BUSPOWER

OFF MUTEFROM MAIN

uCOMIC701/67,

Q708,Q730

MAINY,Pb,PrFROMIC3002(YCT-SEL)

HD,VDSYNCFROMIC3004

(DRC-SYN-SEL)

IC3410D/A

OSD,RGBFROM MAIN uCOM

IC701

H DRIVE

V DRIVE

PMUTE

R

G

B

IK

YO-7

CRO-7

CBO-7

H+V

YCBCR

MID H

MIDV

CN202/CN9001

CN3203/CN003

YO-7

CRO7

CBO-7

C BD.

A BD.

Y,Pb,PrCOMPONENTVIDEO

FROM IC3001(AV-SW1)

B BD.

4BDTV02 1255

PROG VERT

HTIMHD HORIZ.

IC3048 (YCTMAIN)

VTIMINTERLACE

VERTIC3048,(YCT MAIN)

IC3414YUV SW.

MID

25

Component Video leaving the B board - Color Bar input


1 Mid Y CN3203/pin B8 0.7Vp-p

2 Mid H CN3203/pin B14 3.8Vp-p

3 Mid V CN3203/pin B15 3.8Vp-p


c h3

c h2

c h1

C H 1! 500m V~

CH 2!2.00 V=

CH 3!2.00 V= CH P M TB10.0us line ch1p

1

2

3

RGB Drive / AKB Circuit

The Y/C CRT Drive IC201 has several functions:

• Amplifies the RGB signal and applies it to the CRT cathodes

• Mixes the main signal with the RGB On-Screen Display (OSD)

• Automatic Cathode Balance (AKB) or IK (cathode current)The AKB circuit monitors the CRT cathode currents and adjusts the RBGdrive levels to compensate for CRT aging. By adjusting RGB drive levelsto simulate the same cathode currents, white balance can be maintained.

To accomplish this task, at power ON three IK drive pulses (about 3Vp-p)from IC201 are sent to each CRT cathode (video is muted). The cathodecurrents from all three cathodes are returned to IC201 on the single IKline. The three pulses are used to adjust the RGB drive pulses (and RGBgain) to produce equal amplitude IK return pulse levels. When the AKBloop closes, the AKB drive pulse is reduced (1.8Vp-p - ch 2). Finally, thevideo signal is unmuted to display a picture.

To see the full operation in the next scope shot, the red drive wire hasbeen opened at CN9001/pin 1. The CN9001/pin 1 connector is shorted toground to simulate a defect red cathode. Notice the red IK drive pulse

(vertical blanking area of ch 1) is still at 3Vp-p (power On level). Thenormal green signal (ch 2) shows the IK signal is reduced to 1.8Vp-pbecause the IK loop is complete. The last waveform (ch 3) does not showthe missing red IK signal because of sampling errors in the digital scopeused.

IK drive signal in the vertical interval - Color Bar input

Channel Name Location (C board) Comments

1 R Drive CN9001/pin 1 4Vp-p (opencircuited)

2 G Drive CN9001/pin 3 3Vp-p

3 B Drive CN9001/pin 8 1.4Vp-p

Time base = 0.5msec/div

Technical Note: If one or two cathodes falls below AKB adjustment range,the video will NOT blank as in other AKB circuits. However, if a cathodedraws too much current, (Ik pulse gets large) the picture will blank, andthe standby light will blink five times and repeat.

In normal operation, if you increase the screen voltage, the IK return pulses(ch 3) will increase in amplitude because more cathode current is drawn.Because of the AKB closed loop, IC201’s output IK drive pulses (ch 2) willdecrease to lower the cathode current.

Vertical blanking

IK drive pulses

339 , U & S

ch3

ch2

ch1

CH 1!2.00 V=

CH 2!2.00 V=

CH 3!1.00 V= CHP MTB 500us- 1.08dv ch1-

1

2

3

T

26


IC3413SYNCSW.

IC3303DRC - MF

IC3408MID - XA

B10B9B8

B15B14

IC3402 64MSDRAM

MID-uCOMIC3090

35

1

8

10

IC9001,IC9002IC9003RGBOUT

IC201Y/CCRT

DRIVE

RGBTO CRT

CONT.MID-uCOM

IC3090

HIGH DEFINITIONVIDEO 5 OR 6

MAIN H,

CONT:TO IC3414(YUV SW)

II C BUS DO,CODATA/CLK

Y,Pb,Cr

VIDEO

SYNCSEL SYNC

G2MUTE

II C BUSPOWER

OFF MUTEFROM MAIN

uCOMIC701/67,

Q708,Q730

MAINY,Pb,PrFROMIC3002(YCT-SEL)

HD,VDSYNCFROMIC3004

(DRC-SYN-SEL)

IC3410D/A

OSD,RGBFROM MAIN uCOM

IC701

H DRIVE

V DRIVE

PMUTE

R

G

B

IK

YO-7

CRO-7

CBO-7

H+V

YCBCR

MID H

MIDV

CN202/CN9001

CN3203/CN003

YO-7

CRO7

CBO-7

C BD.

A BD.

Y,Pb,PrCOMPONENTVIDEO

FROM IC3001(AV-SW1)

B BD.

4BDTV02 1255

PROG VERT

HTIMHD HORIZ.

IC3048 (YCTMAIN)

VTIMINTERLACE

VERTIC3048,(YCT MAIN)

IC3414YUV SW.

MID

27

Picture with PictureThe picture with picture feature in the Sony model KV32XBR400 and36XBR400 TVs displays two signals side by side. The picture-in-picturefeature containing a small “sub” picture in one of the corners of the mainpicture is not used in this TV set.

If the left or right picture is defective or missing, the signal path is requiredto localize the defect. There are two signal paths, one for each picture. Incomparing the two diagrams, you will note that the main picture is on the

left when both pictures are standard 480i video resolution. The confusingpart is that when video 5 or 6 is selected and a 480p or 1080i signal isdetected, the main picture moves to the right. There is no swap button toexchange pictures.

Standard Resolution Input

When only standard resolution signals are selected in the picture-with-picture mode, the left picture will pass through the DRC-MF circuit fordetail improvements. The right picture will enter the MID-XA circuit di-rectly to be reduced and merged with the main DRC picture on the samescreen.

IC9001 - 3VIDEOOUT

A/V SWITCHESCOMPOSITE TO

COMPONENTMATRIX

A10

A6IC3303DRC -

MF

IC3408MIDXA

IC201CRT

DRIVE

��

��

MAIN480i

PIX INDRC

PROCESS

SUB480iPIX

480iY,Pb,Pr

MAIN

MAINTUNER

SUBTUNER

VIDEO 1 - 4

VIDEO 5 - 6

SUBTU - V

MAINTU - V

CN3203/CN003

MAIN +SUB

CRT CN9001/CN202

CN003/CN3203

SUB

MAIN

SUB

INPUTS ARE 480i

U BD.

A BD.

A BD.

C BD.

PICTURE WITH PICTURE - STANDARD RESOLUTION

B BD.

SUBTUNER

VIDEO 1234

MAIN TUNERVIDEO 1

234

VIDEO 5 - 480i6 - 480i

28

High Resolution Input

If video 5 or 6 inputs were selected, the MID circuit measures the signal’shorizontal frequency to identify the video signal. If the frequency is higherthan 15.75kHz, the signal is either 480p or 1080i. The MID uCom togglesswitches to set up the signal path shown in the diagram below. When a480p or 1080i signal is detected, this picture will be placed on the left sideof the screen.

The right 480i main picture will come from the tuner or video 1-4 signalsalong the top 480i path through the DRC-MF IC3303.

The right side picture in Twin View cannot select video 5 or 6 inputs (theyare skipped during the selection).

PICTURE WITH PICTURE - HIGH RESOLUTION INPUT

IC9001 - 3VIDEOOUT

A/V SWITCHESCOMPOSITE TO

COMPONENTMATRIX

A10IC3303DRC -

MFIC3408

MIDXA

IC201CRT

DRIVE

��

��

VIDEO 5,6Y,Pb,Pr

1080i/480p

480iPIX IN DRCPROCESS

480iY,Pb,Pr

HDPIX

MAINTUNER

VIDEO 1 - 4

VIDEO 5 - 6

CN3203/CN003

TO CRTCN9001/CN202

CN003/CN3203

MAINPIX

MAIN

U BD.

A BD.

A BD.C BD.

IC3001COMPJ - F

HIGHERRESOLUTION

STANDARDRESOLUTION

B BD.MAIN

+HD

MAIN TUNERVIDEO 1

234

VIDEO 56

29

Power ON Block

Power SuppliesThere are four power supplies in the XBR400 TV:

KV32XBR400 Power Supplies

Name Board Start Purpose

Standby A Plug in 5V for Main uCom

7V & 15V for power relay

Primary A Power ON Unreg 11V, 7V, 5V becomeregulated 9V, 5V, 3.3V.

Secondary D Primary Pre15V, MainRelay

+200V for HV stage,+135V for H. Output, +15V,+24V for Audio stage

HV Converter(not shown)

D Horiz OutputAFC-PLS

31.5kV HV for CRT, Focusvoltage.

Except for the Standby power supply, the Primary, Secondary and HVConverter supplies are similar. The last three supplies use the same IC ina similar configuration. How they are turned on and the voltages theydeliver is what makes them different.

Each power supply is turned on in the order listed. The first power supplyis operational when the TV is plugged into AC. When the TV is poweredON, the second and third supplies are turned ON one after the other.These supplies power the horizontal stages. Finally, the fourth powersupply is turned ON after the horizontal output transformer develops scan,filament voltage and AFC pulses. The last power supply is not shown onthis diagram, but knowing when the HV is powered on is important fortroubleshooting.

Standby Power SupplyWhen the TV is plugged in, the standby power supply outputs three volt-ages: +15V, +7V, and +5V. A small transformer develops the +15V and+7V. The +7V is regulated down to +5V to power the Main uCom IC701.

Primary & Secondary Power SuppliesBefore power ON can occur, the front panel master ON/OFF button (S01on the HA board) must be pressed in. This latching switch behind thebutton supplies the AC relay (RY6501) with standby 7V. Pressing theswitch again would unlatch the switch and the set would shut OFF.

Power ON can be activated from the remote control or when the frontpanel button is latched in. The second half of front panel switch S01 (notshown) grounds out the power ON input to Main uCom IC701. IC701powers ON the TV by turning on relay driver Q6527. Q6527 grounds oneend of relay RY6501 and momentarily turns on Q710 via C724. Q710supplies a higher +15V to AC relay RY6501 because a relay needs morevoltage to close the contacts than to hold them closed.

Primary Power SupplyThis power supply only needs 340Vdc from the bridge rectifier D6530 tostart up and run. Three voltages with the prefix “set” are used on the Aand plug in B and BC boards. The most important voltage is the Pri Pre15V output that starts up the Secondary power supply on the D board.

Secondary Power SupplyThe Secondary Power Supply needs three items to operate:

Three Items needed to run the Secondary Power Supply

Item From Purpose

340Vdc (B+) Bridge Rectifier D6530 Powers the Driver/Output

Pri Pre 15Vvoltage

Primary Power Supplysecondary

Starts the oscillator whenmore than 15.6Vdc.

Main Relay(normally HIGH)

Main uCom IC701 Enables IC6501 whenHIGH

This secondary power supply produces the remainder of the low voltagesto power the TV. The +200V feeds the HV Converter power supply. The+135V powers the Horizontal stages. The +15V makes Main 12, Main 9and Main 5V used throughout the D board. The +24V feeds the audiooutput stage.

30

POWER ON BLOCK 10/3/00

STANDBYP.S.

DEGAUSSINGCIRCUIT

Q710

FRONT PANELPOWER (HA BD.)

IC701MAIN uCOM

121 1 1

IC6001PRIMARY

POWER SUPPLY

IC6010

IC6007

IC6003

UNREG.5V7V11V

RY6501

Q6530,Q6532PROT.LATCH

STANDBY 15V

DCCCOIL

ACRELAY

+135V

OVP

OCP

STANDBY 7V

IC6501SECONDARY

POWERSUPPLY

SET 9V

SET 5V

SET 3.3V

+200V

+135VSOURCE

SOURCE

A BD.

STANDBY 5V

STANDBY 7V

STANDBY 15V

SOURCE

ACOUT

AC

Q6527

D6530

D BD.

D721D722

R6006

R6526

ACRECT

+

F60016A

CN6013/

CN6503

CN7003/CN702/CN6504

CN6005/

CN6501CN6502

6DTV02 1261

2 5

DGCCOIL

MAINRELAY

MAINRELAY

PRIPRE15V

STANDBY5V

POWER ON(HA BD.)

S 01

+24VAUDIO

+ 15V-

3

C724

SETON

31

Primary Power SupplyThe primary power supply on the A board consists of three parts:

1. Oscillator 2. Output stage 3. Regulator Stage

Start UpThe oscillator within IC6001 starts if the V Sense input voltage at pin 1 isabove 1.3Vdc. Sample voltage from pin 18 is then used to run the inter-nal oscillator. The initial frequency is approximately 200kHz. The lowamplitude initial oscillator signal is output IC6001/pins 12 and 16 into thedriver/output stage.

Driver / Output stageThe oscillator voltage output at pins 12 and 16 use drivers Q6007 andQ6008 to develop T6003 secondary voltages. IC6001’s oscillator will shutdown if the driver transistor’s current is excessive. To prevent prematureshutdown, the timer capacitor C6064 delays the shutdown.

VC1 Enables the Regulator

Although the oscillator is running, at this initial frequency of 200kHz, thereis insufficient current from T6003 to produce any unregulated 5, 7, or 11Vvoltage because of the load. There is little load on D6005 and D6009,producing about 15V each at the cathodes (normally about 18Vdc). Thevoltage from D6005 is returned to IC6001/pin 8 to serve as regulated B+for the internal drivers that amplify the oscillator signal leaving pin 12.The VC1 voltage also enables the internal regulator circuit (responds tothe error voltage input IC6001/pin 2) to change the oscillator frequency.

B+ for IC6001’s Internal Drivers

At start up IC6001 uses current limited B+ from pin 18 to amplify theoscillator signal and get it out to pin 16 (internal drivers). When VC1 ispresent, the internal drivers switch to this stable regulated B+. The B+ forthe internal drivers for IC6001/pin 16 comes from Vb at pin 14. D6003and C6009, external to IC6001/pins 10 and 14 (Vb), complete an internalvoltage boost circuit. This boost circuit starts with VC1 voltage (input pin8) that is connected internally to VC2 pin 10 (less 0.6Vdc). This VC2voltage is filtered by C6009 and passes through blocking diode D6003

into pin 14. Internal pulses from IC6001/pin 14 add to D6003’s DC volt-age, producing the boost voltage at Vb pin 14. This boost voltage isapproximately +10V above the reference voltage at IC6001/pin 15 andused internally to serve as the B+ for the top internal drivers that amplifyoscillator signal leaving IC6001/pin 16.

Secondary Power Supply Starting

The Pri Pre 15V output of D6009 is only approximately 10Vdc at start upwhen the oscillator frequency is high (normally about 18Vdc). When isreaches 15.6Vdc, it starts the Secondary Power Supply. Therefore, theSecondary Supply cannot start until the Primary Supply is running.

RegulationConcept

T6003’s secondary output voltages are dependent upon the match be-tween the output resonate circuit (T6003 = L, C6014 = C) and the oscilla-tor frequency. When IC6001’s oscillator frequency is the same as theresonate circuit frequency, there is maximum power transferred in T6003producing maximum output voltage. By setting the oscillator frequencyabove resonance, T6003’s output voltage can be regulated.

T6003OutputVoltage

85kHz = Normal Operation

200kHz = Start Up

Output Voltage Control

The regulating stage uses error detector IC6002 and optical isolatorPH6001 to monitor the unregulated +7V output from T6003. If the un-regulated +7V output is LOW as it is at initial start up, the voltage fed backto IC6001/pin 2 goes HIGH, decreasing the oscillator frequency. Thedecrease in frequency increases the output of the T6003 transformer,until +7Vdc is reached.

Regulation Feedback Voltages

Unreg 7V Output (D6011) PH6001/pin 2 IC6001/pin 2

Low high high

32

PRIMARY POWER SUPPLY 10/3/00

PH6001OPTICAL

ISOLATOR

R6002

R6010

NCH

NCH

IC6001DRIVER

MCZ3001D

16

12

9

15

18

26 8 10 14

1

2C6009

1

IC6002ERROR DET.

uPC1093C3 1

ACRECT.+FROMD6530(D BD.)

R66060.47 OHMS

R6059R6007

R6008

R6009

R6011

C6064

VC1 VC2 VB F/B

OCP R6043

+

+

T6003

Q6008

Q6007

TIMER

R6049 R6050R6022

R6029

D6011

C6014

UNREG.7V

SOURCE

D6005

D6009

D6012

D6013

PRIPRE 15V (D

BD.)

UNREG.5V SOURCE

UNREG. 11VSOURCE

VSENSE

7DTV02 1263

340VDC

160V

3V

1.86V

D6003

18.4V

A BD.

VD

VGH

VS

VGL

33

ch2

ch1ch1: pkpk= 325 V

ch1: freq= 84.8kHz

CH1! 100 V=

CH2!5.00 V= MTB2.00us- 1.18dv ch1-

1

2

T

In the following scope shot both drive outputs from IC6001/pins 12 and 16are shown. The outputs are complementary, the duty cycle is 50% andthe frequency has dropped down from 200kHz to about 85kHz.

Primary PS Oscillator - Normal operation - 85kHz

Channel Name Location Voltage

1 Top Driver Output Q6008/gate 340Vp-p

2 Bottom Driver Out Q6007/gate 12Vp-p (4.6Vdc)

Time base = 2usec/div.

TestingChecks for Primary power supply operation

Check Point Normal

1. R6006 340Vdc P.S. Input voltage

2. CN6005/ pin 5 >+15.6Vdc Pri-Pre 15V. Checks P.S. Output

3. IC6001/ pin 2

(Feedbackvoltage)

1.9Vdc If step 2 voltage is low, measureIC6001/pin 2. If pin 2 is High (4V) -problem is around IC6001. If pin 2is Low (0-1V), problem is thefeedback path IC6002, PH6001.

4. IC6001 voltages. See the next chart.

IC6001 Voltages (Power ON, Video 1 input, Dark screen)

1. 2. 3. 4. 5. 6. 7. 8. 9.

3.0V 1.8V 2.2V 2.5V 0V 0V 4.5V 18.4V 0V

10. 11. 12. 13. 14. 15. 16. 17. 18.

10V 0V 4.5V -0.2V -28V -32V -32V -0.3V 313V

PM3394, FLUKE & PHILIPS

ch2

ch1ch1: pkpk= 349 V

ch1: freq= 209kHz

CH1!79.9 V=

CH2!10.0 V= MTB1.00us- 1.28dv ch1+

1

2

T

Hot ground is at CN6501/pin 6 (black wire).

Oscillator Output OperationThe details of how the oscillator develops output voltage in T6003 areexplained here. When the oscillator in IC6001 starts up (V Sense = 3V,no feedback VC1 voltage yet), the signal is amplified using unregulatedvoltage input pin 18 and a 200kHz signal is output IC6001/pins 12 and 16.This is shown in the following waveform:

Primary PS Oscillator - Start Up = 209kHz


1 Top Driver Output IC6001/pin 16 340Vp-p

2 Bottom Driver Out IC6001/pin 12 12Vp-p (4.6Vdc)


The two signals applied to the Q6008 and Q6007 drivers are complemen-tary. This means only one MOSFET is conducting at a time. A positivevoltage applied to top MOSFET Q6008’s gate turns it ON so its Drain toSource resistance drops, increasing the voltage to T6003’s primary wind-ing. This voltage passes through the primary winding of T6003 into C6014.As the increasing voltage charges C6014, a magnetic field is built up inthe primary of T6003. This magnetic field induces voltage into the sec-ondary windings that is rectified to supply low voltages to the TV set.

The cycle continues when Q6008 turns OFF and Q6007 turns ON. Thecharged C6014 discharges through the primary of T6003 and Q6007 toground. The cycle then repeats.

34

PRIMARY POWER SUPPLY 10/3/00

PH6001OPTICAL

ISOLATOR

R6002

R6010

NCH

NCH

IC6001DRIVER

MCZ3001D

16

12

9

15

18

26 8 10 14

1

2C6009

1

IC6002ERROR DET.

uPC1093C3 1

ACRECT.+FROMD6530(D BD.)

R66060.47 OHMS

R6059R6007

R6008

R6009

R6011

C6064

VC1 VC2 VB F/B

OCP R6043

+

+

T6003

Q6008

Q6007

TIMER

R6049 R6050R6022

R6029

D6011

C6014

UNREG.7V

SOURCE

D6005

D6009

D6012

D6013

PRIPRE 15V (D

BD.)

UNREG.5V SOURCE

UNREG. 11VSOURCE

VSENSE

7DTV02 1263

340VDC

160V

3V

1.86V

D6003

18.4V

A BD.

VD

VGH

VS

VGL

35

Secondary Power SupplyThe Primary and Secondary power supplies are similar because they usethe same IC and driver/output stage. They differ in start up and outputvoltages.

Start UPAlthough IC6501 is identical to IC6001 in the Primary power supply, IC6501/pin 18 in this supply is not connected to 340Vdc. This makes VC1 at pin8 the primary source of power to start this IC after pin 1 senses voltage.The start up sequence is listed as follows:

1. 340Vdc (B+) is applied to this stage from bridge rectifier D6530.2. Pri Pre 15V voltage from the Primary power supply is applied to IC6501/

pin 8. It must be at least 15.6Vdc to enable IC6501’s internal oscilla-tor.

3. Main Relay signal from Main uCom IC701/pin 72 (HIGH at CN6501/pin 5) turns ON Q6531, PH6503 and Q6528. Q6528 turns OFF Q6503,enabling voltage to appear at IC6501/pin 1.

4. R6646 and R6513 deliver at least 1.3Vdc to IC6501/pin 1.5. IC6501 turns ON using voltage from pin 8 to run the oscillator.6. An internal diode connected between pin 8 and 10 supplies voltage to

VC2.7. Oscillator pulses from VC2 pass blocking diode D6502 to make a

(“pump up”) voltage for the internal predriver amplifier stage.8. Oscillator signal outputs IC6501/pins 12 and 16.In summary, these items are necessary to run the Secondary Supply:

Three Items needed to run the Secondary Power Supply

Item From Purpose

340Vdc (B+)

(CN6501/pin 1)

Bridge Rectifier D6530 Powers the Driver/Output

Pri Pre 15Vvoltage(CN6501/pin 5)

Primary Power Supplysecondary

Starts the oscillator whenmore than 15.6Vdc.

Main Relay(normally HIGHat CN6504/pin 2)

Main uCom IC701 Enables IC6501 whenHIGH

RegulationThe +135V line to the Horizontal Output stage is fed back to IC6501 forregulation of the secondary power supply. Error Control IC6503 and OpticalIsolator PH6502 control regulation. If the +135V output rises, the voltageat IC6501/pin 2 lowers to correct. A reduced voltage increases the oscil-lator frequency and decreases the output voltages of T6501.

TestingThe typical error correction feedback voltage at IC6501/pin 2 is 2Vdc. Bymeasuring the +135V B+ at R6598 and the feedback at IC6501/pin 2, youcan determine if the problem is in the basic oscillator stage or the errorregulator stage.

1. Measure B+ atR6598 (0.27 ohms

at 1W)

2. MeasureIC6501/pin 2

Voltage

3. Problem area

Higher than 2V Oscillator stage IC6501B+ is LOW or 0V

Lower than 2Vdc Error regulating stageIC6503/PH6502

Higher than 2V Error regulating stageIC6503/PH6502

B+ is HIGH(shutdown Stbylight blinks 3 times) Lower than 2Vdc Oscillator/Driver Stage

IC6501

IC V l (P ON Vid i D k )IC6501 Voltages (Power ON, Video 1 input, Dark screen)

1. 2. 3. 4. 5. 6. 7. 8. 9.

2.5V 1.8V 2.2V 2.5V 0V 0V 4.0V 18.3V 0V

10. 11. 12. 13. 14. 15. 16. 17. 18.

10V 0V 4.7V 0 V -15V -19V -19V 0V 1.5V

Hot ground is at CN6501/pin 6 (black wire).

36

SECONDARY POWER SUPPLY 10/6/00

1

PH6503OPTICAL

ISOLATOR

2

3

IC6501DRIVER

MCZ3001D

16

12

9

8

15

18

14

10

2

- 15VSOURCE

+ 15VSOURCE

PH6502OPTICAL

ISOLATOR4 2

1

IC6503CONTROL

DM-585

4

1

PRIMARYPOWERSUPPLY

AC

ACD6530

DC

PRIPRE 15VCN6005/6

(A BD.)

GND

AU + 24TO AUDIO

+200VSOURCE

135VSOURCE

T6501PIT

R65260.1 OHM

R6513

R6646

Q6507

Q6528

N

STANDBY 5V

START

MAINRELAY FROMMAIN uCOM

IC701/72(A BD.)

Q6531

N

R6504

D6502

R6501

VC2

VC1

V B

OCP

Q6503R6533

N

R6535

Q6506

R6556C6532 R6590

NCH

NCH

D6515

D6513VSENSE

R6557

D6517

R6552

D BD.

8DTV06 1262

ON

ON

OFF

TO HVSOURCE

R6598

1

R6517

VD VGH

VS

VGL

F/B

D6514

D6516NOCONNECTION

37

No horizpincushioncorrection

Pix isbowedinward

Horizontal Drive / H Pincushion Correc-tion / Filament Voltage

OverviewThe purpose of the horizontal drive circuit is to manufacture a magneticfield that is used to sweep the CRT’s electron beam from left to right onthe screen. Within the basic horizontal drive circuit there is a PWM circuitthat supplies the Horizontal Output transistor with voltage and provideshorizontal pincushion correction. The horizontal drive circuit also makesthe CRT filament voltage.

Basic Horizontal Drive CircuitThis circuit is split between an oscillator on the A board and an outputstage on the D board. The 33.75kHz horizontal oscillator is in the Y/CCRT Drive IC201. IC201 outputs a 2Vp-p rectangular waveform from pin40 while there is B+ at pins 55 & 61 and the 2.7MHz X201 crystal isrunning. The horizontal drive waveform is buffered by Q211 and entersthe D board.

On the D board, an N channel MOSFET driver and an output transistoramplify the signal to provide sufficient current to drive the HOT T5001 andthe H DY deflection yoke.

At the output stage, the HOT T5001 has a secondary winding that pro-vides filament voltage while its main winding provides +200V for the RGBvideo output ICs. While the H DY yoke provides horizontal beam deflec-tion (sweep), a voltage divider consisting of capacitors C5058-C5060 tapoff a sample of the H spike from the H Output Q5030/Collector to start theHV converter stage. This AFC-PLS is also used in the convergence anddynamic focus stages.

The waveforms of the horizontal drive stage show typical signal shapes.The difference between this set and a conventional one is that the hori-zontal frequency is 33.75kHz (ch 2), not 15.75kHz (ch 1). When compar-ing the input sync (ch 1) to the horizontal oscillator (ch 2), notice that theyare not in phase. This is because the DRC circuit doubled the H fre-

quency, but the MID circuit stored the video and output the signal at anew H freq. of 33.75kHz, independent of the source.


ch4

ch3

ch2

ch1

CH1!2.00 V~

CH2!2.00 V~

CH3!10.0 V~ STOP

CH4! 125 V= ALT MTB5.00us L=2 ch2p

1

2

3

4

Horizontal Drive Signals


1 15.75kHz H signalInput

NTSC generator from thegenerator

2 33.75kHz osc output IC201/pin 40 2.2Vp-p

3 H Driver input Q5028/gate 12Vp-p

4 Horiz Output Q5030/Collector 1kVp-p


PWM CircuitThe PWM circuit has two functions. First it provides a regulated 102Vdcoutput for the H Output transistor. Second it compensates for horizontalpincushioning and keeps the picture straight at the sides.

38

HORIZONTAL DRIVE 10/10/00

Q50

04O

CP

IC201Y/C CRTDRIVE

CXA2150Q

39 40 2

MID HSIC3413/4

SYNC SW.(B BD.)

Q5035,Q5036,

Q5026-7H DRIVE

6

IC5002,Q5003,Q5011

PWM CIRCUIT

1

8

2

Q5016200VREG.

IC50066V

REG.

C5035100+

Q211

MAIN12V

D5013

RGBVIDEO

OUTPUT(C BD.)

T5002HDT

CN203/CN5505

R5013

R5096

D5015

R5095 D5014

NCHQ5028

DRIVER

Q5030H OUT

R5142-4

T5001 HOT

D501850V

H DY

R5094 D5012 G2TO

C BD.

R5164

D5025

UNREG.7V (A BD.)

D5024

D5023N

C5058

C5059

C5060

CRTHEATER

H. PROTIC701/44

Y/C (A BC.) 135V

D BD.

A BD.

HOT

AFC-PLS TO:

14DTV02 1266

+135V

102V

47 7E/W

DRIVECN201/CN5503

3361

55

X201MAIN9V

7

37AFC-PLSQ5030/C

HD

IC8001/8 HV CONV.IC5511/19 DQP CONT.IC5513/14 DY-CONV.IC201/39 Y/C CRT DRIVE

39

Regulator

The PWM circuit regulates +135Vdc from the secondary power supplydown to 102Vdc. It is driven by H drive pulses from Drivers Q5026-7.These pulses are amplified and output to HOT T5001/pin 1. To controlthe output voltage, the output is sampled and used to change the pulsewidth of the H drive pulses. These changes regulate the output voltage to102Vdc at T5001/pin 1.

Pincushion correction

If the PWM output voltage at T5001/pin 1 were changed, the horizontalpicture size would vary accordingly. A vertical pincushion signal made byIC201/pin 47 is applied to this PWM stage to increase the picture widthand compensate for pincushion distortion.

The first waveform shows the input E/W (east/west) pin correction signal.The second waveform is the PWM output. The corresponding modula-tion (sum of E/W signal and horizontal drive) changes the width of theoutput pulses (ch2), but that is not easily seen at this scope’s time base.

Horizontal Pincushion Correction


1 E/W Drive Cn5505/pin 7 0.7Vp-p

2 PWM Output T5001/pin 1 150Vp-p.102Vdc

Time base = 5mesc/div.

ch2

ch1

CH1 ! 500mV~

CH2!50.0 V= MTB5.00ms ch1+

1

2

T

Filament VoltageThere are two sources of filament voltage. When the set is turned ON,unregulated 7V from the primary power supply (A board) is reduced byD5025 and D5024 to approximately (7V-1.2V =) 5.8Vdc. This is the firstfilament voltage source used warm up the CRT quickly at power ON.

There is no danger from this unregulated 7V supply. Excessive voltageon the unregulated 7V-line causes Main uCom IC701 to shut down the TVset (protection circuit not shown here). Consequently, filament damagefrom an unregulated primary power supply is unlikely unless a technicianbypasses the protection circuitry during troubleshooting.

The second filament voltage is applied when the horizontal oscillator sig-nal produces horizontal sweep. The horizontal output transformer T5001/pin 8 outputs 7.7Vdc when running. This voltage is regulated to 6.1Vdcby IC5006 to become the main filament voltage.

40

HORIZONTAL DRIVE 10/10/00

Q50

04O

CP

IC201Y/C CRTDRIVE

CXA2150Q

39 40 2

MID HSIC3413/4

SYNC SW.(B BD.)

Q5035,Q5036,

Q5026-7H DRIVE

6

IC5002,Q5003,Q5011

PWM CIRCUIT

1

8

2

Q5016200VREG.

IC50066V

REG.

C5035100+

Q211

MAIN12V

D5013

RGBVIDEO

OUTPUT(C BD.)

T5002HDT

CN203/CN5505

R5013

R5096

D5015

R5095 D5014

NCHQ5028

DRIVER

Q5030H OUT

R5142-4

T5001 HOT

D501850V

H DY

R5094 D5012 G2TO

C BD.

R5164

D5025

UNREG.7V (A BD.)

D5024

D5023N

C5058

C5059

C5060

CRTHEATER

H. PROTIC701/44

Y/C (A BC.) 135V

D BD.

A BD.

HOT

AFC-PLS TO:

14DTV02 1266

+135V

102V

47 7E/W

DRIVECN201/CN5503

3361

55

X201MAIN9V

7

37AFC-PLSQ5030/C

HD

IC8001/8 HV CONV.IC5511/19 DQP CONT.IC5513/14 DY-CONV.IC201/39 Y/C CRT DRIVE

41

G2 Circuit

OperationThe G2 circuit controls the voltage to the screen grid of the CRT. Thehigher the voltage the more electrons are accelerated in the gun struc-ture, resulting in a brighter picture.

The source of the G2 voltage is approximately 1kV from the HorizontalOutput Transformer (T5001) secondary winding. The G2 control circuituses three transistors to shunt some of the G2 source voltage to ground.The remaining voltage is applied to the CRT’s G2 grid. A simplified dia-gram of this voltage divider is shown below:

Within the shunt circuit are three transistors. Q9008 is used as a refer-ence while Q9012 and Q9014 set the resistance to ground.

Rotating RV9002 varies the conduction of Q9012 and Q9014, and conse-quently the shunt resistance. A lower shunt resistance produces a lowerG2 voltage. The G2 voltage range of the screen control is listed in thechart.

G2 (RV9002) Voltage Range

RV9002 Position G2 Voltage

CCW 292.4Vdc

Normal 484Vdc

2/3 CW 590Vdc is maximum before shutdown

Operating VoltagesNormal Operating Voltages

Transistor Collector Base Emitter

Q9002 10.9V 0V 0V

Q9008 12.0V 5.4V 4.8V

Q9012 10.4V 5.4V 4.8V

Q9014 438.5V 11.5V 10.9V

Automatic Video MuteAt power OFF, the Main uCom IC701 outputs a HIGH that turns on Mutetransistor Q9002. Q9002 lowers the G2 voltage, blanking the video whenthe TV is shut off. The HIGH remains present as long as the TV is pluggedin (standby voltage is present).

CRT G2voltage

Approx.1kV fromthe HOTT5001/6

Resistor string

ShuntTransistorsQ9014,Q9012,Q9008

G2 HV AdjRV9002

42

G2 CIRCUIT 10/3/00

180k OHMSEACH

G2VOLTAGE

FROM HOTT5001/6(D BD.)

R9055 R9085 R9064 R9084

12V

489VDC

C9032907VDC

D9013G2-DUMP D9014

PROT

R90771k

+

+

R9062100k

R9056100k

484VDCCRTG2

GRID

D9001

D9003 R9004R9005

Q9002MUTE

C90384.7

R901010k

R9009 10k

FROM MAINuCOM

IC701/67(A BD.)

R9078

C903610

+

10.4V

5.4V

R9067

R9076

Q9012G2-REF

D9015PROT

Q9008G2-REF

Q9014G2-REF

R9063100k1/2W

RV9002100kG2

R9063

D9017 PROTD9016 PROT

C90470.01CHIP

R9081

C90372.2

R9079

POWEROFF MUTE

N

NNN

C BD.

18DTV02 1267

+

43

HV Converter BlockThis HV Converter is similar to the two low voltage power supplies be-cause they have the same MCZ3001D ICs. This power supply differsonly in the start up, voltage output, and over voltage (OV) protection. TheFlyback Output transformer of this power supply generates regulated31.5kV and focus voltage for the CRT. Excessive current drawn by thisstage will permit Q8009 to shut down the TV set, but there will be noStandby light blink indication.

Start UpThree items are necessary to start this HV power supply:

HV Converter Inputs (Starting)

Name From Destination

1. +200V D6515 & D6517 / cathode(D Bd) IC8002/18 (199V)

2. +15V D6514 / cathode (D Bd) IC8002/8 (14.7V)

3. AFC-PLS

H Out Q5030/C (D Bd)

(CN5501/pin 3 = 9Vp-p

IC8002/1 (1.6V)

The Start sequence is as follows:

1. The Primary power supply produces low voltages for the Horizon-tal stage (D board).2. The Secondary power supply produces +135V for the Horizontalstage, along with +200V and +15V for this HV Converter stage.3. The Horizontal Output stage is needed to develop AFC-PLS pulses(CN5501/pin 3 = 9Vp-p) for the HV Converter.4. AFC-PLS pulses turn ON Q8001 and turn OFF Q8002.5. IC8002/pin 1 rises. (1.3Vdc is the minimum to start IC8002).6. IC8002’s oscillator starts and drives the flyback transformer.7. The voltage at IC8002/pin 2 decreases from 4V to 2Vdc as the HVclimbs to 31.5kV.8. Regulated HV and focus voltage output the Flyback transformer.

Protection / ShutdownThere are two protection circuits for the HV stage. The first circuit shutsdown the HV oscillator if the HV is excessive (without affecting the sound).The second circuit shuts down the entire TV set if the +200V current de-mand is excessive.

Excessive HV Protection

The HV oscillator in IC8002 is stopped if the HV sampled from the flybackis excessive. The oscillator stops when via Q8003 or Q8004 groundsIC8002/pin 1.

Sample high voltage from the flyback transformer normally takes two pathsto keep Q8003 and Q8004 turned OFF. The first path is from D8014through 33V zener D8025. If the sample HV is excessive, zener D8025conducts, turning ON Q8010. A LOW voltage outputs to IC8001/pin 7.The LOW input and output turns Q8003 ON, grounding IC8002/pin 1.This shuts down the HV Converter stage.

The second shutdown path is from D8014 through R8078, and IC8001 toQ8004. An excessive voltage will similarly turn Q8004 ON, shutting downthe HV Converter. RV8001 and RV8003 form a voltage divider along thefeedback path to set the shutdown point.

Excessive Current Protection

Excessive current drawn by the +200V line into this HV Converter stagecauses the TV to shut down. There is NO Standby light blink indicationwhen this HV stage shuts down the TV. The +200 line feeds IC8002, thetwo converter transistors (not shown), and flyback transformer. Exces-sive HV will also cause the TV to shut down by drawing too much currentthrough the flyback.

In summary, shutdown without a Standby light indication indicates a prob-lem in this HV stage.

HV AdjustmentThe adjustment procedure for these three controls is straightforward. Firstthe shutdown controls are preset (ineffective). Then the RV8002 HV con-trol is set to the shutdown trip point. The two shutdown controls are reset.Finally the HV control is set. A HV probe connected to a DVM is requiredfor this adjustment procedure.

44

H.V. CONVERTER BLOCK 10/3/00

Q8022-3, Q8018DYNAMIC FOCUS

AMP

IC8001OP AMPSNJM2901M

IC8002HV DRIVERMCZ3001D

1

2

7

6

4

5

1

2

IC8003, IC8004PH8001 ERROR

DET

CONVERTERTRANSISTORS

FLYBACK

HV TOPICTURE TUBE

FOCUSVOLTAGE(PICTURE

TUBE)

DF DRIVEDQP CONTROL

IC5511/11

+200V(FROM

SECONDARYPOWERSUPPLY)

AFCPLS

(Q5030/CH OUT) Q8001

Q8002

C8004100

ON OFF

Q8004

OFF

OFF

Q8003

R8053-R8055 V

SENSE

RV8002HV

F/B

D80045.1V

D8014

C800547

D8020

Q8010

D802533V

+

+

+

+

-

- R8078

9DTV02 1264

RV8001(COARSE)

RV8003(FINE)

R8042

STARTHV

CONV.

D8003SHUTDOWN LATCH

Q6530,Q6532D BD.

Q8009OCP

18VD

8VC1

+15V(SEC P.S.)

R8056

45

The procedure is as follows:

1. Replace RV8001, RV8002, and RV8003 (they are epoxyed).2. Turn RV8001 and RV8003 both CCW from the top of the D board.3. Turn the set ON with a black screen (HV unloaded).4. Adjust HV RV8002 for 35.5kV (shutdown threshold).5. Adjust RV8001 and RV8003 until the set just shuts down.6. Turn HV RV8002 CW to turn the set ON. Input a white signal. Bring the HV up to 35kV to make sure the set does not shut down. (This rechecks the RV8001 and RV8003 adjustments.)7. Adjust HV RV8002 for 31.5kV.8. Guard against premature shutdown by following bulletin 492 (appendix).

Testing1. HV Check - Measuring the voltage at D8025/Cathode verifies HV.Normally D8025/Cathode = 31.6Vdc when there is HV, and 0V when HVis missing. D8025’s Anode voltage should not be higher than 0.6Vdc innormal operation (measured). D8025 is located next to the potted (epoxysealed) RV8001/RV8003 controls at the left edge of the D board.

2. HV Converter Check - If no HV is output, look for +200V input atIC8002/pin 18 and more than 15.6V at IC8002/pin 8.

Look for HV Conv start voltage at IC8002/pin 1 (normally 1.6Vdc but mustbe more than 1.3Vdc. to start).

Converter IC8002 Voltages

Pin 1 2 3 4 5 6 7 8 9

Volts 1.63 1.75 2.25 2.47 0 0 4.56 14.7 0

Pin 10 11 12 13 14 15 16 17 18

Volts 10.3 0 4.14 0 108 98.6 103 0 200

Additional Important Voltages related to IC8002/pin 1 Voltage

Electrical Location Physical Location Voltage

IC8001/pin 1 0V

IC8001/pin 2

14 pin Surface mounted IC underRV8001/RV8003 0V

C8004/ + lead Behind IC5515 s large heat sinknext to large 820uf, 250V C8023.

0.02V

3. HV may be starting, then shutting down - Monitor D8025/Cathode for3.16V at start up. If it is 0V, there is no HV. Check the converter transis-tors and suspect IC8002 and the flyback to cause OCP shutdown (viaQ8009). If the cathold voltage momentarily rises to beyond 31Vdc, thereis HV but it may be excessive. Turn the RV8001 and RV8003 controlsCCW and adjust the HV. Follow the HV adjustment procedure. If shut-down still occurs suspect D8025, C8005, and D8004.D Bd A Bd

KV32XBR400 rear

D8025

Flyback

46

H.V. CONVERTER BLOCK 10/3/00

Q8022-3, Q8018DYNAMIC FOCUS

AMP

IC8001OP AMPSNJM2901M

IC8002HV DRIVERMCZ3001D

1

2

7

6

4

5

1

2

IC8003, IC8004PH8001 ERROR

DET

CONVERTERTRANSISTORS

FLYBACK

HV TOPICTURE TUBE

FOCUSVOLTAGE(PICTURE

TUBE)

DF DRIVEDQP CONTROL

IC5511/11

+200V(FROM

SECONDARYPOWERSUPPLY)

AFCPLS

(Q5030/CH OUT) Q8001

Q8002

C8004100

ON OFF

Q8004

OFF

OFF

Q8003

R8053-R8055 V

SENSE

RV8002HV

F/B

D80045.1V

D8014

C800547

D8020

Q8010

D802533V

+

+

+

+

-

- R8078

9DTV02 1264

RV8001(COARSE)

RV8003(FINE)

R8042

STARTHV

CONV.

D8003SHUTDOWN LATCH

Q6530,Q6532D BD.

Q8009OCP

18VD

8VC1

+15V(SEC P.S.)

R8056

47

CommunicationsThere are three communications networks used in this DX-1A TV chas-sis. All three consist of only clock and data lines running on a parallelconnection with multiple ICs.

Communications Networks

Network Location Purpose

0

(clock 0, data 0 lines)

IC701/pin29, 30

Dedicated communications tothe two NVM on the A & Dboards (IC707 & IC5501.

1

(clock 1, data 1 lines)

IC701/pin28, 31

Main IIC bus to providedirection to most ICs on the A,B, & D boards

2 B Bd.IC3090 toIC3089 &IC3408

Multi Image Driver (MID)uCom CI3090 communicationslink with driver IC3408 andNVM (memory) IC3089.

Communications Network 0 & 1Main uCom IC701 generates the clock signal for communications net-work 0 and 1. Network 0 is used by IC701 to read and write data to NVMIC707 (A board) and IC5501 (D board). Network 1 is used to send data tomost of the ICs in the TV set.

At power ON, the user data in IC707 and deflection data in IC5501 isretrieved by IC701 using network 0 and passed to the appropriate ICsusing network 1. Once the ICs on network 1 receive this data to set theiroperating parameters, the TV can function.

The Y/C CRT Drive IC201 on the A board and MID uCom IC3090 on theB board can provide return (reply) data to IC701. This data either up-dates the on-screen display menu (OSD is in IC701) or initiates a safetyshutdown of the TV.

The data at both network 0 and network 1 is always present as long as theTV is ON. The first scope shot shows the network 0 data being read fromNVM IC707 and IC5501. The clock and data lines from IC701 are con-

nected to both memories in parallel. The first group of communicationsgoes to IC707. IC5501 is hard wired differently at pins 2 and 3 to acceptthe second communications group from IC701.

c h3

c h2

c h1

C H 1 !5.0 0 V=

C H 2 !5.0 0 V= S T O P

C H 3!5 .0 0 V = C H P M TB 5 .00m s- 2 .58dv ch1 -

1

2

3

T

Memory Communications - TV Channel 7 displayed

Scope Channel Name Location Voltage

1 WP (read/write) CN702/pin 8 5Vdc

2 Clock CN703/pin 1 5Vp-p

3 Data CN703/pin 2 5Vp-p

Time base = 5msec/div.

In this second scope shot, when the TILT rotation number is changedfrom the setup menu, the WP pulse (ch 1) goes LOW when the network 0is communicating with IC707. This allows IC701 to write the new rotationnumber into NVM IC707.

48

COMMUNICATIONS BLOCK 9/29/00

IC35013D

COMB

IC7001AUDIOPROC.

MAINTUNER

SUBTUNER

IC201Y/CCRT

DRIVE

IC701MAIN uCOM

50

28

47

29

30

62

31

1

8

1

IC707NVM

7

6

5 4

3

2

1

8

IC5501NVM

7

5

6 4

3

2

1

2

5

8

2

87

A29 A30

IC5511DQP CONT.

IC3001COMP. I/F

IC3090MID uCOM

IC3201 A/VSW.

IC3202AUDIO SW.

IC3601 SUBCCD V CHIP

IC3408Y CT MAIN

IC3089NVM

IC3408MID-XA

IC3110 Y CTSUB

IC3602 MAINCCD V CHIP

IC5513DY-CONV.

IC4103AUDIO

D/A

STBY+5V

STBY+5V

STBY+5V

DAT 1 CLK 1

WP

CLK 0

DAT 0

Q717

RESET

CLK

DATA

R829

R827

R834

IIC BUS

STBY+5V

WP

DATA

BC BD.

CN706/CN5501

CN703/CN6506

CN702/CN6504

CN7001/CN4104

CLK

CN3201/CN3500S BD.

A BD.

D BD.

B BD.

DAT. CLK

CN203/CN3203

910

65DTV02 1280

16

49PM3394, FLUKE & PHILIPS

ch3

ch2

ch1

CH1!5.00 V=

CH2!5.00 V=

CH3!5.00 V= CHP MTB5.00ms- 2.58dv ch1-

1

2

3

T

Memory Communications during picture Tilt


1 WP (read/write) CN702/pin 8 5Vp-p




Although not shown, network 0 data and clock are accessible at the 10-pin rear panel service connector.

Network 1 communications is also always present when the TV is ON. Ascope shot of the two 5Vp-p signals is shown:

ch2

ch1

CH1 5.00 V~ STOP

CH2 5.00 V= MTB5.00ms- 1.32dv H xx

1

2 T

Network 1 Communications - TV Channel 7 displayed





Communications Network 2Communications network 2 is only used between three ICs on the B board.MID uCom IC3090 communicates with MID IC3408 to retrieve processeddata such as the input horizontal frequency and uses it to select videosignal paths.

MID uCom IC3090 also communicates with memory IC3089 and IC3408to set up the twin picture (picture with picture) parameters. This data inmemory IC3089 is accessed in the service mode using MID uCom IC3090to interface to IC701. MID uCom IC3090 is connected to communica-tions network 1 and 2.

50

COMMUNICATIONS BLOCK 9/29/00

IC35013D

COMB

IC7001AUDIOPROC.

MAINTUNER

SUBTUNER

IC201Y/CCRT

DRIVE

IC701MAIN uCOM

50

28

47

29

30

62

31

1

8

1

IC707NVM

7

6

5 4

3

2

1

8

IC5501NVM

7

5

6 4

3

2

1

2

5

8

2

87

A29 A30

IC5511DQP CONT.

IC3001COMP. I/F

IC3090MID uCOM

IC3201 A/VSW.

IC3202AUDIO SW.

IC3601 SUBCCD V CHIP

IC3408Y CT MAIN

IC3089NVM

IC3408MID-XA

IC3110 Y CTSUB

IC3602 MAINCCD V CHIP

IC5513DY-CONV.

IC4103AUDIO

D/A

STBY+5V

STBY+5V

STBY+5V

DAT 1 CLK 1

WP

CLK 0

DAT 0

Q717

RESET

CLK

DATA

R829

R827

R834

IIC BUS

STBY+5V

WP

DATA

BC BD.

CN706/CN5501

CN703/CN6506

CN702/CN6504

CN7001/CN4104

CLK

CN3201/CN3500S BD.

A BD.

D BD.

B BD.

DAT. CLK

CN203/CN3203

910

65DTV02 1280

16

51

CRT Electrodes:Focus Accelerating

FocuspointElectron

beam

Picture Tube - Top View

Yoke

Electronbeam

Focus ArcRightside

Leftside

FlatCRTscreen

H D ynam ic focus vo ltage

rightle ftN o correction

HV to CRT

FlybackDFTransformer

Focus V to CRT

Dynamic Focus Block

Static Focus ConceptAn electron beam within the picture tube consists of many electrons thatare slowed down by the focus electrode. After passing through the focuselectrode, the accelerating electrode brings the beam to a fine point onthe screen. This focus point is positioned by adjusting the voltage at thefocus electrode relative to the accelerating voltage. The accelerating volt-age is usually fixed at the HV potential from the flyback secondary.

As the electron beam is moved from side to side (swept) by the magneticfield created by the external horizontal deflection yoke, the focus pointsform an arc as shown by the arrowheads. Early picture tube glass screenswere made into a similar arc to maintain focus at the left and right sides ofthe screen.

This means the focus point must be moved up at the left and right sides tomeet the flat picture tube screen.

Dynamic Focus ConceptThe job of the dynamic focus circuit is to change the focus points to meetthe flat picture tube screen. This is done by either increasing the staticfocus voltage when the beam is at the left and right sides of the screen ordecreasing the static focus voltage when the beam is at the middle of thescreen. Either method accomplishes the same effect. This dynamic fo-cus correction voltage is shaped like a parabola to match the focus arc.


ch4

ch3

ch1

CH1! 100 V~

CH3!50.0 V~ STOP

CH4!10.0 V= ALT MTB5.00us ch1+

1

3

4

T

CircuitryThe Dynamic focus circuitry is divided into two parts:

• DF Drive

• Modulated power supplyBoth signals are fed to DFT T8002 to make the dynamic focus voltage. Inthe scope shot, the top waveform is the DF Drive and the second is themodulated power supply. The third waveform is the flyback signal thatmarks the left and right sides of the screen.

52

IC5502OP AMP

1/2*

IC5502OP AMP

2/2*

DYNAMIC FOCUS 10/10/00

IC5511DQP

CONTROLCXA202GAS

1

2

19

11

14

21

5

2

11

13 Q5508,Q5509

DRIVERS

Q8022,Q8023

DRIVERS

Q8019,Q8020

DF PROT

1

17

*

TV SCREEN

DF FOCUSCORRECTION

IC5502 = NJM2901M

VTIM CN5503/2Y/C CRT DRIVE

IC201/54

T8001FLYBACK

HVCONV

CRTHV

CRTFOCUS

VOLTAGE

R8082

Q5501

C5509

R8102

C805110

T8002DFT

+135V

PR8101

Q8016SW

C80604.7

160V

Q8015SW

L8005

D8017DATA

CLK

IICBUS

SWO

DAC1

AFC-PLSH OUT

Q5030/C

22k

C8058

Q8018DF

OUTPUT

N

D BD.

15DTV 1268

6

4

3

91VDC

1

SM CATEGORY 2026ASDF ON - 0=ON, 1=OFFDF - CHANGES FOCUS START

53

ch4

ch3

ch2

ch1

CH1!10.0 V~

CH2! 200mV~

CH3!10.0 V~

CH4! 100 V= ALT MTB5.00us ch1+

1

2

3

4

T


ch4

ch3

ch2

ch1

CH1!10.0 V~

CH2! 200mV~

CH3! 200mV~ AVG

CH4! 100 V= ALT MTB5.00us ch1+

1

2

3

4

T

Dynamic Focus Signals


1 DF Drive signal T8002//pin 3 400Vp-p

2 Modulated power supply T8002//pin 1 140Vp-p

3 AFC-PLS (H fly pulses) IC5511/pin 19 10Vp-p


By examining the channel 2 and 3 waveforms, the modulated power sup-ply (ch 2) is turned off before and after the H sync pulse (ch 3). Thismeans there is no dynamic focus correction to the left nor right sides ofthe screen. However focus correction is applied to the center of the pic-ture as seen by the increasing voltage at the DF drive signal (ch1). Thefocus correction at the center brings the focus point to the same level asthe sides.

DF DriveThe DF drive signal is manufactured in IC5511 from horizontal and verti-cal timing pulse input at pins 19 and 21. The drive signal is output pin 11and delayed in a chain of amps (IC5502 and Q5501). Driver transistorsQ5508-9 and Q8022-23 buffer the signal as it travels from one part of theD board toward the other near the FBT. The final DF Output transistorQ8018 applies the signal to T8002/pin 3.

In the following waveforms you can see the low going drive signal fromIC5511/pin 11 (ch 2) become inverted and delayed (ch 3). The final drivesignal (ch 4) goes low to reduce the focus voltage at the right side of thepicture.

Modulated power supplyThe modulated power supply signal is also made in IC5511 from horizon-tal and vertical timing pulses input pins 19 and 21. IC5511’s output signalis AC coupled to switches Q8015 and Q8016 and finally applied to T8002/pin 1. The modulated power supply signal passes through T8002 to powerDF Output transistor Q8018 with modulated dynamic focus voltage.

In the scope shot of the DF power supply, the channel 2 waveform showstwo switching voltages in between the H sync pulses (channel 1). Thetwo positive switching voltages in channel 2 result in low going B+ parts ofchannel 4’s waveform. The reduction of B+ corresponds to no focus cor-rection at the left and right sides of the picture. However, dynamic focuscorrection does take place at the center of the picture when there is B+output Q8016/Collector.

DF Drive Signals


1 AFC-PLS IC5511/pin 19 10Vp-p

2 Dynamic Drive IC5511/pin 11 0.3Vp-p

3 Delayed DF Drive Q8018/Base 10Vp-p

4 Final DF Drive Signal Q8018/Collector 400Vp-p

Time Base = 5usec/div.

54

IC5502OP AMP

1/2*

IC5502OP AMP

2/2*


IC5511DQP

CONTROLCXA202GAS

1

2

19

11

14

21

5

2

11

13 Q5508,Q5509

DRIVERS

Q8022,Q8023

DRIVERS

Q8019,Q8020

DF PROT

1

17

*

TV SCREEN

DF FOCUSCORRECTION

IC5502 = NJM2901M


IC201/54

T8001FLYBACK

HVCONV

CRTHV

CRTFOCUS

VOLTAGE

R8082

Q5501

C5509

R8102

C805110

T8002DFT

+135V

PR8101

Q8016SW

C80604.7

160V

Q8015SW

L8005

D8017DATA

CLK

IICBUS

SWO

DAC1

AFC-PLSH OUT

Q5030/C

22k

C8058

Q8018DF

OUTPUT

N

D BD.

15DTV 1268

6

4

3

91VDC

1


55

DF Switching Signals


1 AFC-PLS IC5511/pin 19 10Vp-p

2 SWO (Switch control) IC5511/pin 14 0.3Vp-p (main)

3 Switch Drive signal Q8016/Base 0.1Vp-p (main)

4 Final DF Drive Signal Q8016/Collector 140Vp-p

The purpose of “DF Protect” transistors Q8019 and Q8020 in the switch-ing path is unknown as of this writing.

AdjustmentThe manual focus adjustment is located on the flyback (the only control).Input a crosshatch and adjust the focus control until you can see the scan-ning lines in the picture.

Dynamic focus can be turned ON/OFF and phase adjusted (start loca-tion) in the service mode. Data group #7 with the heading “2026” con-tains two items related to dynamic focus:

Service Mode Category 2026

Item Name Purpose

DFON Data 0 = dynamic focus ON

Data 1 = dynamic focus OFF

DF Positions IC5511/pin 14 switching pulses to change thestart of the dynamic focus points on the screen.

Service mode item “DFON” turns OFF the switching voltage from IC5511/pin 14. This can be seen in the following chart that contains the DCvoltages of the output stage.

DF Output Stage Voltages

DFON data = Q8018/C T8002/pin 3 T8002/pin 1

0 (DF is On) -14Vdc 89Vdc 91Vdc

1 (DF is Off) 0.3Vdc 0Vdc 0Vdc

56

IC5502OP AMP

1/2*

IC5502OP AMP

2/2*


IC5511DQP

CONTROLCXA202GAS

1

2

19

11

14

21

5

2

11

13 Q5508,Q5509

DRIVERS

Q8022,Q8023

DRIVERS

Q8019,Q8020

DF PROT

1

17

*

TV SCREEN

DF FOCUSCORRECTION

IC5502 = NJM2901M


IC201/54

T8001FLYBACK

HVCONV

CRTHV

CRTFOCUS

VOLTAGE

R8082

Q5501

C5509

R8102

C805110

T8002DFT

+135V

PR8101

Q8016SW

C80604.7

160V

Q8015SW

L8005

D8017DATA

CLK

IICBUS

SWO

DAC1

AFC-PLSH OUT

Q5030/C

22k

C8058

Q8018DF

OUTPUT

N

D BD.

15DTV 1268

6

4

3

91VDC

1


57


ch2

ch1

CH1! 200mV~

CH2! 100 V= MTB10.0us H xx

1

2

T

ch2

ch1

CH1! 200m V~

CH 2! 100 V= M TB10.0us H xx

1

2

T

DQP Circuit Corner Focus Correction

Focus at the sides of a Wega flat screen picture tube was accomplishedwith the Dynamic Focus Circuitry. Focus at the corners is corrected usinga Dynamic Quadrapole circuit. Although they are independent circuits, afailure in one will make it appear as if the other is also defective. There-fore, both the Dynamic Focus and DPQ circuits must be tested whenthere is poor focus on a portion of the screen. The DQP circuit is alsoused to correct for mis-convergence at the perimeter.

CircuitryIC5511 manufactures the corner focus correction signal that is amplifiedand applied to four coils placed at the neck of the CRT. There are twosignals marked Para 1 and Para 2 that output IC5511/pins 4 and 6. Theyare amplified and applied to the four QP coils.

At power ON, Q5008 and Q5505 use C5027 to momentary disable theDQP amplification in IC5504. This is so the beam will be unaffected byincorrect voltages at start up.

Q5502, Q5507 and IC5502 monitor the horizontal width (AFC-PLS fromQ5030) and corrects for focus if the width changes momentarily. This isaccomplished by changing the DC input voltage of IC5504/pin 2 propor-tional to the width of the picture.

The waveforms in the following scope shot are made by IC5511/pin 4 andapplied to the QP coils at CN5509/pin 6.

DQP-- Signal Processing


1 DQP negative signal IC5511/pin 4 0.4Vp-p

2 Amplified DQP- signal CN5509/pin 6 130Vp-p


The waveforms in the following scope shot are made by IC5511/pin 6 andapplied to the QP coils at CN5509/pin 4.



1 DQP positive signal IC5511/pin 6 0.4Vp-p

2 Amplified DQP + signal CN5509/pin 4 300Vp-p


By comparing both output waveforms, we can see the resultant DQP cor-rection signal (difference of the two waveforms) is not that complex.

58

DQP FOCUS CORRECTION 9/29/00

POWER ONINHIBIT

Q5008 Q5505

IC5506DQP-AMP1

LA65002 419 4

21

1

2

6

9

IC5504DQP-AMP2

LA65002 4

1

IC5502AMP

Q5502Q5507

3.5OHMS

IC5511DQP

CONTROLLERCXA2026A

SDA

SCL

PWM

PARA2

AFC-PLSQ5030/C

VTIMCN5503/2IC201/54

R5696

C5614

IIC BUSFROM

IC701/28,31

C55310.1

D5514D5515R5564

C5533R5563

R555418k

L5504

C55480.47

R5588 L5505

CN5509

QP-

QP+

MAIN+12V

R5056

C5027

R5577180k

PARA 1

HORIZ.AFC-PLSQ5030/C

67DTV02 1282

6

4

ADJUSTMENT

SERVICE MODE: CATEGORY 2026ASDQP FOCUS CORRECTIONITEM 1 - DQP - PWM LEVELITEM 3 - DQPD - DC LEVELITEM 4 - QPDV - VERT. MODITEM 5 - DVS - TILTITEM 7 - DQPA - AMPLITUDE

59



1 Amplified DQP - signal CN5509/pin 6 130Vp-p

2 Amplified DQP + signal CN5509/pin 4 300Vp-p



ch2

ch1

CH1!50.0 V~

CH2! 100 V= MTB10.0us- 1.18dv L xx

1

2 T

AdjustmentThe waveforms from IC5511 can be changed from the service mode toaffect the starting point of focus correction on the screen, the amount offocus, and convergence. These items are found in the service modecategory 2026AS.

60

DQP FOCUS CORRECTION 9/29/00

POWER ONINHIBIT

Q5008 Q5505

IC5506DQP-AMP1

LA65002 419 4

21

1

2

6

9

IC5504DQP-AMP2

LA65002 4

1

IC5502AMP

Q5502Q5507

3.5OHMS

IC5511DQP

CONTROLLERCXA2026A

SDA

SCL

PWM

PARA2

AFC-PLSQ5030/C

VTIMCN5503/2IC201/54

R5696

C5614

IIC BUSFROM

IC701/28,31

C55310.1

D5514D5515R5564

C5533R5563

R555418k

L5504

C55480.47

R5588 L5505

CN5509

QP-

QP+

MAIN+12V

R5056

C5027

R5577180k

PARA 1

HORIZ.AFC-PLSQ5030/C

67DTV02 1282

6

4

ADJUSTMENT

SERVICE MODE: CATEGORY 2026ASDQP FOCUS CORRECTIONITEM 1 - DQP - PWM LEVELITEM 3 - DQPD - DC LEVELITEM 4 - QPDV - VERT. MODITEM 5 - DVS - TILTITEM 7 - DQPA - AMPLITUDE

61

Convergence correction areas

TV screen

Correctionareas

Correctionareas

Convergence Circuit

ConceptThe purpose of the convergence circuit is to create a dynamic signal thatis applied to the convergence (CY) winding within the main yoke. Theconvergence winding is positioned so the dynamic signal will move one ortwo electron beams more than the third. This is how an electronic signalcan unite all three beams together on the screen. The convergence cir-cuitry corrects at the four sides and right corners of the TV screen in thisTV.

CircuitryAt power ON, convergence data stored in the Non-Volatile Memory IC707is retrieved by Main uCom IC701 (not shown) and sent to IC5513 via theI2C bus. Within ICI5513, this data shapes the vertical and horizontalsignal input to pins 3 and 14 and produces two outputs.

The H Stat output at IC5513/pin 8 corrects for left and right mis-conver-gence. The V Stat output at IC5513/pin 9 corrects for top and bottom mis-convergence. The two signals are combined externally and amplified byIC5515 into a 10Vp-p waveform at the convergence yoke CN5510/pin 3.IC5513’s input and output signals are listed in the chart:

IC5513 s Input / Output Signals

Name IC5513/pin Voltage Purpose

VTIM 3 1.8Vp-p, 4.8Vdc Input Vert sawtoothramp

AFC-PLS 14 10Vp-p, 0.74Vdc Input horiz pulse

Ref 5 5Vdc reference for IC5515

H Stat 8 100 mV p-p left/right conv. signal

V Stat 9 200 mV p-p top/bottom conv. signal

Convergence Output


1. VTIM (Vertical timing) input IC5513/pin 3 1.8Vp-p

2. Convergence Output CN5510/pin 3 10Vp-p

Time Base = 5msec/div

CH1!1.00 V~ STOP ENV

CH2!5.00 V~ MTB5.00ms ch1+

1

2

T

AdjustmentThe convergence yoke signal is adjusted in the service mode. Data group#6 with the heading “D-Conv” has nine adjustment parameters that cor-rect for mis-convergence, mostly at the right side of the TV screen.

62

CONVERGENCE CIRCUIT 10/10/00

IC5513DY-CONV

CXA8070AP

3

14

16

17

5

8

9

1

2

3

8

+

-

4

3

1

10

R5699 V STAT

R5693 H STAT

5V REF.CY PARTOF MAIN

YOKE

CN5510

+15V

-15V

MAIN+12V

SOURCE

VTIMIC201/54

AFC-PLSQ5030/C

R5648R5712 R5711

IC5515STK390-910

DATA CLOCKIIC

BUS

+15V

D BD.

16DTV02 1272

IC500312V REG

SERVICE MODECATEGORY D - CONV9 ADJUSTMENT ITEMS

63

ch2

ch1

CH1 2.00 V=

CH2 2.00 V= MTB5.00ms- 1.32dv H xx

1

2

T

Picture Tilt Correction

When flat screen picture tubes were first manufactured, lines that werenot straight were very noticeable. This meant additional pincushion andconvergence circuitry was required to improve the picture quality.

If the yoke were a little off center, the slight tilt of the picture would also benoticeable. A picture tilt circuit was added to Sony flat screen WegaTVs to correct for this tilt. The user can perform Tilt Correction from thesetup menu. The coarse adjustment is performed in the service mode bychanging the data in category 2150D, item 6 (NSCO).The circuit required a DC voltage to be applied to a N/S coil suspendedabout the perimeter of the yoke housing at the bell of the tube. Applyinga voltage to this N/S coil produces a magnetic field. The field offsets thethree beams as they emerged from the electron gun structure, rotatingthe picture.

A sawtooth waveform is also added to this DC voltage for horizontal trap-ezoid correction. Therefore, there is a DC voltage and a sawtooth signalpresent at the coil. Both the DC level and sawtooth amplitude can becontrolled in the service mode.

Tilt Correction CircuitThe tilt correction DC voltage and the horizontal trapezoid correctionsawtooth signal are created by IC201. The signal and DC voltage leaveIC201/pin 51 and are amplified by IC5510 before being sent to the N/Scoil. The voltages in normal operation and when the user has set the tiltto both extremes (+7) are shown in the chart.

Tilt correction Voltages

Location Name 0 rotation -7 rotation +7 rotation

CN201/pin 5 Output of IC201 4Vdc 5Vdc 3Vdc

CN9102/pin12

N/S coil 0V -4.8Vdc 5Vdc

Horizontal Trapezoid Correction CircuitThe trapezoid correction signal takes the same path the tilt correction DCvoltage did. This signal comes from IC201/pin 51 as a 60 Hz 0.3Vp-psawtooth waveform. IC5510 brings the signal level up to 2Vp-p for themain sawtooth plus 4Vp-p for the low going spike.

Horizontal Trapezoid Correction Waveform


1 V Saw 1 CN201/pin 5 0.3Vp-p

2 N/S Coil CN5509/pin 12 6Vp-p


AdjustmentTilt - The DC voltage from IC201/pin 51 can be adjusted in the servicemode, as well as from the user’s setup menu. Access the coarse adjust-ment by locating category 2150D-1 in the service mode. Scroll down toitem number 6 - NSCO to change the tilt from the service mode.

H Trapezoid - The sawtooth amplitude from IC201/pin 51 can also becontrolled from the service mode, independent of the DC voltage. In thesame category as for tilt (2150D-1), scroll down to item 7 - HTPZ. Chang-ing its data changes the signal amplitude and corrects for trapezoid dis-tortion.

64

PICTURE TILT CORRECTION 10/10/00

IC707NVM

N24C8

IC201 Y/CCRT DRIVECXA2150Q 51

25 26

5

IC701MAIN uCOM

M306V2-DX1A

31 28

29

30

1

24

5

3

W BD.IIC

BUS

DATA CLK1

CLK O

V SAW 1

DATA O

LA6500

R5678

R5679C5601

-12V

R5669

R5670 MAIN+12V

R5613270

R57051

0.25V4V

CN201/CN5503

CN5509/CN9102

D BD.

N/SCOIL

A BD

0V

+

-

66DTV02 1281

11

12

R5688

N/S COIL

YOKE

PICTURETUBEREAR

38.2OHMS

ADJUSTMENTS

USER:SERVICE MODE:

SET UP MENU - TILT CORRECTIONCATEGORY 2150D-1ITEM 6 - NSCO - 0-15ITEM 7 - HTPZ - HORIZ. TRAPEZOID

65

Straighten top& bottom linesusing VPINadjustment


ch2

ch1

CH1! 200mV~ STOP

CH2!1.00 V~ MTB5.00ms L=2 ch1p

1

2

Vertical Pincushion Correction Circuit

ConceptThe geometry on a flat screen picture tube is more critical than that on acurved picture tube. This new circuit applies an electronic signal to a coilat the CRT electron gun to straighten the top and bottom lines on a pic-ture.

CircuitryAt power ON, data stored in the Non-Volatile Memory (NVM) IC707 isretrieved by Main uCom IC701. IC701 distributes the data to various ICsin the TV via the I2C bus. The Y/C CRT Drive IC201 is sent just the datathat pertains to it. Within IC201, a correction signal is made consisting ofmixed horizontal and vertical components. This signal is amplified byIC5514 and applied to the pincushion coil.

The correction signals before and after amplifier IC5514 is shown in thisscope shot.

Vertical Pincushion Correction Signal


1 VSAWO CN201/pin 6 0.3Vp-p

2 PincushionOutput

CN5509/pin 2 0.5Vp-p = main waveform

3.5Vp-p including spike


The Vertical Pincushion coil resistance is 18.9 ohms between CN9102/pins 1 and 2 without the plug connected.

AdjustmentThe vertical pincushion signal is adjusted in the service mode with the aidof an external cross hatch generator. Data group #4 with the heading“2150D-1” contains the VPIN adjustment in its fifth item. The fourth itemVCEN also changes the DC level of the VPIN signal.

VPIN must be adjusted in all three deflection modes:

1. Full - (normal NTSC) 4:3 signal input.2. V Comp1 - (480p) 16:9 video 5 or 6 input.3. V Comp2 - (1080i) 16:9 video 5 or 6 input.

66

VERTICAL PINCUSHION CORRECTION CIRCUIT 10/10/00

TV SCREEN

IC707NVM

N24C8

IC201 Y/CCRT DRIVECXA2150Q 50

25 26

6

IC701MAIN uCOM

M306V2-DX1A

31 28

29

30

1

24

5

3

W BD.IIC

BUS

DATA CLK1

CLK O

V SAW O

DATA O

IC5514V PIN OUT LA6500

R5700

R5615C5616

-12V

R5697

R5698 MAIN9V

R5710270

R57041

0.25V

4V

CN201/CN5503

CN5509/CN9102

CRT

V PIN +

V PIN -

A BD.

D BD.

0V

+

-

20DTV02 1271

SLIGHTBOW

INWARDS

NO CORRECTION

1

2

SM CATEGORY 2150D-15 ITEMS -ADJ. IN ALL 3 MODES:1. FULL (NORMAL)2. V COMP1 - 480P 16:93. V COMP2 - 1080I/VERT ENHANCED

67

c h4

c h3

c h2

c h1ch3 : dc = 26 .2m V

ch4 : dc = 16 3m V

C H 1!2.0 0 V=

C H 2 !2.0 0 V=

C H 3 !1.0 0 V~

C H 4 !2.0 0 V= C H P M TB 5.00m s ch1 -

1

2

3

4

T

Vertical ProcessThe vertical sync source selection on the B board is new, but the oscillatorand output stage is traditional.

Vertical SyncThe vertical frequency is 60Hz but the sync is selected by IC4313 fromone of three sources:

1. MID circuit when Progressive scan is selected by the user (IC4313/pin 13 input).

2. Main video input from input switch IC3048 when interlace scan is se-lected (IC4313/pin 1 input).

3. Sub video input from sub picture switch IC3001 when this picture isthe only one selected (from the Twin mode). (IC4313/pin 2 input)

Switch IC4313 selects one input that outputs pin 14. The selection isbased upon control voltages from MID uCom IC3090 and the Main uComIC701 input IC4313/pin 9-11.

Vertical OscillatorThe vertical oscillator inside IC201 starts and outputs pins 52 and 53 whenMain 9V is applied to IC201/pins 55 and 61. Data need not be present forvertical drive to output like other Y/C “Jungle” ICs.

Vertical OutputThe vertical stage is traditional. The vertical oscillator signal is amplifiedin IC5004 and used to drive the vertical deflection yoke.

To make sure the vertical stage is operational, a sample of the verticalsignal is returned to IC201/pin 35. If IC201 detects a loss of vertical pulses,it blanks the picture. If the loss remains for two seconds, IC201 sendsdata to Main uCom IC701 to shut down the set and store the verticalfailure code.

Vertical pulses from IC5004/pin 3 are sent to the MID uCom IC3090/pin35 to identify the end of the scan for interlace/progressive scan timing.

The waveforms of this stage show the basic operation from sync input(ch1) through drive (ch 2) to feedback (ch 3 & 4).

Vertical Stage Waveforms


1 Mid VS (sync) CN003/pin B15 3Vp-p

2 V Drive + CN5503/pin 4 1.8Vp-p

3 Protect signal CN5505/pin 7 1Vp-p

0.8Vdc

4 Timing CN5501/pin 1 3.5Vp-p

Time base =5msec/div.

Vertical Compression / 16:9 EnhancementWhen a 16:9 video signal is input from video 5 or 6, the aspect ratio isincorrect for this 4:3 TV screen and the picture will appear too tall. Thevertical is compressed slightly to maintain the correct aspect ratio. Theuser chooses this compression from the menu. In the setup menu under16:9 enhancement, he can choose AUTO or ON. In AUTO, the MIDcircuit on the D board detects the higher horizontal frequency associatedwith a 1080i 16:9 picture and reduces the vertical sweep. A 480p signalcan be in either aspect ratio. Therefore the user must manually select ONfor the vertical compression.

68

VERTICAL PROCESS 10/6/00

IC3413SYNC SWSN74LV4053A

13

1

2

10

9 11

14 C15

4

B15

IC201Y/C

CRT DRIVECXA2150Q

42

35

3

53

52

1 65

7 1

4

3

7 1

6

5

R50461.8

R50521.5

TH5001R5599

10kYDY

L5001

V PROT

TIMING

R5023D5002

-15V(D BD.)

+15V(D BD.) Q5005

+15V

N

R5018

CN5002

D50015.1V

+

V SYNC FOROSD MAIN

uCOMIC701/97

VFB TOMID uCOMIC3090/35

(B BD.)FOR PROG./

INTER TIMING

CN201/CN5503

CN3205/CN003

CN706/CN5501

V SYNCPROGRESSIVEV SYNC FROM

IC3408

VTIM (INTERLACE)FROM IC3048/15 YCT MAIN

SEL V OUT(SUB PIX)FROM IC3001/23 COMP J-F

SYNC SELIC3090/10 MID uCOM

TH CONT/X SWIC701/52(A BD.)Y/C CRT DRIVE

V DRV-

+

PROT

A BD.

B BD.

13DTV02 1269

55

CN203/CN5505

61

MAIN9V

D BD.

MIDVS

IC5004 V OUTSTR9379

R5029

1Vp-p

4Vp-p

69P M 3394 , FLU K E & PH IL IPS

c h2

c h1ch2 : pkp k= 1 .55 V

ch2 : freq= 60 .0 H z

C H 1 !2.0 0 V=

C H 2 ! 500m V~ M TB2 .00m s- 0.90 dv ch 1+

1

2

T

RampIrregularity

To keep the information in the vertical blanking area hidden in the verticalarea above the picture, the vertical drive waveform from IC201 is altered.After the electron beam retraces to the top of the screen, normal down-ward scan begins. After the blanking interval, the beam drops down thescreen before resuming sweep. The vertical ramp’s amplitude is alsoreduced. This can be seen when comparing the normal and compressedvertical waveform. Notice there is an irregularity at the beginning of thevertical ramp in the compressed vertical mode.


ch2

ch1ch2: pkpk= 1.78 V

ch2: freq= 122 Hz

CH1!2.00 V=

CH2! 500mV~ MTB2.00ms- 0.90dv ch1+

1

2

T

Normalverticalramp

Vertical Drive Signal - Normal


1 MID VS (sync) CN3205/pin C15 3.5Vp-p

2 V Drive (osc) CN5503/pin 4 1.5Vp-p


Vertical Drive Signal - Reduced (16:9 Mode)


1 MID VS (sync) CN3205/pin C15 3.5Vp-p

2 V Drive (osc) CN5503/pin 4 1.3Vp-p


70

VERTICAL PROCESS 10/6/00

IC3413SYNC SWSN74LV4053A

13

1

2

10

9 11

14 C15

4

B15

IC201Y/C

CRT DRIVECXA2150Q

42

35

3

53

52

1 65

7 1

4

3

7 1

6

5

R50461.8

R50521.5

TH5001R5599

10kYDY

L5001

V PROT

TIMING

R5023D5002

-15V(D BD.)

+15V(D BD.) Q5005

+15V

N

R5018

CN5002

D50015.1V

+

V SYNC FOROSD MAIN

uCOMIC701/97

VFB TOMID uCOMIC3090/35

(B BD.)FOR PROG./

INTER TIMING

CN201/CN5503

CN3205/CN003

CN706/CN5501

V SYNCPROGRESSIVEV SYNC FROM

IC3408

VTIM (INTERLACE)FROM IC3048/15 YCT MAIN

SEL V OUT(SUB PIX)FROM IC3001/23 COMP J-F

SYNC SELIC3090/10 MID uCOM

TH CONT/X SWIC701/52(A BD.)Y/C CRT DRIVE

V DRV-

+

PROT

A BD.

B BD.

13DTV02 1269

55

CN203/CN5505

61

MAIN9V

D BD.

MIDVS

IC5004 V OUTSTR9379

R5029

1Vp-p

4Vp-p

71

Audio Block Diagram

FeaturesThe XBR400 audio section features:

XBR400 Series Audio Section Features (Menu selection)

Feature Description Circuit location

SteadySound

Reduces dynamic range toprevent drastic volume changeswhen switching channels or whena commercial comes on.

Audio ProcessorIC7001

TruSurroundSound

Simulates a 3D sound using thestereo signal and only the TVspeakers

IC4101, IC4103

SimulatedSurround

Adds echo to a Mono signal tosimulate a larger room.

Audio ProcessorIC7001

SeparateWoofer andTweeter

Tweeter is located at the bezel forbetter HF dispersion.

15Watts/channelRMS

IC packages. Power comes fromfusible resistors on the D board.

IC7002 & IC7005

Fixed orVariableaudioOutput

Output is present only when thespeaker is switched OFF from themenu. The fixed or variable levelcan be chosen

IC7001

Signal PathB Board

IC3201 (CXA2069) is an analog switch that selects both audio and video.Using I2C data from the Main uCom IC701 (not shown), IC3201 can se-lect between the following:

• Main Tuner

• Sub Tuner

• Video 1 - 4

The output of IC3201 is sent to IC3202. IC3202 is an analog switch thatonly handles audio. The input choices are:

• Main signal

• Sub signal

• Video 5

• Video 6Selection of Main Vs Sub sound is used in the Twin mode. The outputsgo to the rear monitor output jack and the S board for TruSurround Soundprocessing.

S Board

The L/R channel audio is applied to both TruSurround IC4101 and SwitchIC4102. The TruSurround IC4101 outputs the L/R audio if the TruSurroundmode is not selected.

When TruSurround is selected, the second output from TruSurroundIC4101 to D/A IC4103 is used. IC4103 converts the digital data to acontrol signal that instructs switch IC4102 to return L/R audio to a differ-ent part of IC4101 for TruSurround sound processing. The output of IC4101is into the Audio Processor IC7001 on the A board.

A Board

IC7001 handles the simulated and steady sound processing. It also ad-justs the volume, treble, bass, and balance based upon the user com-mands. Its output is split into three paths. The speaker path is to a highand a low pass filter, then to the 15W power amplifiers IC7002 and IC7005.The third path is through buffer IC7007 to the TV’s rear panel audio out-put jack. This path is muted (not shown) when the TV speaker is ON. Ifthe user turns the speaker OFF from the menu, it is implied the user hasan external amplifier or audio processor connected to the rear audio jackso this jack is unmuted (enabled). The user must then select a variable orfixed output level.

72

DX1A AUDIO BLOCK DIAGRAM 10/10/00

IC3203BUFFERNJM4558

IC3202ANALOG

SWAUDIO

TEA6422

AUDIO 4

IC4102ANALOG SW

NJU4066

IC4103D/A

CXA1315

IC4101 TRUSURROUND NJM2180

A14A15

5 7

109

109

IC7001AUDIO

PROCESSORBH3868

IC7002POWER AMP

TA8216

IC7006LOW PASSNJM4558

IC7005POWER AMP

TA8216

IC7007BUFFERNJM4558

1

7

3

5

(HIGH PASS)

AUDIO 5AUDIO 6

AUDIO 3

AUDIO 2

AUDIO 1

SUB

MAIN

INPUTS:

THICKERLINES

DENOTEL/R

SIGNALPAIR

MONITOROUT

LINE OUT

DATA/CLKIIC BUS

IIC BUS

CN7008

CN7001

CN4101

CN3205/CN003

MAIN

SUB

MON

L

R

H-L

H-R

W-L

W-R

SPEAKERS

B BD.

A BD.

S BD.

17DTV02 1270

5 7

IC3201ANALOG

SW(A/V)

CXA2069

U BD.

73

Front of TV

D Board

FBT

CN6506

8

10

Q8009

D6017

IC6007

CN5505

A Board

IC6007

I O G n/c

Self Diagnostic BlockThe Self-Diagnostic circuit is a program of the Main uCom IC on the Aboard. This program monitors seven general faults that result in one ormore of the following:♦ TV shutdown (AC relay is turned off);♦ TV Latched OFF** (AC relay is held off); or♦ A dark picture (no RGB signal).

As an indication of failure, the Main uCom blinks the Standby LED a num-ber of times, pauses, then repeats.

Faults Monitored by Main uCom IC

StbyLEDBlinks

Symptom Bd MonitoredCircuit

Test point

(verification)

NormalVoltage

0 X Shutdown D +200VOCP (HV)

Q8009/C 0.1Vdc

2 X Shutdown D +135VOCP

CN6506/pin8

0V

3 X Shutdown A Unreg 7VOVP

D6017/C 0V

3 X Shutdown D +135VOVP

CN6506/pin7

0.1V

4 X Shutdown D V Out

Loss

CN5505/pin7

0.78V

5 X Blanking C/A/G2adj

IK balance CN202/pin 8 3 pulsesin verticalinterval.

6X Shutdown A Set 5V

OCP

IC6007/Output

5.0Vdc

7X Shutdown D H OutOCP

CN5505/pin8

0V

** TV latched OFF. Press power button twice to turn TV back on

OSD Diagnostics

In addition to the blinking Stby LED, the Main uCom records the numberof times the failure occurred. This is useful when the user complains ofan intermittent shutdown.

Access the Diagnostic Mode

To enter the test screen, first press these remote control buttons one at atime: Display, 5, Vol —, Power On.

The screen will list the circuit monitored and the number of times thefailure has occurred.

Clear the OSD Diagnostic numbers

To clear the number of failures from the test screen press:

Press 8, Enter.

74

SELF-DIAGNOSTIC BLOCK 10/4/00

+135VOVP

IC701MAINuCOM

UNREG.7V

OVP

IC60075V REG.

+135VOCP

POWER OFFLATCH

D BOARD

Q8009+200VOCP(HV)

OSDRGB

LOW BOCP

UNREG.7V

DATA/CLK

SET 5VRGB

TO CRT

IK SIGNALWHITE BAL

FAILURE

V OUTLOSSH OUTOCPCN203/

CN5505

CN202/CN9001

CN6506/CN703

ACRELAYON/OFF

CN6504/CN702

STANDBYLED

7

8

IC201Y/CCRT

DRIVE

8

7

8

C BD.

D BD.

D BD.

D6018

D6017

10DTV02 1260

1

NUMBER OF TIMES THESTANDBY LIGHT BLINKS

AFTER SHUTDOWN

X

3 X

0 X

2 X

0 X

3 X

6 X

5 X

4 X

7 X

75

Self Diagnostic CircuitWhen the TV shuts down and the standby LED blinks, the Main uComIC701 knows which failure activated the shutdown. The number of timesthe Standby LED blinks indicates the problem board or section.

Shutdown - Standby light does not blinkCircuit - The current on the +200 volt line is monitored by R8043 andQ8009. This 200-volt line supplies the High Voltage Converter stage,which feeds the flyback. A short in the flyback or excessive high voltagewill demand sufficient current to shut down the TV. Since there is noconnection to the Main uCom IC701, the standby LED will not indicatethis failure.

Unstable standby voltage or a defect in the basic latch circuit (Q6530 andQ6532) will also cause the TV to shut down without the standby lightblinking. This last problem is rare.

Testing - To determine if the +200V line to the HV Converter stage iscausing shutdown, monitor the voltage at Q8009/Collector at power ON.The voltage should not rise above 0.2Vdc at power ON. A higher voltagemeans the problem is on the D board in the Converter.

Shutdown - Standby light blinks two timesThere are two +135V OCP monitoring circuits. The first circuit will causethe Standby light to blink two times and the second will cause the light toblink seven times. Both sensing and output circuits are on the D boardbut the indicating circuit is on the A board.

Circuit - R6598, R6591, Q6520, Q6521, and Q6524 monitor the currenton the +135V line from the Secondary Power Supply. The +135 volt linesupplies:

♦ Velocity modulation (V) board♦ Horiz Output (Q5030) and PWM (Q5003) stage (D board)♦ The HOT supplies +200V to the RGB Output ICs (C board).Testing - The blinking LED indicates the failure, but the problem could bein one of three locations: The H. Output/PWM stage, the sensing circuiton the D board, or the sensing circuit on this A board. Verify this problem

by monitoring CN6506/pin 8 as you power ON. If the voltage does notrise above 0v at power ON, the problem is not on the +135V line. If thevoltage reaches 1.2V, disconnect the V board and try again. If the CN6506/pin 8 voltage still rises to 1.2V, test the H Output and PWM transistors orreplace the entire D board.

Shutdown - Standby light blinks three timesCircuit - There are two possible causes for this LED indication caused byexcessive voltage. Two power supply voltages are monitored, +135V onthe D board and Unreg. 7V on the A board. On the D board, the maxi-mum voltage on the +135V line is +140V. This is monitored by IC6505and Q6522. On the A board, the maximum voltage on the unregulated 7Vline is 8.2V. This is monitored by D6014.

Testing - The problem can be on either the A or the D board. LocateD6017/Cathode or D6014/Anode and monitor this voltage as you powerthe TV. If the voltage rises above 1V, the problem is in the A board’spower supply (regulation). To test the power supply on the D board, monitorCN6506/pin 7. If this voltage rises above 0.6Vdc, the problem is on the Dboard.

Shutdown - Standby light blinks four timesCircuit - A vertical failure because of the output IC or power supply (bothon the D board) will cause the Y/C, CRT Drive IC201 to send emergencydata to Main uCom IC701. IC701 turns the TV by opening the AC relay(IC701/pin 69 goes LOW).

Testing - Measure the +15v and -15V to the vertical output IC5004/pins 2and 4 before you suspect the IC5004 itself.

Blanking - Standby light blinks five timesCircuit - The Ik signals are measured by Y/C, CRT Drive IC201 and areused to adjust the RGB gain to maintain color balance. As the picturetube ages, the Ik signals may fall below the threshold for automatic bal-ance and mute/blank the picture.

Testing - Increase the G2 control on the CRT’s C board. If that does notreturn cathode current to within operating range so the picture will ap-pear, examine each filament to see if it is lit.

76

SELF-DIAGNOSTIC CIRCUIT 1/2 10/3/00

Q6530,Q6532LATCH

IC6506OVP

8

Q6520,Q6521OCP

R6602

Q8009OCP

Q6501AC RELAY

1

7

44

45

69

43

30

29

IC60075V REG.

1

R6019D60174.7V

D60147V

R60151k

IC701MAINuCOM

OCP

OVP

D BD. A BD.

R6593

R6598

R6591STBY 5V

R6612

Q6524

P

P

+135V(SEC P.S.)

+135V SOURCE

+15V

Q6527

AC FROMF BD.

200V TOHV CONV.

+200V(SEC P.S.)

R80431 OHM D8003

D6537 OVP OCP

Q6522

D6501

AC TO+200V/+135V

POWERSUPPLY

ACRELAY

CN6506/CN703

CN6504/CN702

D6018

UNREG.7V

SET 5VSOURCE

STANDBYLED

TO/FROMYC/, CRT

DRIVEIC201/26,27

DAT O

CLK O

UNREG.7V(PRI P.S.)

11aDTV02 1258

48

77

CN6505 CN6006

CN6504 CN702

CN6506 CN703

CN5503 CN201

CN5505 CN203

CN5501 CN706

10

1

101

11

1

10

18

1

8

1

Bridge Connectors

6 1

CN6501

D Board

6

1

A Board

CN6005

HotGround

IC 60 07

IC6007

Back of TV

O

I O G n/c

Then use your scope to examine the signal to the cathode. Go to CN9001/pins 1, 3 and 5 to see if there is a signal coming into the C board. Nextcheck the signal at the CRT cathodes. If they are present, check the IKsignal from CN9001/pin 8 of the C board. You should see three pulsesand be able to change the level of the signal with the G2 control. If youget about 1Vp-p pulses at pin 8, this is the normal output from the CRT/Cboard so the problem is on the A board about IC201.

Shutdown - Standby light blinks six timesCircuit - IC701/pin 43 monitors the Set 5V supply from the power supplyon the A board. This voltage feeds almost all the boards. A short on theSet 5V line will cause IC701 to shut off the AC relay (IC701/pin 69 goesLOW).

Testing - At power ON, measure the “Set 5V” at regulator IC6007/Outputon the A board. The trip voltage is 3.7Vdc. If this voltage remains low atpower ON, unplug the B board within the A board and power ON again.

Shutdown - Standby light blinks seven timesThere are two +135V OCP monitoring circuits. The first circuit will causethe Standby light to blink two times and the second will cause the light toblink seven times. Both sensing and output circuits are on the D board,but the indicating circuit is on the A board.

Circuit - The second OCP circuit monitors the current through the PWMOutput (Q5001-3) that supplies B+ voltage to the H. Output transistorQ5030. When there is excessive current drawn by the Horizontal Outputstage, Q5018 turns OFF, permitting IC201/pin 34 to rise to a threshold of1.2Vdc. IC201 blanks the picture to prevent a CRT line burn and sendsdata to IC701/pin 30 to shut down the TV.

Normal Operating Voltages

Location At power ON Operating

IC5007/pin 8 0.07V 0V

IC5007/pin 9 3V 3V

IC5007/pin 1 2.6V 2.6V

Q214/base 5V for 5 seconds 0V

Q214 is turned on for five seconds at power ON to permit comparatorIC5007 time to stabilize.

Testing - If the Standby light blinks two or seven times, the problem ismost likely on the D board where the sensing and Horizontal Output stagesare. On the D board, if the Horizontal Output (Q5030), PWM (Q5003)transistors, and video output ICs (C board) are good, suspect the compo-nents in the sensing circuit (same board). The sensing parts are Q5004,IC5007 and Q5018.

Verify that this circuit is causing the shutdown by disconnecting the H.Output Transistor Q5030 and monitor the voltage at CN5505/pin 8 as youpower ON. If this voltage rises above 1 volt, this +135V OCP circuit isresponsible. Suspect Q214 on the A board and the following main partson the D board:

R5013, Q5004, IC5007, delay cap C5006, Q5018.

78

SELF-DIAGNOSTIC CIRCUIT 2/2 10/3/00

IC201Y/C,CRT

DRIVE

25

58

26

35

8

7

834

IC5004V OUT 65

L5001

R9042

R9041

R9036

18

9

Q5004OCP

Q5001Q5002Q5003

PWM OUT

DATOFROMMAINuCOMIC701

CLKO

VYOKE

HDTT5001/1

H OUTQ5030

+135V

N

C2190.06825V

R9006

+12V

CN202/CN9001

R9065

Q9001

P

R9012R9008 D9002

+12V

IKFROM

IC9001/5,IC9002/5,IC9003/5

R9068

R5013

C500610

IC5007COMPARATOR

MAIN9V R5108

R5108

Q214PROTMUTEMAINuCOM

IC701/54

N

Q5018H PROT

R250R249

VPROT

MAIN9V

R559910k

R5125

R5104

MAIN12V

R50461.8 OHMS

R50521.5 OHMS

OUT

CN5002

5

CN203/CN5505

A BD. C BD.

D BD.

IK

11bDTV02 1259

-

+

APPENDIX

i

Service GroupService Item

DataServiceVideo 5480i

WLS = 0

F/A Flag:CBA Flag:

1111011111111111

IDID0

0 Service480I

Main uCom numberMain uCom version NVM G G

89WSL=0

A Board NVM

D Board NVM

Service Mode DisplayService Mode Access (same as other Sony TVs):

Point the remote control at the TV and press the following buttons:

Display, 5, Volume +, Power ON.

DisplayThe service mode display has more information.

WSL

At the center of the service screen is a Weak Signal Level (WSL) number.This number is similar to the AGC level in older TV sets. The lower theWSL number the stronger the TV signal. 0 is a strong station and about255 corresponds to snow. When a video input is selected, the WSL num-ber is fixed at 0.

480i/480p/1080i Video Format

When Video 5 or 6 is selected, the input format is shown at the right sideof the display.

The video format is detected by the MID circuit when measuring the hori-zontal frequency of the signal input. The default format is 480i whenthere is no video signal input.

Input signal Horizontal Frequency

Standard NTSC 480i 15,734 Hz

High Resolution 480p 31.5kHz

High Resolution 1080i 33.75kHz

Bottom Flag numbers

These numbers are added in manufacturing to identify where the boardscome from and when they were made. The information is used for qual-ity control purposes.

Memory Check

In the service mode you can check the condition of two of three NVM ICs(memories). Press the #2 button repeatedly until the Service Group = ID.At the lower right, G = Good. NG = No good.

Geometry AdjustmentsThe geometry adjustments have three memory locations for each item inthe service menu.

• 480i standard NTSC• 480p 16:9 aspect ratio• 1080i 16:9 aspect ratioAfter performing the adjustment in the 480i standard mode, change theuser setup menu to 16:9 Enhanced Mode. Selecting ON reduces thevertical for the 1080i mode. Perform the adjustment again. The middle480p 16x9 mode requires a generator to access.

ii

DIGITAL SATELLITE SYSTEM CONVERTER BOX 10/3/00

Tuner

12.2 - 12.7GHz

MicroSMART

card(plug in)

950-1450Hz

TransportDemultiplexer

VideoDecoderMPEG 2

Audio DecoderDolby AC-3

NTSC Encoder

S Video

CompositeVideo

Ch 3/4 RFOutput

IEEE 1394(i-LINK)

Analog Audio

Optical Out(Digital)

RJ11 phonejack

Low speed data(9 pin D-sub)

Interface

Modulator

audio video

video

audio

access card

41DTV02

DSS Dish

iii

DTV SET TOP BOX 9/13/00

Tuner

Cable signalfeed

Antenna

VSB Demodulator

Transport PacketDemultiplexer

Micro

VIDEO Decompression

MPEG 2

AUDIO Decompression

Dolby AC-3

Analog L&R

Digital OpticalPort

Composite Video

Componet Video (Y,Pb, Pr)

S Video

or

Format Decoder/ Down

Conversion

iv

PC CAMCORDERDIGITAL

VCRPRINTER

TYPICAL IEEE1394 HOOK-UP

PEER TO PEER CONNECTION

CAMCORDERCAMCORDER

IEEE-1394

OverviewIEEE-1394 is high-speed digital interface that can be used by many typesof products, including computers and consumer electronics. It uses trans-action-based packet technology to communicate between devices. Thisstandard was developed to help bridge the gap between PCs and con-sumer electronic products.

AdvantagesThe IEEE-1394 has been chosen as the standard interface for digital con-sumer products because of its many advantages. Listed below are sev-eral of these advantages:

It is a hot pluggable and unpluggable system. Devices may be addedor removed at any time and their presence or absence will be recog-nized by the system.It is a non-proprietary standard adapted by the Institute for Electricaland Electronic Engineers. There are no licensing problems at thistime to stop companies from adapting this format.It allows for flexible hookups and easy connection. One thin cablebetween devices does it all. The system allows for daisy chaining upto 63 devices together at one time and also supports branching. It isPlug and Play and does not require ID jumpers or switches. There isno need for terminators.

Peer to peer communications are possible. Any device should com-municate with any other device without the need for a hub or a PC tobe connected.

The system uses scalable architecture that will allow older, slowerdevices to communicate with newer, faster devices at the slower rate.Different combinations of faster and slower devices can be used onthe same bus.

HardwareThere is hardware currently available to support speeds of 100, 200 and400 Mb/s (Megabits per second). These speeds are fine for digital videosince it has a data rate of 30 Mb/s. Data rates of 800 and 1600 Mb/s arealready scheduled for release. A data rate of 3200 Mb/s is in the planningstage.

IEEE-1394 consists of three layers of hardware called the physical, linkand transaction layers. These components may be found in a single IC orin several ICs. These layers will perform the same function regardless ofhow many ICs there are. A description of each layer is listed below:

Physical Layer – Provides the electrical and mechanical interfacebetween a device and a connector. This layer also provides initializa-tion and arbitration between devices. There is a built-in arbitrationsubroutine that will make one of the devices the bus master. Thisdevice will assign IDs to the nodes (devices connected) and controltraffic.Link Layer – The link layer handles all data packet transmissions andreceptions. The data can be either asynchronous or isochronous.

v

MODEDATABUS

TRANSACTIONLAYER

LINKLAYER

PHYSICALLAYER

VIDEOANDAUDIODATA

EXAMPLE: IEEE1394 INTERFACE IN CAMCORDER��

CAMCORDER100 Mb/s

PC400 Mb/s

BANDWIDTH LIMITED BY SLOWER DEVICE

SCANNER200 Mb/s

BANDWIDTH NOT LIMITED BY SLOWER DEVICE

SCANNER200 Mb/s

��

CAMCORDER100 Mb/s

PC400 Mb/s

Transaction Layer – Manages asynchronous data protocols. Thislayer is also responsible for communicating between a device that isusing IEEE 1394, such as a digital camcorder or a capture card, andthe link layer. This would be the system control IC in a camcorder andthe PCI bus in a PC.

Protocol

Data TransferThere are two types of data transfer possible using IEEE-1394. They areas follows:

Asynchronous – This is a memory mapped system. Each packet ofdata is sent to a specific address to be stored and buffered by therecipient. An acknowledge signal is sent when the data is properlyreceived.Isochronous - Isochronous data needs to be sent and received at asteady rate that is in close timing with the ability of the receiving de-vice to process the data. For example, if a digital camcorder pro-cesses data at approximately 30 Mb/s, then the receiving device mustbe able to use this data at the same rate. Data is essentially broadcastat a predetermined rate and not checked for accuracy.

Dynamic Node AddressingEach device, called a node, is assigned a specific address. This occurswhen a bus reset occurs or a new device is added to the system. Threesteps occur when these events occur:

IDs Cleared - All previous ID information is erased.Tree ID - The device, which is the bus master, assigns each node aspecific address. This is called the Tree ID Process.Self-ID - After IDs have been assigned, the system allows time foreach device to identify itself to the other nodes in the network.

Multi-Speed TransactionsThe IEEE-1394 allows for data transmission speed to vary over the net-work. If necessary, a faster device will change its speed to communicatewith a slower one. The paths taken between devices also limit data rates.In Example A below, the PC or scanner would have no trouble communi-cating with the camcorder at a rate of 100 Mb/s. However, the scannercould not communicate with the PC at its top data rate of 200 Mb/s be-cause the path between the two contains a 100 Mb/s device (thecamcorder). The maximum data rate that can be achieved through an-other device is limited to the speed of that device. In example B, the PCand the scanner would be able to communicate at the scanner’s top rateof 200 Mb/s. It is very important that when an IEEE-1394 network is setup that care is taken to properly place devices that need to communicatewith each other at top speeds.

vi

CABLES

CONNECTORS

Cable Technology

WireA standard six-wire cable is used by the PC industry as an IEEE-1394connection. There is also a four-wire connection used by Sony and othermanufacturers on digital camcorders and similar devices. The six-wirecable contains B+, Gnd, and one differential pair for transmitting data andone differential pair for receiving data. The four-wire cable only containsthe two differential pairs for data. There are adapters available if onedevice uses a four-wire cable and other uses a six-wire cable.

ConnectorThe connectors are simple, sturdy and reliable. They are designed withthe contacts inside the connector to reduce corrosion and the risk of shock.They are childproof, if there is such a thing, and are based on the NintendoNES™ connector.

Trade NamesThere are a few trade names associated with the IEEE-1394 standard.The most notable are Fire Wire, which is an Apple trademark andi.LINK, which is a Sony trademark.

Current ProductsA brief list of products that use IEEE-1394 are:

♦ DV Camcorders♦ D8mm Camcorders♦ High-Resolution Digital Cameras♦ HDTV♦ HDTV Set-Top (Converter) Boxes♦ DSS (Digital Satellite System) Boxes♦ Hard Disks♦ DVD-ROM Drives♦ Printers♦ Scanners

Future DevelopmentsIEEE1394 seems poised to take its place as the home networking stan-dard of the future. Its high speed and ease of use are part of the keys thatmay one day make it the bond between all the components in your home.

Sony, along with other industry leaders, is working on a standard calledHAVi. HAVi, which stands for Home Audio Video Interoperability, wouldbe an “open architecture” system. This means that software, applicationprogramming interfaces and communication protocols will allow all digitalelectronic components to work together regardless of manufacturer. Thismight mean that you could control your DTV set top box, digital audiosystem and the temperature of your refrigerator all from one central loca-tion. The amount of products that may use this system is limitless. Weare heading for a digital future and it seems that IEEE1394 will be a largepart of it.

Fire Wire is a trademark of Apple Computer Inc.

i.LINK is a trademark of Sony.

vii

DDDD[ ][ ][ ][ ]

AAAA[ ][ ][ ][ ]

HAHAHAHA[[[[ ]]]]HBHBHBHB[[[[ ]]]]

CN6506

CN6504

CN6505

CN6503

CN706

CN703

CN702

CN6006

CN7003

CN6501

CN5005to [VM]CN701

CN4301CN4503

CN5003to [C] (G-2)

CN5501

CN606

CN6502

DY CONNCN5002CN5505

CN5503

CN5510to CY

BUS CONN

CN3204

[[[[ ]]]]BBBB

UUUU[ ][ ][ ][ ]

CN203

CN201

CN6005

CN607

CN605DGC

[[[[SSSS

[[[[ ]]]]WWWW

]]]]

CCCC[ ][ ][ ][ ]

CN603AC CORD

TOSPEAKERS

TOSPEAKERS

CN9001

CN9002ANTANTANTANTSWSWSWSW

[[[[

CN202

CN204

FOCUS LEAD

HV LEAD

CN707

12mmPurseLock(38mmheight)

)CN7004

MAINMAINMAINMAIN

SUBSUBSUBSUB

TO DY

CN9102CN9103(N/S)

CN9101

DX-1ACHASSIS

ASSEMBLY

CL701

HV REG.BLOCK

(Optional)

BCBCBCBC]]]] 9

Put one loopin HV Leadand securewith purse lock

viii

Board Replacement

Board Removal Functions Possible FailureSymptoms

After board replacement

D

Slide chassis assembly back away from thepix tube.

Remove 7 screws securing the board.

Slide the board toward the pix tube and tiltup to access the flyback.

Unsolder the flyback.

Primary Power Supply(+200V, +135V)

Protection latch circuit

HV Regulator circuit

Corner focus circuit

Top/bottom pincushioncircuit

H Output / V Output

Shutdown

Sides bowing in♦ Transplant memory IC5501 containing

deflection parameters.

♦ Adj Focus (on FBT).

♦ Enter the service mode and perform touchup geometry adjustments to D-Conv/CXA8070 (group #6) andCXA2026AS data (group #7)*.

♦ Adjust HV RV8002 for 31.5kV.

Adj HV shutdown RV8001 (coarse) andRV8003 (fine) according to safety relatedadj in the service manual.

A

Remove 4 screws from the rear panel andfold it down.

Pry the locks from connectors CN3202/3while wiggling the B board away form the Aboard.

Remove 6 screws securing the A board.

Lift the right side of the A board out.

Standby Power Supply

Degaussing circuit

Secondary Power Supply(9V, 5V, 3.3V)

H & V Oscillators/Jungle

Both Tuners

Main uCom IC701

Audio processing

OSD (Menu)

Dead set (checkfront panel masterswitch).

♦ Transplant memory IC707 containingsystem and user data.

♦ Enter the service mode and verify the TVID (group #19), then perform touch upgeometry adjustments to CXA2150D-1data (group #4-1)*.

U


Pry the locks from its connector and wiggle it

Rear panel input connectors Loss of video / audio1-6 inputs. Tuner isunaffected.

None

ix

B


Pry the locks from connectors CN3202/3while wiggling the B board away form the Aboard.

Video processing and audioswitching.

Closed caption/V Chip

DRC for line doubling

MID for twin pictures

Loss of video, Y or C.

Loss of sync to mainor sub pix.

Transplant memory IC3089 containing Twinpicture parameters.

C

Wiggle the C board off the CRT neck.

Unsolder the CRT socket and install on thenew board.

RGB CRT signal amplifiers Dark screen (adjustG2 first)

Stby light blinks 5times & repeats.

Adj Screen control according to the servicemanual: Reduce vertical size to see IK line atthe top. Blank pix in the service mode bychanging CXA2150P-2/ALBLK data from 0 to1. Adjust screen control so the IK line is justinvisible in a dark room.

W

Remove the C board.

Mark the pix tube neck to reinstall the new Wboard assembly.

Loosen the clamp and remove the assembly.

Velocity Modulation circuitto improve detail

Top/bottom Pincushion &corner focus coils

White outline alongobject.

* Refer to the service manual s section 5 for the list of adjustments.

W boardclamp

G1Pixtube

DynamicConvergence Secondary

Power Supply

HV Regulator

FBT

HorizontalDeflection

Vertical

PrimaryPower Supply

S Bd(audio)

B board(video)

StbyCircuit

HA/HB boards - Front panel remote & buttons

x

Front of TV

D Board A Board

HA board HB board

U board

B board

BC board

Pry out

CN3202

CN3203Pry out

BCboard

U board

xi

Model: KV-32XBR400, KV-36XBR400No. 492

Subject: Service Manual Correction: Safety RelatedAdjustments

Date: July 27, 2000

Symptom:(****) There is an error on page 23 of the preliminary service manual in the HV

Service Flowchart.

Solution: Change the incorrect text as follows:

Incorrect:"Confirm +B, Vd, and check hold-down on D-board with black video with thefollowing steps:1. Confirm +B across C6544 to make sure it is 135.3 – 1 Vdc.2. Confirm Vd at pin 2 CN6506 or at TP-Vd for 4.9 V < Vd < 5.1 Vdc.3. Apply 5.5 + 0.5 VDC at pin 2 of CN6544, then confirm set holds down."

Correct:"Confirm +B, Vd, and check hold-down on D-board with black video with thefollowing steps:1. Confirm +B across C6544 to make sure it is 135.3 – 1 Vdc.2. Confirm Vd at pin 2 CN5506 or at TP-Vd for 4.30 V = Vd = 4.65 V.3. Apply 5.5 + 0.3 VDC at pin 2 of CN5506, then confirm set holds down."

csv-1Sony Service CompanyNational Technical ServicesA Division of Sony Electronics Inc.Park Ridge, New Jersey 07656

CONFIDENTIALService BulletinTV Products

S

SSEL Service Company

A Division of Sony Electronics Inc.1 Sony Drive

Park Ridge, New Jersey 07656

DTV021000 Printed in U.S.A.

S and i.LINK are trademarks of Sony ElectronicsDolby Digital is a trademark of Dolby

Fire Wire is a trademark of Apple Computer Inc.TiVo is a registered trademark of TiVo Inc.

sony dx 1a troubleshooting manual

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