soft usb design challenges lane hauck · the objective: soft usb function traffic enhanced 8051...
TRANSCRIPT
![Page 1: Soft USB Design Challenges Lane Hauck · The Objective: SOFT USB Function Traffic Enhanced 8051 Core 3.3V, 24 MHz, 4-clock cycle Program and Data RAM I/O](https://reader034.vdocuments.us/reader034/viewer/2022051910/5fff5f16a957362f6544a6c3/html5/thumbnails/1.jpg)
Soft USB Design Challenges
Lane Hauck
Systems EngineeringManager
Anchor Chips Inc.
laneh@ anchorchips.com
www.anchorchips.com
![Page 2: Soft USB Design Challenges Lane Hauck · The Objective: SOFT USB Function Traffic Enhanced 8051 Core 3.3V, 24 MHz, 4-clock cycle Program and Data RAM I/O](https://reader034.vdocuments.us/reader034/viewer/2022051910/5fff5f16a957362f6544a6c3/html5/thumbnails/2.jpg)
Soft USB Design Challenges
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The Objective: SOFT
USBFunctionTraffic
Enhanced8051Core
3.3V, 24 MHz,4-clock cycle
ProgramandDataRAM
I/O
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The Basic USB Interface
SerialInterfaceEngine(SIE)
D+
D-
Bytes
USBTranceiver
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What the SIE Does
SerialInterfaceEngine(SIE)
D+
D-
USBTranceiver
SYNC
OUT
ADDR
ENDP
CRC5
Token Packet
SYNC
DATA1
PayloadData
CRC16
Data Packet
SYNC
ACK
SYNC
OUT
ADDR
ENDP
CRC5
Token Packet
SYNC
DATA0
PayloadData
CRC16
Data Packet
SYNC
ACK
H/S Pkt
PayloadData
PayloadData
ACK
![Page 6: Soft USB Design Challenges Lane Hauck · The Objective: SOFT USB Function Traffic Enhanced 8051 Core 3.3V, 24 MHz, 4-clock cycle Program and Data RAM I/O](https://reader034.vdocuments.us/reader034/viewer/2022051910/5fff5f16a957362f6544a6c3/html5/thumbnails/6.jpg)
A USB Control Transfer
SYNC
IN
ADDR
ENDP
CRC5
Token Packet
SYNC
DATA0
8bytesSetupData
CRC16
Data Packet
SYNC
H/S Pkt
SYNC
SETUP
ADDR
ENDP
CRC5
Token Packet
SYNC
DATA1
PayloadData
CRC16
Data Packet
SYNC
SYNC
IN
ADDR
ENDP
CRC5
Token Packet
SYNC
DATA0
PayloadData
CRC16
Data Packet
SYNC
H/S Pkt
SETUP Stage
DATA Stage
STATUS Stage
SYNC
DATA1
Data Packet
SYNC
H/S Pkt
SYNC
OUT
ADDR
ENDP
CRC5
Token Packet
CRC16
H/S Pkt
SerialInterfaceEngine(SIE)
8bytesSetupData
PayloadData
PayloadData
intelligence
ACK
ACK
ACK
ACK
ACK
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EZ-USB Enhanced SIE
SerialInterfaceEngine(SIE)
intelligence
Anchor ChipsEnhanced SIE
FullDevice
Enumeration
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Default Endpoints
Endpoint TypeAlternate Setting
0 1 2Max Packet Size (bytes)
0 CTL 64 64 641 IN INT 0 16 642 IN BULK 0 64 642 OUT BULK 0 64 644 IN BULK 0 64 644 OUT BULK 0 64 646 IN BULK 0 64 646 OUT BULK 0 64 648 IN ISO 0 16 2568 OUT ISO 0 16 2569 IN ISO 0 16 169 OUT ISO 0 16 1610 IN ISO 0 16 1610 OUT ISO 0 16 16
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Advanced SIE Enumerates &Loads Code
SerialInterfaceEngine(SIE)
intelligence
Anchor Chips
Enhanced SIEFull
DeviceEnumeration
Enhanced8051Core
3.3V, 24 MHz,4-clock cycle
ProgramandDataRAM
Download & Upload
Code
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The Download Request
Byte Field Value Meaning0 bmRequest 0x40 Vendor Request, OUT1 bRequest 0xA0 “Anchor Load”2 wValueL AddrL Starting address3 wValueH AddrH4 wIndexL 0x005 wIndexH 0x006 wLengthL LenL Number of Bytes7 wLengthH LenH
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Final USB Device
intelligence
intelligence
Anchor ChipsEnhanced SIE
USBFunctionTraffic
Enhanced8051Core
3.3V, 24 MHz,4-clock cycle
ProgramandDataRAM
SerialInterfaceEngine(SIE)
intelligence
Anchor ChipsEnhanced SIE
I/O
![Page 12: Soft USB Design Challenges Lane Hauck · The Objective: SOFT USB Function Traffic Enhanced 8051 Core 3.3V, 24 MHz, 4-clock cycle Program and Data RAM I/O](https://reader034.vdocuments.us/reader034/viewer/2022051910/5fff5f16a957362f6544a6c3/html5/thumbnails/12.jpg)
AN2131Q Memory Map
Endpoint 0 IN
Endpoint 0 OUTEndpoint 1 IN
Endpoint 1 OUTEndpoint 2 IN
Endpoint 2 OUTEndpoint 3 IN
Endpoint 3 OUT
Endpoint 4 INEndpoint 4 OUT
Endpoint 5 INEndpoint 5 OUT
Endpoint 6 INEndpoint 6 OUTEndpoint 7 IN
Endpoint 7 OUT
EZ-USB regs
6.5K RAM
1024bytesBulk
EndpointBuffers
0000
1B40
1F3F
2000 1024 BytesIsochronous
FIFOS
1024 BytesIsochronous
FIFOS
SOF
USB
Endpoint 0 controlEndpoints 1-7 bulk/interruptEndpoints 8-15 isochronous
All 31 USB endpoints areavailable
USB
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Enumeration
Host PCrecognizes deviceattachment, starts
Enumerationprocess
Host PC loadsloader driver,which loads
firmware anddescriptors intodevice from asoftware file
EZ-USB Coreprovides devicedescriptors to
identify the loaderdriver.
Host PC
Your Peripheral Device
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The ReNumerationTM Process
The MagicHappens
Host PCrecognizes deviceattachment, starts
Enumerationprocess
Final USB device.EZ-USB CPU
services USB andprovides device
functionality
Host PC loadsloader driver,which loads
firmware anddescriptors intodevice from asoftware file
Host PCEnumeratesagain, loadsdevice driver
EZ-USB Coreprovides devicedescriptors to
identify the loaderdriver.
Host PC
Your Peripheral Device
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Emulating a PhysicalDisconnect
DISCON#
EZ-USB
D-D+
5V
GND
To 3.3V Regulator
1234
1500
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Using the Enhanced SIE
intelligence
intelligence
Anchor ChipsEnhanced SIE
USBFunctionTraffic
Enhanced8051Core
3.3V, 24 MHz,4-clock cycle
ProgramandDataRAM
SerialInterfaceEngine(SIE)
intelligence
Anchor ChipsEnhanced SIE
I/O
![Page 17: Soft USB Design Challenges Lane Hauck · The Objective: SOFT USB Function Traffic Enhanced 8051 Core 3.3V, 24 MHz, 4-clock cycle Program and Data RAM I/O](https://reader034.vdocuments.us/reader034/viewer/2022051910/5fff5f16a957362f6544a6c3/html5/thumbnails/17.jpg)
Get Descriptor--W ithout EnhancedSIE
CPU copies FIFO data to RAM, decodes"Get Descriptor" Request
USB Setup data copied to FIFO
SYNC
IN
ADDR
ENDP
CRC5
Token Packet
SYNC
DATA0
8 bytesSetupData
CRC16
Data Packet
SYNC
ACK
H/S Pkt
SYNC
SETUP
ADDR
ENDP
CRC5
Token Packet
SYNC
DATA1
PayloadData
CRC16
Data Packet
SYNC
DATA1
Data Packet
SYNC
ACK
SYNC
IN
ADDR
ENDP
CRC5
Token Packet
SYNC
DATA0
PayloadData
CRC16
Data Packet
SYNC
ACK
H/S Pkt
SYNC
ACK
H/S Pkt
SYNC
OUT
ADDR
ENDP
CRC5
Token Packet
CRC16
SETUP Stage
DATA Stage
STATUS Stage
EndpointFIFO
DescriptorData TableEndpoint
FIFO
1 2
4 53
6
1
2
3
4
5
6
CPU transfers first packet of data frommemory to endpoint FIFO.
FIFO Data sent in response to USB INtoken
CPU Transfers next packet of data frommemory to endpoint FIFO.
FIFO Data sent in response to USB INtoken
7 Repeat steps 5-6 as necessary.
8-byteSETUP data
buffer
H/S Pkt
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Get Descriptor--W ith EnhancedSIE
SYNC
IN
ADDR
ENDP
CRC5
Token Packet
SYNC
DATA0
8 bytesSetupData
CRC16
Data Packet
SYNC
ACK
H/S Pkt
SYNC
SETUP
ADDR
ENDP
CRC5
Token Packet
SYNC
DATA1
PayloadData
CRC16
Data Packet
SYNC
DATA1
Data Packet
SYNC
ACK
SYNC
IN
ADDR
ENDP
CRC5
Token Packet
SYNC
DATA0
PayloadData
CRC16
Data Packet
SYNC
ACK
H/S Pkt
SYNC
ACK
H/S Pkt
SYNC
OUT
ADDR
ENDP
CRC5
Token Packet
CRC16
SETUP Stage
DATA Stage
STATUS Stage
8-byteSETUP data
buffer
1
8051 sets pointer to descriptor table in RAM,EZ-USB core does entire multi-packet transfer.
EZ-USB core copies Setup data directly to RAM,eliminating the FIFO-to-RAM copy step. 8051decodes the "Get Descriptor" request.
1
2
DescriptorData Table
2
H/S Pkt
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Watch Those VID-PID-DIDs
EZ-USB
USBPC
Loads AnchorChips Driver
EZ-USB
Device ID (DID)
Product ID (PID)
Vendor ID (VID)
Serial EEPROM
USBPC
Loads Device-SpecificDriver
Device ID (DID)
Product ID (PID)
VID = 0547
(a) "Anchor Generic" Enumeration
(b) Custom Device Enumeration
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IO Bandwidth Is Important
Accumulator
DPTR ISO OUT FIFO
FWR#
mo
vx a
,@d
ptr
D[7..0]
External FIFOor ASIC
Accumulator
DPTR ISO IN FIFO
D[7..0]
mo
vx @
dp
tr,a
FRD#External FIFO
or ASIC
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AN2131 Transfers to ExternalFIFO
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Expanding the AN2131Q
AN2131Q
PORTA (8)
PORTC (8)
PORTB (8)
Data (8)
RD#WR#
I2C
regOUT Pin
PIN
OE
Alternate Function
Address (16)
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Lane Hauck
Systems EngineeringManager
Anchor Chips Inc.
laneh@ anchorchips.com
www.anchorchips.com