smdp c2sd vlsi lab – nit durgapur umc65 using cadence...

SMDP C2SD VLSI LAB – NIT DURGAPUR

Physical Verification and Parasitic Extraction inUMC65 using Cadence Virtuoso

Follow these steps after completion of layout drawing on cadence virtuoso.

DRC

Open the layout and its schematic. In this example,Library name: DemoCell name: cmos_inverter

on top menu, select Calibre > Run nmDRCbelow shown window opens

Prepared by: Rishi Todani

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On the left side we have a couple of tabs like Rules, Inputs, output etc, We shall call this left panel. Select Rules from left panel. Under DRC rules file, click …. button and browse and select the following file.

/mnt/pdk/_G-01-LOGIC_MIXED_MODE65N-LL_LOW_K/Designkits/Cadence_IC6/G-9FD-LOGIC_MIXED_MODE65N-LL_LOW_K_UMK65FDKLLC00000OA-FDK-Ver.B11_PB/UMK65FDKLLC00000OA_B11_DESIGNKIT/UMK65FDKLLC00000OA_B11/RuleDecks/Calibre/DRC/G-DF-LOGIC_MIXED_MODE65N-1P8M1T0F1U-LL-Calibre-drc-1.18_P1

after selecting this file, click “load” button. This verifies that the file is properly read.

Then click Edit button below the load button.

Under “Recipe Edits” select “Checks selected in the rules file” under include section“Checks with density” under Exclude section as shown above.Click OK

From DRC main window now select “inputs” from left panel. Choose below optionsRUN: DRC (hierarchical) under Layout tab: Format: GDSIIcheck “Export from layout viewer”

If topcell name and library name are not appropriately filled, click on the button to the right of


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Export from layout viewer and select your design. In this example, Topcell: cmos_inverterLibrary name: demoView name: layoutNo changes required in “waivers” tab

no further changes required in other tabs.

Click Run DRC

If errors exist. Will be reported by RVE window. Clear the errors and re run DRC until all errors areremoved and RVE reports no error.

Close all DRC windows when done and return to layout

LVS

Click on top panel “Calibre > Run nmLVS”

Choose Rules from left panel and under rules file, click browse and choose below file:/mnt/pdk/_G-01-LOGIC_MIXED_MODE65N-LL_LOW_K/Designkits/Cadence_IC6/G-9FD-LOGIC_MIXED_MODE65N-LL_LOW_K_UMK65FDKLLC00000OA-FDK-Ver.B11_PB/UMK65FDKLLC00000OA_B11_DESIGNKIT/UMK65FDKLLC00000OA_B11/RuleDecks/Calibre/LVS/G-DF-LOGIC_MIXED_MODE65N-LL_LOW_K_CALIBRE-LVS-1.6-P4.txt

click “load” button to verify that file is properly read.


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Choose Inputs from left panelsetup following selections as shown in image below in Layout tab


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in layout tab, under format, choose GDSII and check Export from layout viewer. Make sure top cell,library and view name are correctly set. U may type or click on button adjacent to export from layout viewer option and select your layout.Now click on Netlist tab and setup as shown below

Format: SPICEcheck Export from schematic viewerclick on adjacent button and select your schematic view. Make sure topcell, library and viewname properly filled. Here view name should be schematic.

In nmLVS window, at the top select SETUP > LVS OPTIONS

a new button on left panel below outputs will appear if it was disabled from below. Click on LVS options on left panel

Under supply lab, type the power nets you have used in layout with proper case as in schematic and layout.Power nets: vddGround nets: gnd

No other changed required in LVS options.

Click Run LVS on nmLVS window.


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The RVE window will show if any LVS error. Clear all errors. When all errors are removed, re run LVS and RVE should appear as shown below

Close all LVS windows

PEX

PEX does parasitic extraction

In virtuoso layout window, click Calibre >Run PEX

under rules file choose

/mnt/pdk/_G-01-LOGIC_MIXED_MODE65N-LL_LOW_K/Rulefiles/XRC/G-DF-LOGIC_MIXED_MODE65N-1P10M2T2F-LL_LOW_K_TOP_METAL8K_XRC-LPE-Ver.1.1_P1/G-DF-LOGIC_MIXED_MODE65N-1P10M2T2F-LL_LOW_K_TOP_METAL8K_XRC-LPE-1.1-P1/Typ/G-DF-LOGIC_MIXED_MODE65N-1P10M2T2F-LL_LOW_K_TOP_METAL8K_XRC-LPE-1.1-P1-Typ.tec

Click load button to verify everything is read properly inside the rule file.


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Click Setup on top and make sure PEX options is enabled.

Choose inputs from left panel. Under layout tab, Format should be GDSII and export from layout viewer checked. Click adjacent button and select your layout view. Top cell, library and viewname properly filled. Viewname is layout here.

Choose netlist tab from top,Format: SPICEcheck export from schematic viewerclick adjacent button and choose your schematic viewtopcell, library name and view name properly filled. Here viewname should be schematic


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Click output from left panel

Extraction Mode: xRCExtraction type: Transistor level , R + C , No inductance

under Netlist Tab,

Format: Calibreview Use names from: Schemaic


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No other changes in outputs required

Now click PEX options on left panel

Under Netlist tab, Select Format tab. Enable “Ground node name” and type the ground net name.

Ground net name: gnd


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Choose LVS options Tab from top and enter the names of power and ground net as shown


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Power net: vddGround nets: gndNow go to “Include” tab from topenable “Include Rule Statements”type below two lines in the box provided below this

SOURCE CASE YESLAYOUT CASE YES

Click on Run PEX

RVE window will now show the parasitic values and should like like this


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Calibre view setup window will appear

under cell map file, click browse and choose the below file

/mnt/pdk/_G-01-LOGIC_MIXED_MODE65N-LL_LOW_K/Designkits/Cadence_IC6/G-9FD-LOGIC_MIXED_MODE65N-LL_LOW_K_UMK65FDKLLC00000OA-FDK-Ver.B11_PB/UMK65FDKLLC00000OA_B11_DESIGNKIT/UMK65FDKLLC00000OA_B11/RuleDecks/Calibre/calview.cellmap

Under calibre view type: select schematicunder create terminals: select create all terminals

reset properties: m=1magnify instance by 1device placement: layout locationopen calibre view: read-mode


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click OK

calibre view will open.

Verify it has all the pins that you have in the symbol with names in the same case.

A new view called calibre will be created along wth layout, schematic and symbol in the cmos_inverter cellname.

Close all PEX windows


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Now we can carry out post layout simulation


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smdp c2sd vlsi lab – nit durgapur umc65 using cadence...

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