Smart Dust: Unique Low Power Flexible Sensor Network

Neil Goldsman, Haralabos (Babis) Papadopoulos and Shuvra Bhattacharyya

Dept. of Electrical and Computer Engineering

University of Maryland

College Park

Lead Personnel All UMD ECE Faculty

•Prof. Neil Goldsman –Director of ECE Mixed Signal VLSI Lab–Director of ECE Semiconductor Simulation Lab–Introduced RF VLSI Circuit Design to UMD–Other Areas: 3D Integration

•Prof. Haralabos (Babis) Papadopoulos –Institute for Systems Research–Communications and Signal Processing Laboratory–Center for Satellite Communications–Other Areas: Power Efficient Private Comm. Networks

•Prof. Shuvra Bhattacharyya –Institute for Advanced Computer Studies–Digital VLSI Design Automation Laboratory –Embedded Systems Research Laboratory,–Communications and Signal Processing Laboratory–Other Areas: Embedded Software; Low Power Design

Outline

• Smart Dust Overview• Electronics (Neil)

– RF VLSI, Hardware, Sensors and 3D Integration

• Communications (Babis)– Algorithms and Signal Processing

• Microcontrol (Shuvra)– Digital Hardware and Software for Data Flow and

Processing

Overview: Smart Dust Network

•A network of smart sensors (dust particles) that communicate with each other wirelessly and perform distributed computations.

•Dust particle to be mm size (grain of sand).

•Network to be seamlessly integrated into environment for flexible application.

•Each dust particle usually contains a sensor, a micro-controller, a transceiver, and powering mechanisms

•The network can contain several hundreds or even thousands of dust particles.

Overview: What is a Smart Dust Network?

• The dust particles sense physical attributes of the environment, and then wirelessly communicate these attributes to other dust particles.

• Using a distributed computing algorithms, the dust particles fuse their data, and make decisions based on the cumulative information of the overall network.

• Applications: – Motion and Distance tracking– Biological and Chemical Environmental Factors– Distributed Image Recognition and Optical Sensing– Acoustic and Vibrational Sensing

Overview: The Challenges

• Dust particles are small size but must still house RF and computational circuitry.

• Low Power: Dust particles are either to be powered externally or by a power source that is commensurately sized with respect to the dust particle. We must perform RF communication, computations and sensing which minimize power use, but still overcome noise limitations and bit errors.

• How to physically produce dust particles that allow for sensing, communication and computation on a system that is millimeter scale?

• What special computational codes and hardware do we need, and what special communication algorithms do we need?

Overview: Overcoming the Challenges

To develop a state-of-the-art smart dust system we have divided the project into three major tasks.

1. Design of Physical Smart Dust Particles (Neil).

2. Development of Network Communication Protocols and Fusion of Data (Babis).

3. Computation for Data Analysis and Network control (Shuvra).

Design of Analog Smart Dust Particle Components

Neil Goldsman

Dust Particle Basic Topology

Achieve with State of Art CMOS, Novel Materials (CNTs) & Unique 3D Integration

L1

L2μPSensor ADC

Tx

Rx

•Sensor: Optical, Biological, Temperature, etc. (analog)

•μP: microprocessor (control and signal processing)

•Tx, Rx: Transceiver

BPF LNA IMF IFF 1,0

PA

MOD & Carrier

f1-f2=

f2-f3=

f3-f1=

….

DEMOD

N,N+1

N,N+1,N+2,…

Sample CLK

Series to Parallel CPU

Rx

Tx

PLL

Use Phase-Locked Loop-Based Transceiver

Background: FSK PLL VLSI Chip Already Developed

A/DConverter

ShiftRegister

PLL

Dual Modulus Prescaler

AnalogInput

Reference Frequency

Output

Clock DataSampling

Rate

DigitalInput

Background PLL FSK Chip PrototypeFabricated in 0.5μ CMOS

12-B

it C

oun

ter Ou

tpu

tD

rive

r

Ou

tpu

tD

rive

r

OutputDriver

PF

DVCO VCO VCO

Digital Switching Noise Testing Circuit 1

PLL Output MeasurementsLow Phase Noise, Nice Lock

50MHz 100MHz 500MHzFrequency:

-2.2dBc/Hz-1.6dBc/Hz -1.8dBc/HzPhaseNoise:

-1.4dBc/Hz20.8dBc/Hz 16.5dBc/Hz

Analog Structures for Meeting Low Power, Small Size Dust Design Constraints

• Operating frequency high GHz for small dimensions• On-Chip antenna tuned to high GHz• Transceivers rely heavily on tuned circuits

– Need State of Art Inductors for Max Q and Min Area.– 3D inductor and Antenna design– Carbon Nanotube Kinetic Inductor (2nd generation)

• Sensors– On chip temperature sensor array– Optical diode array (visible and infrared) – MEMS accelerometer, microphone (2nd generation)

• On-chip microwave power harvester– Antenna and Schottky diode form power supply

Assemble into Single Dust Particle with Novel 3D Integration Methods

Achieving Smart Dust with 3D Integration

• To integrate sensors, RF, and processors into a millimeter size system, 3D integration is a likely approach.

• We can build on our existing research in this area with LPS (G. Metze).

• Integration achieved through modular levels.

Three-Dimensional Integrated Dust Particle

3D Inductor and Transformer Test Structures

Transformer

PlanerSpiral

Inductor

3DSpiral

EMCbetween

Spiral andTransistor EMC between

n wells

EMC betweenTransistors

Prototype fabricated in 0.5μ CMOS with MOSIS.

Simulations indicate 3D structures have much larger L and Q

Currently being verified experimentally a with network analyzer.

Prototyping Temperature Sensor Array (10x10)

Diodes are used as temperature sensors:

Diode current increases exponentially with temperature.

Fabricated in 0.5μ CMOS

3-D Prototyping Stacking Chip3-D Prototyping Stacking Chip

•New chip with structures that can connect in 3D.

•Uses Symmetric Vias for 3D Interconnects”

•Prototype fabricated in 0.5μ CMOS with MOSIS.

Proof of Principle Prototype

• Develop Temperature Sensor Smart Dust Network

• Use aforementioned RF and Temperature Systems

• Employ State of the Art Dust with 3D Integration• Power

– First with batteries– Second by harvesting the environment (RF, Heat)

• Communication and Microcontrolling schemes to be used are described next.