smart cuttm nano technology

European Innovation Day Tokyo, October 15, 2018

Smart CutTM Nano Technology

Dr. Carlos Mazuré CTO, Soitec

Chairman, SOI Industry Consortium

2

A Introduction

B RF

C MEMS

Agenda Agenda

European Innovation Day Tokyo, 15 October 2017

D Takeaways

Substrate Engineering: Built-in Functionality

European Innovation Day Tokyo, 15 October 2017 3

SiO2

ONO

…..

Silicon

Strained Silicon

Germanium

III-V

…..

Buried insulator

Device layer

Handle Substrate

CZ Silicon

High Resistivity Si

Sapphire

Glass

Smart CutTM Technology


5

3 core technologies available and material expertise

to manufacture engineered substrates

Engineered

Substrates Configured through layer

transfer techniques

Smart Cut Smart

Stacking

Epitaxy Material

Expertise


Smart Cut Flexibility


Piezzo On

Insulator

Silicon On Sapphire

InGaN On Sapphire

Ma

teri

al O

pti

on

s

Thickness Capabilities Silicon On Insulator

InP On GaAs

…

A/MS/mmWave

Soitec in the Value Chain


Smart Cut TM

technology

SOI processed

wafer with multiple raw dice

per wafer

SOI substrates

(Silicon on Insulator)

Silicon die with millions of

transistors

SOI transistor

S

Base material

Buried Oxide

D G Si

IC

PCB

Starting

wafers

Engineered substrates

Our engineered substrates are at the heart of everyday life

8

Higher reliability

Longer battery life Outstanding Performance

$$$$

Optimized cost

Data Centers IoT

Automotive Smartphones

Soitec’s engineered substrates


Soitec – A Leading Engineered Substrates Supplier

addressing Large Consumer related Markets


Photonics Power RF Front-end

Module

Processor &

connectivity SoC

FD-SOI RF-SOI Power-SOI Photonics-SOI

Imagers

Imager-SOI

In Production

10

A Introduction

B RF

C MEMS

Agenda Agenda


D Takeaways

Enhanced Signal Integrity SOI - RFeSI™

Trap Rich layer freezes the highly conductive layer at BOX – Handle interface

11

Fixed

charges

Mobile &

Interface trapped

charges

Mono-crystal Top Silicon

Buried Oxide Trap Rich Layer

High Resistive Base


12

RFeSI

>25 dBm

Insertion Loss Linearity High Q passives Crosstalk Source: UCL

HR-SOI RFeSI SOI

RFeSI™ addresses all FEM challenges


Buried Oxide Trap Rich Layer

High Resistive Base


Buried InsulatingLayer SiO2 (BOX)

High Resistivity SiBase


Soitec RF-SOI wafers : HRSOI & RFeSI™

13

HRSOI

RFeSI relies on a unique Trap Rich

layer that will limit high frequency

signal propagation in the substrate

boosting device RF performance Value proposition

Manufacturing in 200mm and 300mm

$$$

Bernin 1 Bernin 2 Simgui Singapore

High Resistive Base

PERFORMANCE

› Higher Linearity

› Lower RF losses

› Lower crosstalk

› High quality passives

COST

› Lower than GaAs and MEMS

› Integration with switch, amplifiers and passives

› Available in 200/300mm

AREA

› Lower die size

RFeSI

Enhanced Signal Integrity

Mono-crystal Top Material

Trap rich layer

High resistivity Silicon

Buried Oxide


Buried Insulating

Layer SiO2 (BOX)

High Resistivity SI

Base


4G and 5G sub <6GHz Front End Module


RF-SOI

RF-SOI

RF-SOI

RF-SOI

RF-SOI

Switch

Antenna

tuner

Diplexer

PA

LNA

Piezo On Insulator

3G LTE ✓

Filters

RF-SOI Innovation: From R&D to Tech Dev to Mfg

15

2005 2009 2011 2012 2015

RF-SOI 300mm

ramp

Soitec RFeSi substrate ramp

RF-SOI switch

mainstream 1st RF-SOI

switch

TR-SOI UCL & Soitec IP

RF

-SO

I

>50%

2017

Contribution of many organizations and companies


Strong SOI ecosystem driving innovation for 4G/5G


mmW

Switch Antenna

Tuner

LNA

PA Digital

DAC

ADC

PLL Mixers

+

RF-SOI

0.25um

RF-SOI

0.18um

RF-SOI

0.13um

RF-SOI

90nm

RF-SOI

65nm

RF-SOI

45nm

Addressing current needs

and new challenges

< 6Ghz

…

> 10 foundries

in HVM mode FD-SOI

22/28nm

SOI mixed signal platforms for 4G & 5G


Mixed signal design & integration options

Lower Power

No junction capacitance

Back Bias Ultra low

VDD

Higher Frequency

Short Channels

Low Device Parasitics

Forward Body Bias

Signal Integrity

Low transmission

loss High isolation

Low harmonics

RF-SOI / RFeSI ● 3/4G Front End Module

○ Antenna Switch

○ Antenna Tuner

○ Low Noise Amplifier

○ Power Amplifier

FD-SOI ● Wide range of digital app.

● Ultra Low Power IoT

● Transceivers

● Low Power analog

● 5G Front End Module

● 5G transceivers

● Radar mmWave (77Ghz)

PD-SOI / HR ● 5G Front End Module

RF-SOI Innovation: From R&D to Tech Dev to Mfg

18 European Innovation Day Tokyo, 15 October 2017

SOI Industry Consortium 1.0:

Accelerator of ecosystem development

Ecosystem focused workshops around the world

Oct 2009, @ IMEC, Leuven, Belgium

Sept 2010, @ Univ of Tokyo, Japan

Dec 2010, San Francisco, US

April 2011, Hsinchu, Taiwan

Feb 2012, San Francisco, US

Dec 2012, San Francisco, US

Topics: technology, modeling and fabless requirements

Contributors: academia, R&D (Institutes, Industry), EDA, Fabless


SOI Industry Consortium 2.0:

Ecosystem growth and promote adoption

Industry events for the industry by the industry around the world

Sept 2014, Shanghai

Jan 2015, Tokyo; Feb 2015, Si Valley; April 2015, Hsinchu, Taiwan; Sept 2015, Shanghai

Jan 2016, Tokyo; April 2016, Si Valley; Sept 2016, Shanghai

April 2017, Si Valley; Jun 2017, Tokyo; Sept 2017, Shanghai

Mar 2018 Brussels; April 2017, Si Valley; Jun 2018, Tokyo; Sept 2018, Shanghai

Topics: foundry platform, design ecosystem and first products

Contributors: Institutes, Industry, Fabless, Market Analysts, Investment Funds


Ecosystem Partnership: 5G connectivity

21

Main challenges and DRIVERS

-Increased linearity and higher number of communication bands

and bandwidth

-Robust and highly integrated RF FEM with no performance

degradation at high temp

Driving demand:

-Reliable cyber-physical communication systems (V2X) for

Smart Autonomous Vehicles (Automotive, Aeronautics)

-Low-latency, available, low-power Infrastructure

(communication modules & equipments)

-New business models with mobile connectivity for utility

providers (Energy, Smart Metering)


Ecosystem Partnership: Value Chain


23

A Introduction

B RF

C MEMS

Agenda Agenda


D Takeaways

SOI for Sensors – MEMS - NEMS


Source: Presented at Tokyo SOI Workshop, June 2016

SOI for Sensors & Actuators: Layer transfer on cavities


‘‘Thick’’

5-10µm

‘‘Thin’’

~ 1µm

‘‘Ultra-Thin’’

~0.15µm

25-100-500 µm

cMUTs & pMUTs (Micromachined Ultrasonic Transducers)

Capacitive MUTs

cMUTs

Suspended Membranes


MUT: Resonance Frequency control (very simplified model*)

t

w

Fres a t / w² (*) Not including :

- stress effects,

- damping, loading,

- DC polarization

- electrode stack

- etc …

cMUT (LETI)


Si membranes on cavities :

- 20x20 µm² and 40x40 µm² cavity arrays

- ~1 µm Si membrane

Collaboration

Very dense arrays

become possible !

~ 20 x 20 µm² cavities

7µm spacing

40 x 40µm²

Wafer diameter : 200mm


Sacrificial SiO2 to adjust Si thickness

(thermal oxide) 0.8µm mono Si

membrane

SiO2

SiO2/Si3N4 stack

Gap (vacuum bonding)

Collaboration

29

0.8µm thin membranes on 40 x 40µm² arrays


…on 1.5µm thick membranes …

2.6 µm Si epi …

… on cavity

~ 4 µm epi thickened membranes on 20 x 20µm² arrays

Collaboration

MembraneThickness flexibility Tuning downwards by etching, sacrificial oxidation,...

Tuning upwards by epitaxy (before or after transfer on cavity)

Front-end CMOS

compatible

engineered substrate


cMUT electrical characterization

Collaboration

~ 5 MHz

Arrays of

40µm x 40µm²

cavities


More than Moore: Ecosystem growth 2018 Japan SOI Workshop Tokyo, 2018.10.26

Takeda Hall, Tokyo University


Session: Keynotes Chair: Carlos Mazure, SOI Industry Consortium

9:40 - 10:10 Distributed AI and computing at edge and nodes for sensors, Giorgio Cesana, Sr. Director,

STMicroelectronics

10:10 – 10:40 RF- & FD-SOI: addressing substrate supply to support accelerated growth, Jean-Marc LeMeil,

Director, Soitec

10:40 – 11:10 FD-SOI for ultra low power edge computing, Jon Cheek, Director, NXP

11:10 - 11:40 Break

Session: MEMS & Sensors Chair: Jon Cheek, NXP

11:40 - 12:05 A Time-of-Flight Range Image Sensor with High Near Infrared Quantum Efficiency Using SOI-

Based Fully-Depleted-Substrate Detectors; Prof. Shiji Kawahito, Shizuoka University

12:05 – 12:25 An Overview of SOI based MEMS; Jean-Philippe Polizzi, MEMS Business Development

Manager, Leti-CEA

12:25 – 12:50 Smart Cut technology applied to MEMS: illustration in the field of ultrasonic transducers; Bruno

Ghyselen, Sr. Expert, Soitec

12:50 - 13:50 Lunch

Takeaway: Substrate-Device-Application Co-Optimization

Semicon Europa Munich, November 2017 33

Innovation platforms

Systems

ICs

Materials Virtual wafers 8" or 12" for small diameter

materials: InP, GaN, GaAs, LiTa03, LiNbO3,…

Flexible IC

New gen.

SOI-MEMS

Sensing, 5G, Cloud

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