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Department of Electronics and Communication Engineering, VBIT SM Charts P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) VIDYA SAGAR P 1 https : //potharajuvidyasagar . wordpress . com

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  • Department of Electronics and Communication Engineering, VBIT

    SM Charts

    P.VIDYA SAGAR ( ASSOCIATE PROFESSOR)

    VIDYA SAGAR P1

    https://potharajuvidyasagar.wordpress.com

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    ➢ SM Charts: State machine charts, Derivation of SM Charts, Realization of SM Chart,

    Implementation of Binary Multiplier, dice game controller.

    VIDYA SAGAR P2

    CONTENT

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    Algorithmic State Machine (ASM)

    ➢ A sequential circuit is also known as an Algorithmic State Machine (ASM) or simply a State

    Machine. These names are often used when the sequential circuit is used to control a digital

    system that carries out a step-by-step procedure or algorithm.

    ➢ Principal Component Of An ASM Chart

    1.State Box : Contains output list.

    2. Decision Box : Condition is placed.

    3. Conditional Output Box : Contains conditional output list.

    4. ASM Block : contains one or more exit paths. Describes machine operation

    VIDYA SAGAR P3

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    Specific Rules for constructing SM Chart:

    ➢ Certain rules must be followed while constructing an SM block.

    ➢ For every valid combination of input variables ,there must be exactly one exit path defined

    .This is necessary because ,each allowable input combination must lead to a single next state.

    ➢ The second rule is no internal feedback within an SM block is allowed. This is shown in the

    diagram below.

    VIDYA SAGAR P4

    Wrong feedback Correct feedback

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    EXAMPLE

    VIDYA SAGAR P5

    ASM charts are not unique, it may have more than one equivalent form Fig. shown three equivalent ASM charts

    for combinational network Z=A(B+C).

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    EXAMPLE

    ➢ Contains only one state box

    ➢ For Z=A+BC

    ➢ Put (A+BC) in one decision box & Z

    ➢ in one Conditional output box

    VIDYA SAGAR P6

    ➢ Put each term in condition box

    ➢ If A=1,Z=1

    ➢ If A=0 (B=0,Z=0 or B=1,C=0/1,z=0/1)

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    ASM chart in equivalent form

    VIDYA SAGAR P7

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    Conversion Of State Diagram To An ASM Chart

    ➢ Mealy Machine : In case of Mealy machine ,output is a function of both present state and input .

    For construction of ASM chart from Mealy state diagram ,we should follow the following steps.

    1.Represent each states by state boxes.

    2.Put input in decision box after each state box.

    3.The Mealy output appear in conditional output boxes since they depend on both the state and

    input.

    4.Mealy circuit output written only when it is equal to '1' i.e. true .

    5. Depending on value of input connect the path to next state box.

    ➢ Moore Machine : In case of Moore machine ,output is a function of the present state only . For

    construction of ASM chart from Moore state diagram ,we should follow the following steps

    1.Represent each states by state boxes.

    2.The Moore output are placed in the state boxes since they do not depend on the input .

    3.After each state box put the input in decision box.

    4.Depending on value of input connect the path to next state box.

    VIDYA SAGAR P8

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    Example1➢ Convert the state diagram of Fig. below to ASM chart.

    VIDYA SAGAR P9

    Fig.State diagram

    Fig.ASM chart

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    Example 2 ➢ Convert the state diagram of Fig. below to ASM chart.

    VIDYA SAGAR P10

    Fig.State Diagram

    Fig.ASM chart

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    Example2

    ➢ Dram an ASM chart to describe a mealy state machine that detects a sequence of 101 and that

    asserts a logical 1 at the output during the last state of the sequence .

    VIDYA SAGAR P11

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    VIDYA SAGAR P12

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    Derivation of SM Charts

    The method used to derive an SM chart for a sequential control circuit is similar to that used to

    derive the state graph. First, we should draw a block diagram of the system we are controlling.

    Next, we should define the required input and output signals to the control circuit. Then we can

    construct an SM chart that tests the input signals and generates the proper sequence of output

    signals.

    ➢ Binary Multiplier

    The first example is an SM chart for control of the binary multiplier shown in Figures A and B).

    The add-shift control generates the required sequence of add and shift signals. The counter

    counts the number of shifts and outputs K 1 just before the last shift occurs. The SM chart for

    the multiplier control (Figure) corresponds closely to the state graph of Figure(c). In state S0,

    when the start signal St is 1, the registers are loaded. In S1, the multiplier bit M is tested. If M 1,

    an add signal is generated and the next state is S2. If M 0, a shift signal is generated and K is

    tested. If K 1, this will be the last shift and the next state is S3. In S2, a shift signal is generated,

    since a shift must always follow an add. If K 1, the circuit goes to S3 at the time of the last shift;

    otherwise, the next state is S1. In S3, the done signal is turned on.

    VIDYA SAGAR P13

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    VIDYA SAGAR P14

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    A Dice Game

    As a second example of SM chart construction, we will design an electronic dice game. This game is

    popularly known as craps in the United States. The game involves two dice, each of which can have a

    value between 1 and 6.Two counters are used to simulate the roll of the dice. Each counter counts in

    the sequence 1, 2, 3, 4, 5, 6, 1, 2, . . . .Thus, after the “roll” of the dice, the sum of the values in the

    two counters will be in the range 2 through 12.The rules of the game are as follows:

    1. After the first roll of the dice, the player wins if the sum is 7 or 11. The player loses if the sum is 2,

    3, or 12. Otherwise, the sum the player obtained on the first roll is referred to as a point, and he or

    she must roll the dice again.

    2. On the second or subsequent roll of the dice, the player wins if the sum equals the point, and he

    or she loses if the sum is 7. Otherwise, the player must roll again until he or she finally wins or loses.

    Figure 5-11 shows the block diagram for the dice game. The inputs to the dice game come from two

    push buttons, Rb (roll button) and Reset. Reset is used to initiate a new game.When the roll button is

    pushed, the dice counters count at a high speed, so the values cannot be read on the display. When

    the roll button is released, the values in the two counters are displayed.

    .

    VIDYA SAGAR P15

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    ➢ Figure shows a flow chart for the dice game. After rolling the dice, the sum is tested. If it is 7 or

    11, the player wins; if it is 2, 3, or 12, he or she loses. Otherwise the sum is saved in the point

    register, and the player rolls again. If the new sum equals the point, the player wins; if it is 7,

    he or she loses. Otherwise, the player rolls again. If the Win light or Lose light is not on, the

    player must push the roll button again. After winning or losing, he or she must push Reset to

    begin a new game. We will assume at this point that the push buttons are properly debounced

    and that changes in Rb are properly synchronized with the clock.

    ➢ The components for the dice game shown in the block diagram (Figure) include an adder,

    which adds the two counter outputs, a register to store the point, test logic to determine

    conditions for win or lose, and a control circuit. Input signals to the control circuit are defined

    as follows:

    ➢ D7 = 1 if the sum of the dice is 7

    ➢ D711 = 1 if the sum of the dice is 7 or 11

    ➢ D2312 = 1 if the sum of the dice is 2, 3, or 12

    ➢ Eq = 1 if the sum of the dice equals the number stored in the point register

    VIDYA SAGAR P16

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    ➢ Rb = 1 when the roll button is pressed

    ➢ Reset = 1 when the reset button is pressed

    Outputs from the control circuit are defined as follows:

    ➢ Roll = 1 enables the dice counters

    ➢ Sp = 1 causes the sum to be stored in the point register

    ➢ Win = 1 turns on the win light

    ➢ Lose = 1 turns on the lose light

    VIDYA SAGAR P17

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    VIDYA SAGAR P18

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    VIDYA SAGAR P19

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    VIDYA SAGAR P20

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    VIDYA SAGAR P21

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    Realization of SM Charts

    Methods used to realize SM charts are similar to the methods used to realize state graphs. As with any

    sequential circuit, the realization will consist of a combinational subcircuit, together with flip-flops for

    storing the state of the circuit. In some cases, it may be possible to identify equivalent states in an SM

    chart and eliminate redundant states using the same method as was used for reducing state tables.

    Realization of ASM charts are similar to the realize state diagram .The following procedure can be used

    to derive the next state equation for a flip-flop Q .if gates and flip-flops are used .

    1.The first step is to make a suitable state assignment for each state

    2.Search all the states for which Q is one .

    3.For each of these states, find all of the link paths that lead into the state.

    4.For each of these link paths ,find a term that is 1 with the link path.

    5.The expression for the next state of Q is formed by ORing together all the terms found in step3.

    6.Similarly ,the expression for output can be read directly from the ASM chart.

    7.Find a simplified expression for output and next-state equations with a K-map using the

    unused state assignment as a don’t care condition.

    8.Realize the SM chart using gates and flip-flops.VIDYA SAGAR P22

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    procedure for deriving the next state equation for a flip-flop Q from the

    SM chart is as follows:

    1. Identify all of the states in which Q 1.

    2. For each of these states, find all the link paths that lead into the state.

    3. For each of these link paths, find a term that is 1 when the link path is followed. That is, for a

    link path from Si to Sj, the term will be 1 if the machine is in state Si and the conditions for exiting

    to Sj are satisfied.

    4. The expression for Q (the next state of Q) is formed by OR’ing together the terms found in step 3.

    VIDYA SAGAR P23

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    VIDYA SAGAR P24

    Example

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    Example

    ➢ For the SM chart of Fig. below make the following state assignment for the flip flops P and Q.

    VIDYA SAGAR P25

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    Solution:

    ➢ Z=PQX

    ➢ Q+=P'QX'+ P'QX+ P'Q'X+PQX

    ➢ link1 link2 link3 link4

    ➢ P+= P'QX' link1

    ➢ Next state equation of Q can be simplified with k-map using the unused state assignment as a

    don’t care condition .

    ➢ Q+=P'Q'+ P'X+QX

    VIDYA SAGAR P26

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    Implementation of Dice Game:

    VIDYA SAGAR P27

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    ➢ We can realize the SM chart for the dice game (Figure) using combinational circuitry and three D

    flip-flops, as shown in Figure.We use a straight binary state assignment. The combinational

    circuit has nine inputs and seven outputs. Three of the inputs correspond to current state, and

    three of the outputs provide the next state information. All inputs and outputs are listed at the

    top of Table .

    VIDYA SAGAR P28

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    VIDYA SAGAR P29

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    VIDYA SAGAR P30

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    VIDYA SAGAR P31

    E2 =D’7 Eq’ in the 1010 square. In rows 7 and 8, Win is always 1 when ABC = 010,so 1’s are plotted in the corresponding squares of the Win map.

    The resulting equations are

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