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A NOR Emulation Strategy over NAND Flash MemoryA NOR Emulation Strategy over NAND Flash Memory
Jian-Hong Lin, Yuan-Hao Chang, Jen-Wei Hsieh, and Tei-Wei Kuo
Embedded Systems and Wireless Networking LaboratoryDept. of Computer Science and Information Engineering National Taiwan UniversityTaipei, Taiwan
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Agenda
• Research Motivation
• An Efficient Prediction Mechanism
• Performance Evaluation
• Conclusion
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Comparison between NAND and NOR
NORSLC NAND
(large-block, 2KB-page)
Access Method Random Sequential
Access SpeedRead: 23.84 MB/secWrite: 0.07 MB/sec
Erase: 0.22 MB/sec
Read: 15.33 MB/secWrite: 4.57 MB/sec
Erase: 6.25 MB/sec
Density Low High
Price High (34.55 $/GB) Low (6.79 $/GB)
Application
Code storage
•low-end mobile handsets
•PC BIOS chips
Data storage
•MP3 player (music storage)
•Digital Cameras (image storage)
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Motivation
• Replace NOR with NAND for code storage
• Challenge: – How to fill up the performance gap between NAND and
NOR?- Use SRAM for data caching
- Prediction scheme
- Implementation design
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A Prediction-based Prefetching Strategy• An Example Scenario
Offline: Traces analysis
1.
Online: Prefetch the data based on the prediction information
2.
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The System Architecture
Cache for data access
Communication with the host system
For code and data storage
Address translation from byte addressing to LBA addressing
Prefetch data from NAND to SRAM based on prediction info.
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A Prediction Graph• A prediction graph
– An Illustration of the access patterns(a sequence of LBA’s)
– One node for each LBA in the graph
seq i … 1000, 1001, 1002, 1003, 740, …seq j … 1000, 1001, 345, 346, 347, …
1000 1001 1002 1003 740
345 346 347
Branch node
Regular node
branch node
e.g.
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An Implementation• The Way to Save the Prediction Graph in
the Flash Memory
• The Spare Area Usage of Nodes1. Regular Nodes (Subsequent LBA Information)
spare area !small block: 16 bytes
large block: 64 bytes
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An Implementation (cont.)2. Branch Nodes (Assisted by a Branch Table)
addr(b1)
addr(b2)
addr(b3)
An example
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A Prefetch Procedure
• The Objective: The Probability Maximization of Data Accesses over SRAM
• Cyclic Buffer with Two indices: current and next
• A Greedy Algorithm in the Prefetch Procedure– Regular Node Prefetching of its Subsequent LBA
– Branch Node Prefetching of all Possible Following LBA Links in a Round-Robin Way
• Stop Conditions1. next reaches a branch node again along a link.
2. next and current point to the same page.
3. The caching buffer is full.
…
…
…
meet a branch node again!
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A Prefetch Procedure
1 2 3 4 5 1 6current next
the cache
Prediction graph
An Example
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Snapshots of the Access Patterns
RANDOM ACCESS!
RANDOM ACCESS!
BURST READ!
BURST READ!
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Performance Metrics and Experiment Setup• Performance metrics
– Read performance– Cache miss rate– Main-memory requirement
• Experiment setup– Large-block NAND flash memory:
- Setup time (random access): 25 us/page- Serial access time: 50 ns/byte
– SRAM- 10 ns/byte
– NOR flash memory- 40 ns/byte
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Read Performance
saturate at 4KB
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Conclusion• An Application-Oriented Approach to Replace NOR with
NAND– Prefetching of data from NAND based on the trace analysis– Limited SRAM requirement– Good performance, but the results depending on the predictability of
the applications
• Performance Improvement and Overhead Evaluation– Read performance better than that of NOR:
- AOE II: 24%- TTD: 216%- Raiden: 298%
– Cache miss rate:- Lower than 10% in most cases