sl-note-98-099 md · web viewa novel rf beam control architecture has been successfully tested in...

BE/Note/2011/NNN (sub ref)2023-05-20

[email protected]

4 Channel Digital Down Converter – DDC (EDA-00991)

Alfred BLAS, dept. BE/RF, Angela SALOM SARASQUETA, Joe DELONG (BNL-USA)

Keywords: DDC, digital down converter, low-level rf, beam control, LEIR

Summary

A novel rf beam control architecture has been successfully tested in the LEIR synchrotron. The design is based on a VME 64X carrier board, including a DSP (digital signal processor), into which different daughter cards can be plugged in. The DDC (Digital Down Converter) is one of them. Hardware wise it has the features of a four-channel ADC (analogue-to-digital converter) which outputs drive a powerful FPGA (field programmable logic array); the latter is connected to the DSP on the carrier board via high-speed connectors. Mainly, this unit will acquire rf signals to analyze their phase and amplitude at a specified harmonic of the revolution. The main sampling clock feeding the mezzanine board is at a high harmonic of the particle’s revolution frequency. In the PSB, this frequency is varying along the accelerating cycle and this choice allows analyzing the rf signals from the cavities or from the beam without changing any parameter along the cycle. The sampling clock is tagged at the revolution rate allowing for a synchronous load of new parameters along the accelerating cycle. Synchronous means in phase with the different electronic boards composing the rf beam control. The different signal processing features programmed in the FPGA will be depicted in this note.

Table of contents:

1. Introduction.................................................................................................................................................42. Digital down converter global circuitry......................................................................................................53. Hardware structure......................................................................................................................................6

3.1. Clock circuit........................................................................................................................................83.2. Input anti-alias filter..........................................................................................................................10

4. Local oscillator..........................................................................................................................................114.1. Phase and amplitude resolution........................................................................................................124.2. LO frequency word resolution..........................................................................................................124.3. Error on the LO frequency................................................................................................................134.4. Master DDS frequency resolution:...................................................................................................154.5. Phase to amplitude conversion..........................................................................................................15

4.5.1. Taking advantage of sine wave symmetries.............................................................................154.5.2. ½ LSB phase shift.....................................................................................................................174.5.3. Compression technique for phase to amplitude conversion.....................................................17

5. CIC filter...................................................................................................................................................185.1. Intuitive description of the CIC........................................................................................................195.2. Choosing the value of M (differentiator pipeline delay)..................................................................215.3. Choosing the value of R (decimation or down-sampling value)......................................................225.4. Choosing the value of N (number of stages)....................................................................................235.5. Group delay.......................................................................................................................................235.6. CIC gain............................................................................................................................................235.7. CIC word truncation.........................................................................................................................24

6. FIR filter....................................................................................................................................................257. DDC internal signals monitoring..............................................................................................................26

7.1. Acquisition sequence........................................................................................................................267.2. Acquisition start time and sampling rate..........................................................................................277.3. SRAM timing diagrams....................................................................................................................27

8. LO frequency measurement......................................................................................................................289. I/Q vector frequency discriminator...........................................................................................................2810. Clock harmonic change.........................................................................................................................3011. DSP interfacing registers......................................................................................................................32

11.1. Communication protocol:.............................................................................................................3211.1.1. VME leading the bus................................................................................................................32

11.2. Address decoding..........................................................................................................................3311.3. RF synchronous registers..............................................................................................................3811.4. Double-tag synchronous registers.................................................................................................4011.5. Double tag synchronous pulses.....................................................................................................41

12. Acknowledgments.................................................................................................................................4213. References.............................................................................................................................................4214. Annex....................................................................................................................................................43

14.1. Connections to the DSP board......................................................................................................4314.2. List of the different motherboard blocks sharing the signal existing on the DDC card...............4514.3. FPGA interconnections.................................................................................................................4614.4. Memory map.................................................................................................................................47

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1. Introduction

A novel rf beam control architecture has been successfully tested in the LEIR machine. Its core, designed in the Brookhaven National Laboratory (J. Delong), makes use of a VME 64X board, including a DSP, into which different daughter cards can be plugged in. The DDC (digital down converter) is one of them. This card initially designed in BNL has been upgraded to fulfill new requirements. Apart from the re-engineered firmware of the onboard programmable logic circuit, the SRAM capacity has been increased from 512 kB to 2 MB, a higher capacity pin-compatible Stratix FPGA has been installed and a new clock input circuit implemented. The initial up-to-80 MHz clock signal (non-tagged) used in BNL was upgraded to an up-to-160 MHz tagged clock, chosen to be a harmonic of the revolution. The tagging scheme requires a de-tagging and a divide-by-two circuit to restore a 50 % duty cycle necessary for the ADCs. The 1.2 ns long tag, synchronous with the revolution frequency signal of the synchrotron, provides an absolute phase reference for the measured rf signals and a double tag, also synchronous with the revolution and triggered when required, enables a synchronous loading of chosen parameters or a synchronous storage of selected signals in the SRAM. The bandwidth required for this 416 MHz ( = 1/2.4ns) equivalent clock signal implied changing the hardware (IEEE 1394 connectors) and the electrical standard (LVDS).The sampling clock harmonic is changed within the accelerating cycle, by factors of 2. This is done as often as required to maintain the clock frequency within the optimal range of [40 MHz , 80 MHz]. This change is synchronously compensated within the DDC circuitry to avoid transients.The DDC will typically input the beam, cavity or ejection reference rf signals and transpose them to base band (DC) such as to extract I/Q quadrature projections of the resulting output vector. The shift to baseband is obtained by mixing the input signal with a local oscillator. The upper frequency-mixing product is eliminated by a CIC and/or a FIR low-pass filter.All parameters of the DDC are controlled by the DSP on the motherboard. 28 FPGA internal signals can be acquired by it on demand (up to 4 at a time), after having been stored in the on-board SRAM. The start time, the sampling rate as sub-multiple of the sampling clock and the length of the traces (up to 1M samples of 16 bits) can be defined.When the DSP requests a “I” value, the DDC outputs the sample following the demand. At the same time it freezes the value of Q so that it corresponds to the same time sample during the following read action (read Q). The same approach applies for the values A2 ∙ ∆ ω and A2 from which the DSP calculates the frequency offset with respect to the local oscillator. A is the amplitude of the I/Q vector.

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2. Digital down converter global circuitry

The digital down converter inputs rf signals (beam signal, cavity return, synchronization reference…) and transposes them to DC base band. The obtained modulation around zero Hertz is provided as two signals in quadrature phase: I (in phase with the local oscillator) and Q (in quadrature). Its basic functionality is depicted in figure 2.1.

Figure 2.1: DDC global functionality (one of the 4 channels)

The rf analogue signals feeding the DDC are first filtered to remove the spectral components above the Nyquist limit and then digitized at a selected harmonic of the rf frequency, then sent to two digital mixers (multipliers). A local oscillator supplying two signals in quadrature (sine and cosine) at a frequency (harmonic) selected for the analysis, feeds the multipliers on their other input. The output will provide the sum and difference frequencies. In order to keep only the low frequency modulation, the output of the multiplier is sent to a digital low pass filter (CIC and optionally FIR). The remaining modulation around DC represents the actual modulation of the rf input signal around the local oscillator reference. Having two multipliers fed with signals in quadrature allows obtaining the vectorial information characterizing the modulation through its projection on two perpendicular axes (real and imaginary parts). These standard I and Q components can be treated independently in a damping loop process or used to compute phase and amplitude values.

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3. Hardware structureThe DDC typically inputs the rf signals from the cavity or from the beam. Hardware wise it has the functionality of a 4 channel ADC (analogue to digital converter) with a resolution of 14 bits and a maximum sampling rate of 120 MHz. The ADCs outputs feed a powerful FPGA (Stratix field programmable logic array from Altera) being connected to the DSP on the carrier board via high speed connectors called “site connectors”. Figure 3.1 shows the time structure of the tagged clock feeding the DDC and typically used to sample the rf inputs. This clock is at a high harmonic of the particle’s revolution frequency but stays always below 160 MHz, the specified upper limit. The tag is a short pulse of 1.8 ns that can be compared to the high state duration of the remaining 50% duty cycle clock signal that is always longer than 3.1 ns. The tag is a revolution phase reference used to synchronize rf sources, but in order to do specific synchronous actions at a specific tag point, a double tag is created. The double-tag takes the form of a succession of two tags separated by a normal clock pulse.

Figure 3.1: Main sampling clock feeding the SDDS

Figure 3.2: DDC hardware structure

The clock interface in figure 3.2 and represented as a divide-by-2 and de-tagging circuit allows recovering the 50 % duty cycle required for the ADCs – this is the role of the divide by 2 circuit. The ADC sampling frequency is thus the half of this of the incoming clock. See the annex for the details of the interconnections.

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Main components on the DDC board:

14 bit ADC AD 9245BCP-80 (80 MHz max and 50% duty cycle clock) In the actual hardware, the ADC is a 14 bit model from Analog Devices (AD 9245BCP-80)500 MHz differential input bandwidth, 1 → 80 MSPSSFDL: 76 dBc, SNR > 70 dB in the Nyquist range. DNL < +/- 1 LSB, ENOB > 11 bits.Input voltage is in the +/-1 to +/- 2 Vp-p range.The ADC operates with a single 3 V supply / 366 mW.

The ADC has to supply a 2’s complement digital value. Therefore the mode pin (pin22) needs to be connected to AVDD (+3.3 V) which corresponds to the 2’s complement mode without Duty cycle stabilizer (not compatible with a swept clock frequency). The 120 Ω resistor connected between pin 22 and GND should thus be suppressed.With the actual choice of connections on the ADC, The ADC differential input voltage span is 2 Vpp. As it is preceded by a differential Amplifier AD8138 with a gain: [2Vpp - common mode input] -> [2Vpp diff mode output] (gain 1), the DDC input voltage span is 2Vpp or +/- 1 V as it is DC coupled.

SFDL: Spurious-Free Dynamic Range In ADCs, Spurious-Free Dynamic Range (SFDR) is defined as the ratio of the RMS amplitude of the carrier frequency (maximum signal component) to the RMS value of the next largest noise or harmonic distortion component.DNL: Differential Nonlinearity: In an ideal D/A converter, incrementing the digital code by 1 changes the output voltage by an amount that does not vary across the device's permitted range. Similarly, in an A/D, the digital value ramps smoothly as the input is linearly swept across its entire range. DNL measures the deviation from the ideal. An ideal converter has the code exactly the same size, and a DNL of 0 (zero).

Altera Stratix EP1S20F484C5, 18460 logic elements, 1.6 MB RAM Cypress CY7C1061BV33 Static RAM (1M x 16 bit), 10ns access time 1 Tagged clock input with IEEE1394 mechanical standard and de-tagging and divide-by-2 circuit

(50% duty cycle required by the ADC).

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Figure 3.3: DDC printed circuit board

3.1. Clock circuit

As mentioned in the previous chapter, the incoming tagged (pulse width modulated) clock (from a circuit called MDDS or Master DDS) is first divided by two to provide a 50 % duty cycle clock to the ADCs.

The upper clock frequency limit is specified as 80 MHz (the ADC maximum sampling rate). It turns out to be also the maximum reliable frequency for the tagging and de-tagging circuits.

The clock source has the capability to change its harmonic at any time, synchronously with the double tag, during the cycle. The idea being that when the clock frequency increases up to the 80 MHz limit, its harmonic is divided by two in order to set the frequency down to 40 MHz. If synchronously, the rf sources within the SDDS compensate for this change, the output signal frequency remains identical. This is what happens.

In summary, whatever the revolution frequency range, the sampling clock frequency will remain within the 40MHz – 80 MHz range.

Figure 3.1.1 describes the details on how the clock signal is processed on the SDDS board, together with some typical propagation delays.

The input clock, issued from the MDDS, arrives as a differential LVDS signal in a IEEE 1394, 9-pin connector where two pairs of signals are available. This standard is compliant with 1.6 Gs/s per pair on a 5m distance, and is thus fully compatible with our constraints. In our present setup, only one differential signal is being used: the tagged clock. This mechanical standard allows for a future topology where clock and tag are taking two different paths.When using the tagged clock only, the signal travels via two passes; one is a “de-tagging” circuit that discriminates the tag by recognizing a pulse shorter than 2.5 ns (the tag is about 1.8 ns wide when the minimal “normal” clock pulse width is 3.12 ns at 160 MHz) and the second is a divide-by-two circuit which outputs a 50% duty cycle signal requested by the ADCs (the tagged or double tagged <160MHz clock is pulse width modulated). This latter signal will become the main sampling clock signal and should remain below 80 MHz (ADC limit). The de-tagging circuit outputs a so-called “wide-tag” pulse. Its duration is one period of the 50% duty cycle clock and its rising edge is synchronous with the trailing edge of the latter.

The FPGA main sampling clock can be selected from 4 different sources: The 40 MHz reference clock coming from the Mother board, the MDDS clock, the MDDS clock divided by 2 (50% DC) or a signal issued from the FPGA. The FPGA provides the selection bits to the clock multiplexer.

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Figure 3.1.1: Details of the SDDS clock processing circuitry

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3.2. Input anti-alias filter

An input filter is inserted to attenuate the aliases above the Nyquist limit at f S/2. These should be attenuated by more than 84 dB to take full advantage of the ADC dynamic range (14 bits). The other specifications of the filter will mainly depend on the context where it is to be used in. In a feedback loop, the phase linearity might be less important than a small group delay.

In the industry (source Mini-Circuits), a typical filter attenuation slope in the 10 MHz range is 52 dB/Octave. This means that the value -84 dB is reached after 3*FC (specified cutoff).

FNOISE

FC=84 dB

52 dBOct

=1 , 61 Oct⇔FNOISE

FC=21. 61=3 .05⇔FNOISE=3 .05∗FC

In a very general context, the spectrum of the DDC input is expected to stay bellow FS/2 and the DAC low-pass filter should be designed as in figure 3.2.1 to avoid aliasing. The effect of the zero-order-hold at the ADC (sinc envelop) input is neglected as it only counts for a supplementary attenuation of – 4dB at FS/2.

Figure 3.2.1: Input filter response to be used in a DDC

From figure 3.2.1 it can be concluded that the low-pass filter should have its cutoff frequency at FS-MIN/6 which means 6.6 MHz when FS-MIN = 40 MHz (minimum sampling frequency).

Note that any signal from FC up to 3*FC = FS/2 will suffer attenuation (weakened signal to noise ratio) and likely group delay variation.Typically, in an rf context, the DDC will be required to input rf signal modulated with close sidebands. In the case of a narrow-band cavity return signal, the harmonics will be naturally filtered out, relaxing the filter requirements. In the case of a beam return, this will not be the case and the harmonics might go high in frequency.

In the case of a narrow band input rf signal at FMAX (the highest expected rf frequency) the lowest frequency alias will occur at FS –FMAX.In such a context where the DDC input signal has a frequency content below FMAX < FS/2, the DAC output filter can be specified as to have an attenuation of 84 dB at (FS – FMAX) > FS/2.

By using a low-pass filter (-52 dB/ oct) with a cut-off frequency FC = FMAX, one gets:

3 * FC < FS - FMAX

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FMAX = FC < FS/4

In LEIR, the clock harmonic will change values by factors of 2, in order to stay within a window [40 MHz , 80 MHz]. With a commercial low-pass filter, the maximum allowed spectrum bandwidth output (full scale) is thus FS MIN/4 = 10 MHz.

Figure 3.2.2: Input filter response to be used in a DDC providing a signal spectrum limited to FMAX

4. Local oscillator

The local oscillator sets the reference frequency around which the rf modulations are to be analyzed. The oscillator, using the standard core of a direct digital synthesizer (DDS), is depicted in figure 4.1.

Figure 4.1: DDC local oscillator

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4.1. Phase and amplitude resolution

To preserve the ADC 14 bit resolution at the mixer’s output, the LO output signal should be at least coded on 14 bits.To obtain an effective 14 bit dynamic range on the amplitude side, a 16 bit resolution (2 more bits) on the phase side is desirable as:

There is an equivalent of 1 bit distortion due to the phase-to-amplitude conversion compression technique (cf. §4.5).

1 bit overhead is needed in case the GCD (Greater Common Denominator) of hLO and 2N >1 (hLO is the digital word presented to the phase accumulator and N the number of bits of the phase accumulator), because in this circumstance the spurs level can be increased by up to 3.9 dB [1]

4.2. LO frequency word resolution

The spectrum quality having been considered, the frequency resolution still needs to be set.

It might be useful at this stage to consider the DDC local oscillator in its context. (Figure 4.2.1)

Figure 4.2.1: DDC local oscillator in its context

As shown in figure 4.2.1, the master DDS provides the clock to the DDC LO, which turns out also being a DDS; with the resulting frequency being:

FLO = (hLO / 2N)(hCLK* FREV).

N: number of bits of the DDC LO phase accumulator.FLO: Output Frequency of the local oscillator

So as to track any harmonic hMEAS of the beam revolution, the digital input word hLO needs to be set to:

hLO = 2N * hMEAS / hCLK

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When the aim is to observe a beam signal in the LEIR synchrotron, a 10 Hz resolution on FLO is sufficient as it is capable to discriminate different synchrotron (fS > 1500 Hz) or betatron harmonics (fB >260 Khz). The number of bits should be such that:

N ≥ log2 (FCLK MAX / FRESOLUTION ) = log2 (80 MHz/ 10 Hz) = 23 bits

Care should be taken that hLO = 2N * hMEAS / hCLK is an integer so that the DDC LO supplies the exact expected

rf frequency (only integers can be represented at the DDS input) to avoid a frequency shift (up to hCLK* FREV / 2N ≡ 1 LSB) and thus also a phase drift. To cancel this unwanted effect, an optional “LO reset at each tag (meaning at each revolution)” feature has been added. When this bit is activated, the LO phase is forced to zero at each revolution tag. In case hLO is an integer, this means no effect as the phase is by construction equal to zero at each tag in that context.

Conclusion: the DDC LO phase accumulator depth should be superior or equal to 23 bit.

4.3. Error on the LO frequency

Due to the finite resolution of the frequency word, sometimes the required LO frequency cannot be exactly represented. This leads to a frequency and phase error. If the frequency error is often negligible, its integral – the phase error – is increasing as the cycle gets longer. What can this error be?

The DDC receives a tagged clock signal from the Master DDS (MDDS), which frequency is:

FMDDS = hMDDS FREV (1)

The maximum MDDS output frequency is 160 MHz.

The MDDS tagged clock frequency is first divided by two in the DDC to provide a 50% duty cycle clock (max. 80 MHz) required mainly by the onboard ADCs.

N being the DDC-LO (local oscillator) phase accumulator depth (in number of bits) and NDDC-LO the frequency word presented to the DDC-LO phase accumulator input, the DDC-LO output frequency can be written as:

FDDC −LO=N DDC−LO

2N +1 ⋅FMDDS (2)

When FDDC-LO is required to be an harmonic of the revolution:

N DDC−LO=2N +1⋅hDDC−LO

hMDDS (3)

As N needs to be an integer (binary word), when the right end side of equation (3) is not an integer, the DDC frequency word cannot be represented exactly.

What can the frequency error on the DDC LO be?Let us first check the error on hDDC-LO

hDDC− LO=N DDC−LO⋅hMDDS

2N+1 (4)

The error on hDDC is thus:

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dhDDC−LO

dN DDC−LO=

hMDDS

2N +1 (5)

The maximum error on NDDC-LO is (dNDDC-LO )max = +/- ½ LSB = 2-1 :

(dhDDC −LO )max=hMDDS

2N+2 (6)

Using (3) and (5), the actual error can be written:

dhDDC−LO=min[2N +1⋅hDDC−LO

hMDDS−Int (2N +1⋅

hDDC−LO

hMDDS ); Int (2N+1⋅hDDC−LO

hMDDS )−2N +1⋅hDDC−LO

hMDDS ]⋅hMDDS

2N +1

Using (6) and knowing that hDDC-LO = FDDC-LO/FREV , the maximum LO frequency error can be written:

(dFDDC−LO )max=hMDDS⋅FREV

2N +2 (7)

and the phase error is (T is duration along which the phase error is integrated):

(dΦDDC−LO)max=360⋅hMDDS⋅F REV⋅T

2N +2 [degrees of DDC_LO signal]

The real error in degrees of the DDC-LO signal is:

dΦ DDC−LO=min [2N+1⋅hDDC−LO

hMDDS−E(2N +1⋅

hDDC−LO

hMDDS ); E(2N +1⋅hDDC−LO

hMDDS )−2N+1⋅hDDC−LO

hMDDS ]⋅360⋅hMDDS⋅FREV⋅t

2N +1

Example:

With hDDC-LO =1 and 2, hMDDS = 112, N =32 and FREV = 1 MHz, the integrated phase error of the LO signal with respect to the expected harmonic of the revolution is:

dΦ DDC−LO = 2.01 degrees per second of operation on h= 1dΦ DDC−LO = 0.67 degree per second of operation on h= 2

Note that the phase error is not proportional to the frequency required on the LO output. It is just a function of how the DDC-LO frequency word is far from the required value in some specific cases.

When the Local Oscillator is required to supply an exact harmonic of the revolution, this phase shift effect can be cancelled by applying a reset at each revolution tag of the Master DDS clock signal.

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4.4. Master DDS frequency resolution:

For the DDC local oscillator to work as expected, the supplied reference clock frequency (from the Master DDS) should be at least as precise as what is required for the LO (see 4.2). There are nevertheless other constraints.As an example, in the PSB the digital loop error word is added to the Revolution frequency word with its MSB having a value of 20 kHz (= 180o phase error or the maximal radial position). With 14 bits resolution, this means that the LSB is worth 2.4 Hz.Without making any deep analysis of the rf loop dynamics, it can be estimated that LEIR requirements will be of the same order of magnitude (same synchrotron frequencies, same loop delays).

To fulfill the PSB requirements with the 14 bits loop dynamic range, the master DDS should have a number of bits in the frequency word greater than:

log2 (1 GHz/ 2.4 Hz) = 29 bits.

1 GHz is the master DDS sampling clock

To make sure that this constraint for the master DDS is sufficient, it must also be checked that this resolution is higher than the resolution of the revolution frequency calculated from the B-field in one of the DSP boards. The resolution of the B-field measurement is 0.1 Gauss.

From the frequency law related to a centered beam, we get:

When dR = 0 → dfREV = (1/γ2) (fREV / B) dB

At injection, with γ = 1.0045, frev = 361 kHz and B = 2827 G: dfREV = 12.6 HzAt extraction, with γ = 1.0775, frev = 1423 kHz and B =11511 G: dfREV = 10.6 Hz

This constraint is less demanding than the previous and does not need to be considered.

4.5. Phase to amplitude conversion

4.5.1. Taking advantage of sine wave symmetries.

For the phase angle φ to be converted to both sin(φ) and cos(φ), a simple lookup table necessitates 1.875 Mb of memory for a 16 bit phase word and 15 bits of amplitude resolution. To lower the requirements, some compression techniques can be applied. The most obvious is to exploit the symmetry of the sine function about π:

sin(φ + π) = - sin(φ)

and about π/2:

sin(φ + π/2) = sin(π/2 – φ)

These two identities allow treating the phase modulo π/2 instead of 2π.As both sine and cosine functions are required, a third identity can also be used:

sin(φ + π/4) = cos(π/4 - φ)

And: cos(φ + π/4) = sin(π/4 - φ)

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Phase value 3 MSb’s of phase wordcoded in binary

Sine and cosine values (φ is modulo π/4)the minus sign means 1’s complement (-001 = 110)

[0 ; π/4[ 000 sin(φ) = sin(φ) cos(φ) = cos(φ)[π/4 ; π/2[ 001 sin(φ) = cos(-φ) cos(φ) = - sin(-φ)[π/2 ; 3π/4[ 010 sin(φ) = cos(φ) cos(φ) = - sin(φ)[3π/4 ; π[ 011 sin(φ) = - sin(-φ) cos(φ) = - cos(-φ)[π ; 5π/4[ 100 sin(φ) = - sin(φ) cos(φ) = - cos(φ)[5π/4 ; 3π/2[ 101 sin(φ) = - cos(- φ) cos(φ) = sin(- φ)[3π/2 ; 7π/4[ 110 sin(φ) = - cos(φ) cos(φ) = sin(φ)[7π/4 ; 2π[ 111 sin(φ) = sin(- φ) cos(φ) = cos(- φ)Table 4.5.1.1: different phases for computing sine and cosine functions modulo π/4 (the full scale of φ corresponds to π/4 – 1*LSB).

Figure 4.5.1.1: Sine and cosine functions

3 MSb’s of the Phase

valueb15, b14, b13

b13 =1=>

Inv. Φ

(b14⋅b13)+ (b14⋅b13 )=>

Sin ↔ Cos

b15 (b14+b13 )+b15b14b13=>

Invert Sin channel

b15 (b14+b13 )+b15b14b13=>

Invert Cos channel

000001 X X X010 X X011 X X X100 X X101 X X X110 X X111 X

Table 4.5.1.2: Actions to be taken depending on the phase word value coded on 16 bits.

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Figure 4.5.1.2: Sine and cosine generation, taking advantage of their symmetry properties

4.5.2. ½ LSB phase shift

When the phase word in the phase accumulator is ramping up by one LSB at each clock, starting from 0, it reaches (2π – 1 LSB) radians (the full scale of the accumulator) and then 0 again. The transition from (2π – 1 LSB) to 0 brings no discontinuity in the amplitude as the amplitude sinφ for 2π is exactly the same as for 0.

In our context, using modulo π/4 look-up tables (LUTs), let us see what happens at the transition point from one amplitude-value-table to the next. The phase word will be represented on 3 digits to ease the understanding.

When the phase (φ) value ramps up from 000 to 111 (= π/4 – 1 LSB) in the modulo π/4 domain, the sin(φ) value is obtained from the sin(φ) LUT (see table 4.5.1.1). This behaves smoothly with sin(111) = (√2/2 – ε). The next phase value after 111 is 000 and corresponds exactly to π/4 in the modulo π/4 domain. At this point, it is required to take the cos(-φ) value (see table 4.5.1.1), which corresponds to cos (111) = (√2/2 + ε) (111 is the 1’s complement of 000). For sin(π/4), we expect the exact √2/2 value, but we get (√2/2 + ε), which means a small distortion

Note that if we were using a 2’s complement to represent the negative phases, the sin(φ) value would go through a higher transient around π/4. sin(111) = (√2/2 – ε) would be followed by cos(000) = 1, followed again by cos(111) = (√2/2 + ε); 000 being 2’s complement of 000 and 111 the 2’s complement of 001.

One way to solve the problem is to make a ½ LSB phase shift, meaning that the phase φ = (0 + ½ LSB) will be coded “000” and (π/4 – ½ LSB) “111”. In such a context and around φ = π/4, sin(111) = (√2/2 – ε/2) will be followed by cos(111) = (√2/2 + ε/2), which are both the expected values.

4.5.3. Compression technique for phase to amplitude conversion

After having used the symmetry properties that allow a factor eight reduction in memory size (still 240 kb required for both sine and cosine signals), other compression techniques can be applied (Taylor series, trigonometric identities, linear interpolation, Cordic algorithms). The Sunderland approach [4] (using trigonometric identities) will be described here as it is the method being employed. It is also the method being used in the CPS beam control for its DDSs. On the actual board we have obtained a compression ratio of 2.86:1 (total = 22.8:1 taking into account the factor 8 for symmetries => required memory = 84 kb for both sine and cosine) which is not the best that can be achieved [2]

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The Sunderland technique uses the following identity:

sin(A+B+C) = sin(A+B).cos(C) + cos(A+B).sin(C)

sin(A+B+C) = sin(A+B).cos(C) + cos(A).cos(B).sin(C) – sin(A).sin(B).sin(C)

The Phase A+B+C will be written in a 16 bit word, with A representing the 6 MSBs [b15 , b10], B the 5 middle bits [b9 , b5] and C the 5 LSBs [b4 , b0].

As b15 represents the angle value π/4 = 45o: A < 44.3o

B < 0.68o

C< 0.22o

sin(A).sin(B).sin(C) < 1/31420 ≈ 2-14

As 14 bits is the required precision, this term can be neglected

cos(B) – 1 < 1/14199 cos(A).cos(B) – 1.sin(C) < 1/3697971 ≈ 2-22

The value cos(B) can be thus replaced by 1 with still a 22 bit precision on the overall result.

The equation can be re-written as follow (with still a 14 bit precision):

sin(A+B+C) ≈ sin(A+B) + cos(A).sin(C)

5. CIC filter

In order to remove the unwanted mixing products, the DDC mixers should be followed by some kind of low-pass filter. The filter should have minimal group delay and linear phase to preserve stability margins when used in a feedback loop. Apart from classical digital FIRs and IIRs using multipliers, the CIC (Cascaded Integrator-Comb) filter [5] is a widely used alternative. It has the advantage of using little resources (just summations) but lacks the programmability that allows precise shaping of the frequency response. If required, the CIC can be used in a first stage as a decimation filter requiring minimal resources on the high sampling rate side, followed by a conventional FIR on the low sampling rate (CIC used in a decimation circuit) side, where the number of multiplications per second is low.The CIC filter is a low pass digital filter with finite impulse response. It can be used as a decimation filter when the integrator stage is upstream the differentiator (= notch filter) section, or as an interpolation filter when the comb stage is upstream the integrators.A basic one-stage decimation CIC is presented in figure 4.1. The first stage is an integrator. It acts as a low-pass filter with frequency responses as shown in paragraph 4.1. The phase response is linear with a constant group delay.

18

Figure 5.1: CIC filter block diagram

5.1. Intuitive description of the CIC

The CIC filter depicted in figure 4.1 is built out of a series of three main blocks. The first block is an N-stage integrator. N can be set from 1 up to 3 in the actual design. An integrator is a low pass block. In our down-mixing application, we need a finite and constant gain in the low-pass band. The integrator unfortunately provides infinite gain at DC.

0 0.02 0.04 0.06

50

Integrator amplitude response

Figure 5.1.1: Integrator frequency response (x-axis: frequency normalized to sampling frequency)

Adding a differentiator downstream the integrator would overcome the DC infinite gain of the integrator by multiplying infinite by zero. As the differentiator is just the inverse of a integrator, we would unfortunately have a unity response over the entire band…which is of little help when a low-pass response is expected.

0 0.02 0.04 0.06

1

2Differentiator amplitude response

Figure 5.1.2: Differentiator frequency response (M=1) (x-axis: frequency normalized to sampling frequency)

0 0.5 1

50

Integrator amplitude response

0 0.5 1

1


19

Now, by increasing the pipe-line delay (M clock periods) in the delayed branch of the differentiator to a value greater than one, we start to obtain the expected low-pass behavior.Figure 5.1.3 shows the response of the differentiator with M = 2 and Figure 5.1.4 the corresponding one stage (N=1) CIC response

0 0.5 1

1


Figure 5.1.3: Differentiator frequency response with M = 2 (x-axis: frequency normalized to sampling frequency)

0 0.5 1

0.1

10CIC1 amplitude response

Relative Frequency [ ]

Gai

n [ ]

Figure 5.1.4: CIC frequency response with N = 1, R = 1 and M =2 (x-axis: frequency normalized to sampling frequency)

With M=2, N=1 and R=1 (decimation factor) the static gain becomes 6 dB (instead of 0dB with M=1) and the -3dB cutoff frequency is 0.385FS (figure 5.1.4).With M = 3, the DC gain rises to 9.5dB and the cutoff frequency goes down to 0.155 FS

20

0 0.5 1

0.1

10CIC1 amplitude response

Relative Frequency [ ]

Gai

n [ ]

Figure 5.1.5: CIC frequency response with N = 1, R = 1 and M =3 (x-axis: frequency normalized to sampling frequency)

M N R DC gain (dB) FC/FS @-3dB1 1 1 0 ∞2 1 1 6 0.3853 1 1 9.5 0.1554 1 1 12 0.1148 1 1 18 0.05616 1 1 24 0.02832 1 1 30 0.014Table 5.1.1: CIC filter characteristics with respect to CIC parameters

5.2. Choosing the value of M (differentiator pipeline delay)

From table 5.1.1 it can be observed that the cut-off frequency is linked to M by a one to one ratio and so is the DC gain.Although the cut-off frequency can be a meaningful parameter, the position of the filter notches might also be crucial. In the case of a longitudinal beam signal where typically only the harmonics of the revolution (with close synchrotron side bands) are present, making revolution lines and notches coincide is very efficient.The notches are at the multiple frequencies of FS/(R.M), R being the decimation or down-sampling ratio. Effectively increasing R correspond to diminishing FS.We have:

FS = FMDDS/2 = hMDDS FFREV /2.and M should thus be such that

k.FREV = FS/(R.M) or M = FS /(k.R.FREV) = hMDDS / 2kRk can be any integer

The acquisition of the DDC I and Q is achieved by the DSP every fast-loop clock tick in total asynchronism with the DDC clock.

21

In terms of signal acquisition the effect is similar to a jitter of one sampling clock with a maximum peak-peak error equal to TDDC-OUT.To lower the resulting spurious, TDDC-OUT should be kept as small as possible. This means in practice to increase as much as possible M in favor of a minimal R.

5.3. Choosing the value of R (decimation or down-sampling value)

In terms of effect on the cut-off frequency, R acts as a multiplying factor over the value of M (see §5.2) but it has side effects.The decimation stage follows the Integrator stage. At this level, the signal has been filtered to remove the high-frequency components. The new sampling frequency FS / R should be chosen such that the new Nyquist frequency (FS / 2R) is higher than those of the remaining unwanted spectrum lines which are still above the LSB level.

The Gain of the integrator is

|I ( f )|=( 1

√2−2 cos(2π ff S ) )

N

The gain follows a (6.N)dB/octave law up to FS/2N = number of stages of the CIC

If B is the number of bits of the system, a rule of thumb is to have an attenuation of the integrator between the signal of interest and the “new Nyquist frequency” (FS /2R) greater than (6.B)dB which corresponds to (B/N) octaves in terms of frequency difference.

Example: If the signal of interest is at 1 kHz and the resolution of the system is 14 bits, the minimum new Nyquist frequency should be above (1kHz . 214/N) = 16.4 MHz with N=1 => R<3

128 kHz with N=2 => R<31225 kHz with N=3 => R<1600

This approach is very conservative as it takes into account an initial spectrum crowded up to F S/2 with full scale lines.

This first approach gives one limitation to the value of R. There is a second limitation:The signal downstream the CIC will be made available to the DSP. The DSP requires the I/Q signals from the DDC at an asynchronous rate (typ. 20 kHz). We are thus sampling (DSP interrupt rate) a digital signal sampled at a different rate (FS/R).The DDC I/Q signals can be seen from the DSP viewpoint of as a digital signal supplied by a sample and hold beating at the FS/R rate. The spectrum of the equivalent signal is the well known digital spectrum with lines at kFS +/- F0 attenuated by the sinX/X shaped gain of the sample and hold.

In this context, the higher the sampling rate FS/R the lower the aliases.

In summary it is always best using the N and M parameters keeping R=1 to obtain the required low-pass shape. If this is not possible, a trade off should be found by calculating the expected improvement due to the steeper low pass compare to the degradation due to the asynchronous DSP acquisition.

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5.4. Choosing the value of N (number of stages)

The value N impacts the steepness and peak to peak filter attenuation range.

N M R CIC(0) [dB] CIC(FS/2) dB -3dB [F/FS]1 2 1 6 -318 0.252 2 1 12 -640 0.183 2 1 18 -955 0.151 4 1 12 -312 0.1142 4 1 24 -624 0.0833 4 1 36 -936 0.068Table 5.4.1: Number of stages and CIC attenuation.

It can be observed from table 5.4.1 that when increasing the number of stages from 1 to 2, the CIC 3dB

cutoff frequency is decreased by a factor √2 and the min to max attenuation is increased by a factor 2.

When increasing the number of stages from 1 to 3, the 3dB cutoff frequency is decreased by a factor √3 and the min to max attenuation is increased by a factor 3.

5.5. Group delay

The integrator stages count for +N.π [rad] from 0 to FS which corresponds to +0.5.N.TS in terms of group delay.The differentiating stages count for -2π.RMN [rad] from 0 to FS which corresponds to – RMN.TS /2. in terms of group delay.

The overall group delay of the CIC filter is thus:

τCIC = 0.5.(1 – RM) N.TS

TS is the sampling period

5.6. CIC gain

The CIC gain depends on its parameters. A normalization coefficient needs to be applied to its output in order to normalize the amplitude value.The overall CIC DC gain is:

|CIC(0)| = (R.M)N

And the number of bit growth is thus:

BOUT - BIN = N.log2 (R.M) - 1

The Integrator of the first stage should cope with the total CIC maximum DC gain. The required BOUT

correspond to the maximum possible input word integrated over (R.M)N samples. In other terms, the first integrator should not saturate before all the differentiators have their pipe-lines full.

23

5.7. CIC word truncationThe amount of possible bit truncated at each stage without impairing the global performance is estimated in [5].

The number of LSB’s that can be removed at stage j is:

B j=⌊−log2 F j+ log2σT (2 N +1 )+12

log26N ⌋

With a maximum N=3 value, there are 2N stages; stage 1 is the first integrator, stage 2, the second… stage 4 is the first differentiator and stage 2N (=6 in our case) the last one.

Fj = ∑

kh j

2 (k )

h j (k ) are the coefficient of the polynomial expressing the z transfer function of the remaining j to 2N (inclusive) stages.

σ T (2 N +1 )2 =2

2 B j

Expressed at the higher sampling rate stage, the CIC transfer function numerator can be expressed as (1 - z -

RM)3 and the denominator as (1 – z -1)3. Solving this division analytically (with mathlab for example) gives the coefficients h 1(k). removing one integrator (the denominator becomes (1 – z -1)2) one gets the h2(k) coefficient and so on…

24

6. FIR filter

For applications where more selectivity is required an FIR filter is implemented. This FIR can be inserted or de-asserted by the DSP. For the circuit board version with the Altera Stratix EP1S20F484C5 with too limited resources only a fixed moving average, second order filter has been implemented. For the next release, a version with programmable coefficients is to be implemented. Figure 6.1 shows the architecture of a symmetric impulse response device with linear phase (constant group delay). The order of the filter is 2N and uses only N+1 multipliers.

Figure 6.1: Symmetric impulse response FIR filter structure

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7. DDC internal signals monitoring

The user can monitor 28 different signals (see memory map for the list of signals) but only up to 4 at a time within the same machine cycle. Indeed, the DDC monitoring system is divided in 4 different lines. Each line corresponds to a selected signal. For each line, the start measurement time, the number of samples and the sampling rate can be set. The acquisition is limited by the SRAM memory which allows the storage of 1Msamples of 16 bits.

7.1. Acquisition sequence

During the storing process, a main counter rules the acquisition by providing a priority code to the 4 measurement lines.The counter is just cycling at the maximum acquisition rate (MDDS/2) through all the possible line numbers (0 to 4). The counter output determines which line has the priority. When the counter outputs 00, line 1 has the priority. In case it is not ready, line 2 is taking the priority. If line 2 is not ready then line 3 is taking over, then line 4. When the counter output is 01, the sequence of priority is 2, 3, 4, 1; when it is 10, the sequence is 3, 4, 1, 2; when it is 11, the sequence is 4, 1, 3 ,2. A line is ready when a new sample has been acquired.

Table 7.1.1 and 7.1.2 summarize the details of the priority encoding

Counter output RAM acquisition line ready(1 = ready; 0 = not ready,

x = don’t care)

Line selected

1 2 3 4

00 1 x x x 100 0 1 x x 200 0 0 1 x 300 0 0 0 1 4

01 1 0 0 0 101 x 1 x x 201 x 0 1 x 301 x 0 0 1 4

10 1 x 0 0 110 0 1 0 0 210 x x 1 x 310 x x 0 1 4

11 1 x x 0 111 0 1 x 0 211 0 0 1 0 311 x x x 1 4

Table 7.1.1: line priorities as a function of the priority counter output

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Counter output RAM acquisition line ready(1 = ready; 0 = not ready,

x = don’t care)

Line selected

1 2 3 4

01 1 0 0 0 110 1 x 0 0 111 1 x x 0 100 1 x x x 1

10 0 1 0 0 211 0 1 x 0 200 0 1 x x 201 x 1 x x 2

11 0 0 1 0 300 0 0 1 x 301 x 0 1 x 310 x x 1 x 3

00 0 0 0 1 401 x 0 0 1 410 x x 0 1 411 x x x 1 4

Table 7.1.2: list of bit patterns required for each line to be selected

7.2. Acquisition start time and sampling rate

There are only 2 possible clock sources: the main sampling clock issued from the Master DDS and the revolution tags from the same source. For each of these two clock signal a down-sampling or decimation rate, coded on 16 bits, can be chosen.If the user chooses a single signal to be measured, the maximum clock rate (MDDS/2 < 80 MHz) can be chosen. Otherwise, the maximum rate becomes MDDS/2N, where N is the number of signals selected for the same round of measurements.

The start time is triggered by a double-tag issued from the MDDS. For this double tag to be active, the “Next double-tag load register” should be loaded with the proper bit set to specify the role of the next double-tag. (see memory map).

7.3. SRAM timing diagramsThe following timing diagram are valid for the Cypress CY7C1061BV33 actually in use.

Figure 7.3.1: SRAM being read timing diagram

27

Figure 7.3.2: Write in SRAM timing diagram

8. LO frequency measurement

A value of each of the 4 LO frequencies is made available to the DSP in a specific register (see memory map). This value is output from a counter clocked with a reference 80 MHz clock issued from an internal FPGA PLL circuit. This counter is enabled within a time window created by another counter clocked with the MSB of the LO signal and which preset value is taken from the “LO frequency measure window” register coded on 16 bits. The DSP user can thus increase the resolution of the frequency counter by increasing the time interval of measurement.

9. I/Q vector frequency discriminator

The measured value of the frequency error between incoming rf signal and local oscillator (LO) is available to the DSP in two coupled dedicated registers (see memory map). The two values being sent are ∆ ω∙ A2 and A2 , A being the amplitude of the vector constructed with I and Q. The DSP calculates the ratio of the 2 values to extract the frequency difference. The principle of the measurement is described below; note that at each clock sample a new value is provided. This measurement is not based on a counting protocol as for the LO frequency measurement. Here there is no need to wait for the end of the measurement time-window, the process is based on the measurement of I/Q signals derivative. Knowing the amplitude, it gives information about frequency.

The scaling factor taking into account the hardware details is as follow:

∆ F [ Hz]=( ∆ ω∙ A2

A2 )DSP result

∙(1.5 /1.6) ∙(1000)∙(1 /R) ∙[(hMDDS∗FREV [ Hz ])/(64 ∙1.4E6)]

( ∆ ω∙ A2

A2 )DSP result

: decimal value obtained by the DSP after it has divided the values ∆ ω∙ A2 by A2 (A =

amplitude of the vector represented by I/Q) supplied by the DDC.R: decimation factor of the CIC filterhMDDS: revolution frequency harmonic of the Master DDS clock

Peak-peak amplitude of the I/Q vector:

A [Vp-p] = (√ A2 )DSP result /3972

28

(√A2 )DSP result in decimal is the result of the square root of the "amplitude-squared" operation achieved by the DSP. The resulting amplitude corresponds to the harmonic of the DDC input signal, present around the LO frequency.

The frequency discriminator is using the following formulas:

I (t)=A ∙ sin ( Δω∙ t )Q(t )=A ∙cos ( Δω∙ t )

dI (t )dt

=A ∙∆ ω∙cos (∆ ω∙ t )

dQ ( t )dt

=−A ∙ ∆ ω∙ sin (∆ ω∙ t )

Q ∙ dI ( t )dt

=A2 ∙ ∆ ω∙ [cos (∆ ω∙ t ) ]2

I ∙ dQ (t )dt

=−A2 ∙ ∆ ω∙ [si n (∆ ω∙ t ) ]2

⟹ A2 ∙∆ ω=Q ∙ dI ( t )dt

−I ∙ dQ (t )dt

This last equation is used in the FPGA to provide the ( A2 ∙∆ ω) value.

The amplitude-squared value is obtained in the FPGA from the equation:

A2 = I2 + Q2

and finally one get the final frequency error value:

∆ ω=∆ ω∙ A2

A2

29

10. Clock harmonic change

The clock of the SDDS will typically be a harmonic of the beam revolution. In the CERN PSB the revolution frequency is multiplied by a factor three during the cycle from 50 MeV to 1.4 GeV. As the maximum sampling frequency specified for the beam control system is 80 MHz, with a fix harmonic of the clock, this would mean at best that the sampling frequency would drop below 27 MHz at injection and thus the practical bandwidth of the system would drop around 9 MHz. This value is too low to cope with the PSB 16 MHz cavity.In order to correct this issue, the Master DDS clock used to sample the daughter cards is capable to change its harmonic in synchronism with the double tag it generates. The daughter cards in turn will also change their frequency words value in order to supply the same LO frequency, before and after the harmonic change, hopefully without transients.The master DDS is designed to change its harmonic by factors of two (divide by one, two, four or eight); this allows on the daughter cards to make a simple shift of the frequency word to obtain the compensating multiplying factor.

Unfortunately, due to pipeline delay within the LO rf signal creation, changing the frequency word while the clock harmonic changes is not sufficient to avoid transients.

When the MMDS harmonic is changed together with the LO DDS frequency word, the amplitude samples into the pipeline chain correspond to the previous clock harmonic.When the MDDS clock harmonic is suddenly divided by 2, the LO will output during the pipeline duration the expected initial frequency divided by 2. In the present circuit the pipeline delay within the LO creation process is equal to 8 Tclk Within this pipeline the samples are just wrong when the clock frequency is changed;One solution to this problem is to create another LO DDS programmed with the future frequency value and clocked at half the rate. During the clock harmonic change there would be a switching from one LO source to the other and a clock exchange. There are of course some phase offsets to be taken care of during this process. How important is this phase jump on the DDC side (rf phase measurement)? This rf LO signal is sent on one input of a mixer.The other input is the rf being measured (or compared to the LO) experiencing the 7.5 Tck of the 14 bit ADC. On the LO side, due the 8 Tck pipeline delay, the signal will be delayed by 4 new Tck as the clock frequency is divided by two, and its frequency will be halved during 8 new Tck.

On the rf input side, due to the 7.5 Tck pipeline delay of the ADC, the signal will be delayed by 3.75 TckConcerning this delay aspect, the global effect is that the LO is delayed by 0.25 new Tck with respect to the rf input. We know that during 8 Tck, the LO frequency will be halved, while on the rf side nothing will happen before the distortion from the SDDS transmitted to the cavity and beam will be perceived by the DDC. In the PSB present beam control the delay from low-level source to cavity added to the delay from cavity voltage probe back to the measurement mixer is equalized to 1316 ns on all cavities and all rings.The beam signal has been equalized in length with respect to the cavity return signal, so the delay is the same.

30

So, during 8 new Tck (= 200ns typ) the DDC will output a perturbation due to the LO frequency being halved; this implies an error signal at the rf frequency (not DC anymore), thus rejected by the downstream low-pass filter.After this 8 new Tck period will only remain the effect of the 0.25 Tck delay which can be compensated for. After 1316 ns the mixer will receive the perturbation from the SDDS and transformed by either the cavity or by the combined cavity-beam effect. On the cavity side, the effect of a 200 ns transient can be neglected, as the cavity bandwidth is typically lower than 500kHz and thus its time constant higher than 200 us.Only the high power could trip due a too high current demand when halving the frequency abruptly.As the effect on the cavity is minor, the effect on the beam is even weaker. On the DDC side, two different measurements setups need to be analyzed: Measurement of beam, narrow band cavities or external reference signals. These signal are little or not affected by the MDDS harmonic change.1) The LO signal will be halved during 8 new Tck cancelling the output error signal, which is not a problem as long as the error signal was null before the clock harmonic change.2) The LO signal will be delayed by 0.25 new Tck (= 6.25 ns typ.). This can be compensated for. Measurement of wideband cavities or SDDS output signals. These signals are much or totally affected by the SDDS perturbation occurring during the MDDS harmonic change.1) The LO signal will be halved during 8 new Tck on one side of the mixer.On the second input of the mixer,- either there is a SDDS with a small delay which would mean that the 2 inputs of the mixer would see the half frequency on both the inputs and the errors signal would become proportional to their phase difference (can be big)- either there is a wideband cavity return signal being perturbed after a long delay (1316 ns in the present PSB) which means that first the mixer output will drop to zero during the 8 new Tck LO pipeline (200 ns typ.) and then would drop again after 1316 ns and during 200 ns as it experiences a different frequency on each side of the mixer.2) The LO signal will be delayed by 0.25 new Tck (= 6.25 ns typ.). This can be compensated for. In the present setup without any duplication of the hardware, a phase offset, compensating for the extra delay of 0.25 new Tck, should be added.

ex: the MDDS harmonic (with respect to the beam revolution) goes from 64 to 32,0.25 Tck represent (360 degrees/32) x 0.25 = 2.8125 degrees of the revolution.The DDC LO needs thus to receive a phase offset equal to +2.8125 degrees of the revolution in order to minimize the impact on the beam. One solution to the DDC problem, with respect to the clock harmonic change, is to freeze the error at the output of the mixer during the expected transients in order to avoid triggering the impulse response of the concerned feedback loop.

31

11. DSP interfacing registersAll registers accessible from the DSP are listed in a memory map (see annex). Some of these registers have particularities that will be described here.

11.1. Communication protocol:The DDC, as all daughter cards, is connected to a data and address bus that is also common to the DSP and the VME interface.As both the DSP and the VME bus – via its VME interface – can master the bus, the daughter cards should be compatible with the different protocols used on the communication bus.

11.1.1. VME leading the bus.

The VME bus on the VME 64x crate backplane is governed by an asynchronous master-slave protocol. A system controller determines which of the many possible masters will handle the bus. Data is passed between modules using interlocked handshaking signals. The cycle speed is set by the slowest module participating in the cycle. Using the 2eVME protocol the R/W cycle can take as little as 50 ns (100 ns otherwise).All bus activities take place on the four sub-buses: the Data Transfer Bus, the Data Transfer Arbitration Bus, the Priority Interrupt Bus and the Utility Bus. There are 32 address pins and 32 data pins on the back-plane connector, but using a multiplexed architecture (allowed in VME64 and VME64x), the data and address transfer can be set up to 64 bits. In this context, data and addresses share the same buses. In the first part of the cycle the address is sent on both data and address tracks, then, in the second part of the cycle it is the turn of the data transfer on the same lines. In our context, there will be only non-multiplexed data transfer.

The first protocol to be described is asynchronous with handshake. It is the safest, most universal and doesn’t make assumptions on the reaction speed of the addressee, but might not be as fast, in some configurations, as the synchronous protocol, or the asynchronous protocol without handshake. It makes use of the different lines provided (DSP address bus [b63 - b32], DSP data bus [b13 - b0], DSP Read/Write lines (RDH/WRH), DSP AKNowledge, DSP IRQ0 interrupt request and SEL0,1 from DSP2RCVR). Here is a brief decomposition of the communication stages.

1) Write to DDC Register Protocol

- The "AKN" bit is in the "available" state showing that the SDDS is ready for any action.- The DSP sends the "DSPaddress" of the register to be filled and its related "DSPdata", together with the active "WRH" bit.- The "SEL0,1" bit becomes active and puts "AKN" in the "busy" state.- The targeted register is loaded by the appropriate procedure and the "AKN" is reset to the "available" state.- If "AKN" doesn't become "available" after W (number of wait state = 2 typ) DSP cycles, an error procedure is launched.

2) Read from DDC Register Protocol

- The "AKN" bit is in the available state showing that the SDDS is ready for any action.- The DSP sends the "DSPaddress" of the register to be read , together with the active "RDH" bit.- The "SEL0,1" bit becomes active and puts "AKN" in the "busy" state.- The targeted register data is loaded to the DSP data bus and the "AKN" is reset to the "available" state.- If "AKN" doesn't become "available" after W DSP cycles, an error procedure is launched.

3) Write to DDC Memory (SDDS SRAM, 18 bit address, 16 bit data) protocol

- The DSP will choose the page by writing first to the page register (see write to DDC register protocol).

32

- The DSP sends the "DSPaddress" (14 LSBs) of the memory location to be filled and its related "DSPdata" with only the 16 MSB's, together with the active "WRH" bit.- The "SEL0,1" bit becomes active and puts "AKN" in the "busy" state.- The targeted memory location is loaded by the 16 MSB's of the "DSPdata"word through an appropriate procedure and the "AKN" is reset to the "available" state.- If "AKN" doesn't become "available" after W DSP cycles, an error procedure is launched.

4) Read from DDC Memory (SDDS SRAM, 18 bit address, 16 bit data) protocol

- The DSP will choose the page by writing first to the page register (see write to SDDS register protocol).- The DSP sends the "DSPaddress" (14 LSBs) of the memory location to be read facontogether with the active "RDH" bit.- The "SEL0,1" bit becomes active and puts "AKN" in the "busy" state.- The targeted memory location is made available on the 16 MSB's of the "DSPdata" bus and the "AKN" is then reset to the "available" state.- If "AKN" doesn't become "available" after 4 DSP cycles, an error procedure is launched.

5) Interrupt request from the DDC card

- The "IRQ0" is set active by the DDC regardless of the other signals.- The DSP will read the DDC interrupt register following procedure 2) where the type of alarm will be coded.- "IRQ0" will be deactivated at the end of the Interrupt request register reading procedure at the same time as "AKN" is set the "available"

11.2. Address decodingThe address bus controlled by the DSP is send to the DDC in the form of 2 distinct terms. There are 15 lines (DSP_ADDR[14..0]) directly issued from the DSP and 2 selection lines (SELN0, SELN1) coming from an address decoder FPGA located on the DSP board which decodes the base address. The SELN signals are thus delayed with respect to the offset address by about 12ns (measured value). If not taken into account, this delay can cause a bad decoding and a bus conflict during this time interval.

33

Figure 10.2.1: Timing diagram summarizing all the possible bus communication (DSP or VME directed) Although there no direct communication between VME and DDC, the DDC shouldn’t conflict with the bus when the VME leads the sequence.

Figure 10.2.2: Timing diagram with the DSP as bus master and in asynchronous READ mode (memory read – bus master mode)

34

W = number of wait states specified in WAIT register HI = 1 if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0H = 1 if an address hold cycle occurs as specified in WAIT register; otherwise H = 0I = 1 if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0TCK = 25 nsTCORE CLOCK = 12.5 ns

Figure 10.2.3: Timing diagram with the DSP as bus master and in asynchronous WRITE mode (memory write – bus master mode)

35

Figure 10.2.4: Timing diagram when the VME master reads the bus.

36

Figure 10.2.5: Timing diagram when the VME master writes onto the bus.

In order to take into account the timing constraints depicted above, an address decoder enabling circuit had to be implemented (see figure 10.2.6). The active low SELN bits, which are part of the address word, are delayed with respect to the other bits by about 12 ns (specific treatment on the mother board). This implies that the address is only valid 12 ns after any of its change.To avoid reading from or writing into a wrong address, the “active” falling edge of the Read and Write (RDN, WRN) signals was chosen to be delayed by the same 12 ns (at least). This is achieved through two flip-flops clocked at 80 MHz (from 12.5 up to 25 ns delay depending on the relative phase of the 80 MHz clock with respect to the DSP 40 MHz clock).The rising edge of RDN and WRN, which indicates the end of the process as demanded by the DSP is not delayed in order to disable immediately the process before any change of the address.

The resulting REG_ADDR_VALID and MEMORY_ADDR_VALID bits create a reference window used to gate all the DSP bus address decoders.

Note that the double flip-flop setup in the delay path is well suited to avoid metastability.

37

OR2

inst1

AND2

inst

NOT

inst34

AND2

inst7

NOT

inst36

NOT

inst549

NOT

inst550

AND2

inst4

AND2

inst5

CLRN

DPRN

Q

DFF

inst6

CLRN

DPRN

Q

DFF

inst8

CLRN

DPRN

Q

DFF

inst9

CLRN

DPRN

Q

DFF

inst10

80_MHz

80_MHz

80_MHz

80_MHz

WRN

RDN

SELN0

SELN1

REG_ADDR_VALID

MEMORY_ADDR_VALID

Figure 10.2.6: Address decoder enabling circuit

11.3. RF synchronous registers

The rf synchronous register is aimed at providing values to the DSP that are obtained in the DDC from an asynchronous rf clock. The circuits makes such that the “rf” sample following the read request is made available on the data bus. When this data is ready, the ACK (acknowledge) bit is activated after a minimal delay of 8ns (the DSP setup time) while remaining synchronous with the DSP 40 MHz clock. This requirement for ACK synchronicity in the context of an asynchronous communication protocol is rather “original” [3]Tests have proven that letting the ACK not being synchronous led to zero value being recorded erratically by the DSP.To avoid blocking the DSP in the absence of the rf clock, the ACK is automatically generated after eight 40 MHz periods.

TRI

inst194

NOT

inst195

AND2

inst196

TRI

inst22

PRN

CLRN

D

ENA

Q

DFFE

inst23NOT

inst5

CLRN

DPRN

Q

DFF

inst13CLRN

DPRN

Q

DFF

inst6

NO

T

inst

7

CLRN

DPRN

Q

DFF

inst14

PRN

CLRN

D

ENA

Q

DFFE

inst24

VCC

CLRN

DPRN

Q

DFF

inst8

NO

T

inst

9

down counterclock

aset

q[2..0]cout

lpm_counter10

inst

RDN

SELECT_REG

MHz_40

RF_CLOCK

DSP_DATA[63..32]

ACK

DATA[63..32]

RF_CLOCK

MHz_40MHz_40

MHz_40MHz_40

ACK delay > set-up time DSP (8ns)

This circuit releases the AKN after a w hile w hen the rf clock is not present or too slowThis avoids blocking the DSP

Figure 10.3.1: RF synchronous register for the LO frequency measurement value

38

The DDC has so-called coupled values that need to refer to the same time sample. For instance, when measuring a I/Q pair, they need to be measured for the same clock tick. These coupled values need to be read in always the same sequence by the DSP (see memory map for the convention). Both values are stored in the output registers when the first read sequence starts (at the first sampling clock edge after the start of the asynchronous read sequence), and only at the end of the second read sequence, the registers are reset.

TRI

inst191

NOT

inst192

AND2

inst193

TRI

inst20

PRN

CLRN

D

ENA

Q

DFFE

inst21NOT

inst5

NO

T

inst

8

PRN

CLRN

D

ENA

Q

DFFE

inst22

VCC

NO

T

inst

15

CLRN

DPRN

Q

DFF

inst17

VCC

NOT

inst24

down counterclock

aset

q[2..0]cout

lpm_counter8

inst2 CLRN

DPRN

Q

DFF

inst7CLRN

DPRN

Q

DFF

inst12 CLRN

DPRN

Q

DFF

inst13

RDN

SELECT_REG

RF_CLOCK

DATA[63..32]

RF_CLOCK

MHz_40 MHz_40

DSP_DATA[63..32]

LOCK_DATA_ACQUISITION

RESET_DATA_LOCK

MHz_40

MHz_40set-up time DSP (8ns)

This circuit releases the AKN after a w hile w hen the rf clock is not present or too slowThis avoids blocking the DSP

ACK

Figure 10.3.2: RF synchronous register for the I signal

AND2

inst233

TRI

inst18

NOT

inst191

TRI

inst231PRN

CLRN

D

ENA

Q

DFFE

inst21

NO

T

inst

3

CLRN

DPRN

Q

DFF

inst16CLRN

DPRN

Q

DFF

inst12CLRN

DPRN

Q

DFF

inst13

CLRN

DPRN

Q

DFF

inst1

VCC

NOT

inst5

GND

RESET_DATA_LOCK

DATA[63..32]

RF_CLOCK

LOCK_DATA_ACQUISITION

80_MHZ 80_MHZREGISTER_SELECTED

RDN

ACK

DSP_DATA[63..32]

At the rising edge of either WRN or RDN (the other being high), The cycle is completed.

Figure 10.3.3: RF synchronous register for the Q signal, blocked by the reading of I

39

11.4. Double-tag synchronous registers

Some registers need to be loaded at a very predictable time. The double tag issued from the MDDS is designed for this task. The synchronous load takes place in 3 stages. First the user needs to load a so-called pre-load register with the foreseen value. Second, another specific register, the “next tag load register” should be written-to by the DSP to activate the bit or the bits corresponding to the register or to the registers to be synchronously loaded.Last, the DSP asks the MDDS for a double tag activation. This tag is part of the clock signal which is distributed on equal length cables over the entire system. All the targeted registers will thus change their parameter synchronously at the tag following the double tag (one revolution later). Reminder: the single tag is short clock pulse sent at the machine revolution rate and the double tag is just a tag inserted after the first one with a normal clock pulse in between the two.

Figure 10.4.1: Double tag synchronous loading – timing diagram

The received MDDS clock is at twice the rf clock frequency. It is divided by two to create the sampling clock with the 50 % duty cycle required by the DAC. The wide tag pulse is created by a dedicated circuit outside the FPGA. Its rising edge is synchronous with the trading edge of the clock pulse corresponding to the tag. The DOUBLE_TAG_MEM bit enables the synchronous loading a new data. It is created by the second rising edge of the clock following the clock pulse corresponding to the tag – if it detects a long wide-tag corresponding to a double tag.

Figure 10.4.2: Creation of the DOUBLE_TAG_MEM bit necessary to enable the synchronous loading of data

WIDE_TAG

RF_CLOCK

The wide tag lasts 1 period of the RF_CLOCKWhen it is a double tag, it lasts 2 periods of the RF_CLOCKThe rising edge of the tag corresponds to the trailing edge of RF_CLOCK

DOUBLE_TAG

MDDS_CLK

WHEN DOUBLE TAG

Change MDDS clock freq at this time

1 2 3 4 5 6Rev Tag

TAG_GLITCH

DOUBLE_TAG_MEM

CLRN

DPRN

Q

DFF

inst40

AND2

inst58

CLRN

DPRN

Q

DFF

inst59

CLRN

DPRN

Q

DFF

inst66

VCC

CLRN

DPRN

Q

DFF

inst68NOT

inst69

CLRN

DPRN

Q

DFF

inst92

NOT

inst93RF_CLOCK RF_CLOCK

DOUBLE_TAGWIDE_TAG

DLE_TAG_MEM

RF_CLOCKWIDE_TAG

RESET_NEXT_TAG_LOAD_REG

40

If the DLE_TAG_MEM is activated and the corresponding NEXT_TAG_LOAD register bit is set, then the following tag (one revolution later) will load the new data.

Figure 10.4.3: Synchronous loading of new data with the tag following the double tag (one revolution later)

11.5. Double tag synchronous pulses

The reset of the phase accumulator and the start for the acquisition of selected inner FPGA signals is also synchronous the double tag.The circuit that generates them is depicted in figure 10.5.1

Figure 10.5.1: Circuit generating the reset of the phase accumulator and the start of the acquisition of inner signals into the SRAM

The so-called TAG_GLITCH is the equivalent of the WIDE_TAG but with a fixed one-clock-period length. This way the reset pulse is not sent during the occurrence of the double-tag and then another time at the next tag.

CLRN

DPRN

Q

DFF

inst64NOT

inst65

VCC

CLRN

DPRN

Q

DFF

inst90

NOT

inst91

LCELL

inst94RF_CLOCK

TAG_GLITCH

WIDE_TAG

PRN

CLRN

D

ENA

Q

DFFE

inst39

AND2

inst63

CH1_H_LO_SYNC[63..32]CH1_H_LO[63..32]

WIDE_TAGCH1_NEXT_TAG_LOAD[32]

DLE_TAG_MEM

OR2

inst1AND2

inst70

AND2

inst72

TAG_GLITCH

CH1_PH_ACCU_RESET

CH1_NEXT_TAG_LOAD[32]

DLE_TAG_MEM

CH1_MODE_OF_OP[39]

41

12. Acknowledgments

The authors would like to thank Flemming Pedersen who initiated the project of importing the digital beam control designed in BNL, and adapting it to the CERN requirements. He was a leading person for the definition of the system architecture.

13. References

[1] An analysis of the output spectrum of direct digital frequency synthesizers in the presence of phase accumulator truncation. Henry T. Nicholas, III, Henry Samueli, 1987

[2] K.A. Essenwanger and V.S. Reinhardt, “Sine output DDSs. A survey of the state of the art”, Proc. 1998 IEEE Int. Frequency Control Symp., May 1998, pp. 370–378.

[3] p26 in http://www.analog.com/static/imported-files/data_sheets/ADSP-21160M_21160N.pdf

[4] CMOS/SOS Frequency Synthesizer LSI Circuit for Spread Spectrum Communications, D. Sunderland, R. Strauch, S. Whartfield, H. Peterson, C. Cole, IEEE Trans. Soluid State Circuits, SC-19, no. 4, 1984

[5] An Economical class of digital filters for decimation and interpolation, Eugene B. Hogenauer, IEEE transactions on acoustics, speech and signal processing, Vol. ASSP-29, NO.2, April 1981

42

http://www.analog.com/static/imported-files/data_sheets/ADSP-21160M_21160N.pdf

14. Annex

14.1. Connections to the DSP board

Site connectors:The DDC card uses 4 so-called site connectors. Each connector is plugged into a DSP board 69-pin socket. The following description locates the connectors for an observer facing the DSP board component side with the front panel on his left.

Top left connector (1/4) Top right connector (2/4)pin pin pin pin1 DSPaddr0 2 FLAG0 1 INIT Done 2 Gnd3 DSPaddr1 4 FLAG1 3 CRC_ERROR 4 Gnd5 DSPaddr2 6 DSPIRQ0 5 NC 6 Gnd7 DSPaddr3 8 DSPWRH 7 TDI_MB (JTAG) 8 Gnd9 Gnd 10 Gnd 9 Gnd 10 Gnd11 DSPaddr4 12 DSPRDH 11 TCK_MB (JTAG) 12 Gnd13 DSPaddr5 14 DSPACK 13 TMS_MB (JTAG) 14 Gnd15 DSPaddr6 16 SITEnSEL0 15 TDO_MB (JTAG) 16 NC17 DSPaddr7 18 SITEnSEL1 17 NC 18 NC19 Gnd 20 Gnd 19 Gnd 20 Gnd21 DSPaddr8 22 DSPdata44 21 NC 22 NC23 DSPaddr9 24 DSPdata45 23 NC 24 NC25 DSPaddr10 26 DSPdata46 25 NC 26 NC27 DSPaddr11 28 DSPdata47 27 NC 28 NC29 Gnd 30 Gnd 29 Gnd 30 Gnd31 DSPaddr12 32 DSPdata48 31 NC 32 NC33 DSPaddr13 34 DSPdata49 33 NC 34 NC35 DSPaddr14 36 DSPdata50 35 RESET 36 LINK port_CLK

37 40 MHz CLK 38 DSPdata51 37 NC 38 LINK port_ACK

39 Gnd 40 Gnd 39 Gnd 40 Gnd41 DSPdata32 42 DSPdata52 41 NC 42 LINK port_DATA0

43 DSPdata33 44 DSPdata53 43 NC 44 LINK port_DATA1



49 Gnd 50 Gnd 49 Gnd 50 Gnd51 DSPdata36 52 DSPdata56 51 Spare 52 LINK port_DATA4

53 DSPdata37 54 DSPdata57 53 Spare 54 LINK port_DATA5



59 Gnd 60 Gnd 59 Gnd 60 Gnd61 DSPdata40 62 DSPdata60 61 Spare 62 +5 AVDC63 DSPdata41 64 DSPdata61 63 Spare 64 - 5 AVDC65 DSPdata42 66 DSPdata62 65 +3.3 V 66 + 5 DVDC67 DSPdata43 68 DSPdata63 67 +3.3 V 68 +2.5 V69 Gnd 69 +2.5 V

43

Bottom left connector (3/4) Bottom right connector (4/4)pin pin pin pin1 NC 2 NC 1 INIT Done (spare) 2 Gnd3 NC 4 NC 3 CRC_ERROR (spare) 4 Gnd5 NC 6 NC 5 NC 6 Gnd7 NC 8 NC 7 TDI_MB (JTAG)

(spare)8 Gnd

9 Gnd 10 Gnd 9 Gnd 10 Gnd11 NC 12 NC 11 TCK_MB (JTAG)

(spare)12 Gnd

13 NC 14 NC 13 TMS_MB (JTAG)(spare)

14 Gnd

15 NC 16 NC 15 TDO_MB (JTAG) (spare)

16 NC

17 NC 18 NC 17 NC 18 NC19 Gnd 20 Gnd 19 Gnd 20 Gnd21 NC 22 NC 21 NC 22 NC23 NC 24 NC 23 NC 24 NC25 NC 26 NC 25 NC 26 NC27 NC 28 NC 27 NC 28 NC29 Gnd 30 Gnd 29 Gnd 30 Gnd31 NC 32 NC 31 NC 32 NC33 NC 34 NC 33 NC 34 NC35 NC 36 NC 35 NC 36 LINK port_CLK

37 NC 38 NC 37 NC 38 LINK port_ACK

39 Gnd 40 Gnd 39 Gnd 40 Gnd41 NC 42 NC 41 NC 42 LINK port_DATA0

43 NC 44 NC 43 NC 44 LINK port_DATA1



49 Gnd 50 Gnd 49 Gnd 50 Gnd51 NC 52 NC 51 Spare 52 LINK port_DATA4

53 NC 54 NC 53 Spare 54 LINK port_DATA5



59 Gnd 60 Gnd 59 Gnd 60 Gnd61 NC 62 NC 61 Spare 62 +5 AVDC63 NC 64 NC 63 Spare 64 - 5 AVDC65 NC 66 NC 65 +3.3 V 66 + 5 DVDC67 NC 68 NC 67 +3.3 V 68 +2.5 V69 NC 69 +2.5 V

Table 13.1.1: Signal present on the daughter card socket

DSPIRQ0: Interrupt request to DSP. Active highDSPWRH/RDH: Write High / Read High (high means 32 MSB’s of the DSP bus [63 .. 32] – those connected to the site. Active low DSPACK: Memory acknowledge to/from DSP ≡ ready for memory access; active highLINK port DATA, CLK, ACK: link port data bus, connection to DSP and VME bus P2 connector (rear transition card takes signals from P2 and make them available for outside use.SITEnSEL0/1: Selection inputs received from DSP2RCVR FPGA decoder on mother board. The DSP2RCVR will decode the 32 bit address from the DSP and activate the SEL0/1 on the daughter board that is being targeted. Active low.

44

14.2. List of the different motherboard blocks sharing the signal existing on the DDC card

Data Shared by:

DSPdata [63, 32] Site connectorTiming interface (U37)Flash memory (U33)RAM (U23→U30)DSP2RCVR (U36)REC2DSP(U35)DSP (U34)

DSPaddr [14, 0] Site connectorTiming interface (U37)Flash memory (U33)RAM (U23→U30)DSP2RCVR (U36)REC2DSP(U35)DSP (U34)VME Bus Interface (U1)Buffer (U5,U6,U11, U12)

DSP Control(FLAG0-1, DSPIRQ0, DSPWRH/RDH/ACK

Site connectorDSP2RCVR (U36)REC2DSP(U35)DSP (U34)VME Bus Interface (U1)Buffer (U7,U8)

LINK BUS (link ports) Site connectorDSP (U34)

PERIPHERAL-CONTROL(RCVRDS, RCVRWR, RCVRnOVR, Site n CFG0-3, Site n SYNC0-2)

DSP2RCVR (U36)

Site n SEL 0-1 DSP2RCVR (U36)

RCVR n Data0-15 REC2DSP(U35)

Table 13.2.1: List of the different motherboard blocks sharing the signal existing on the DDC card

45

14.3. FPGA interconnections

Figure 14.3.1 shows how the FPGA is interconnected to the other parts of the DDC circuit.

Figure 13.5.1: FPGA interconnections

46

14.4. Memory map

In our context, both the VME and the DSP address bus are 32 bit wide. The DSP data bus is 32 bits whereas the VMe data bus is The DDC is considered to have a double width as it uses two site connectors on the mother board. It is connected either to the site connectors 1 and 2 (top of the motherboard) or to the site connectors 3 and 4 (bottom of the mother board).When connected to the top of the motherboard, its DSP offset address becomes 0x 00C8 0000; when connected to the bottom the offset is 0x 00CA 0000. In the following register and memory map, the offset address assume the use of sites 1 and 2 connectors to plug the DDC daughter card on the DSP mother board. The DDC could also be plugged into the two connectors of sites 3 and 4, making the base address change from 0x00C80000 to 0x00CA0000 (8 replaced by A in the following table). The base address 0x00C90000 is reserved for site 2 and 0x00CB0000 for site 4, but as the selection bits (SEL0 and SEL1) have not been wired to the DDC daughter card, they cannot be used.In the following tables, there are 4 VME addresses for each DSP address. The reason is that the VME points to bytes when the DSP points to words (32 bits in this context), which means four times as much information.

Note that to access the 32 MSB’s of the DSP data bus [63 , 32] (which correspond to the 32 bits of the DDC data bus), the DSP address needs to be odd (specification of the DSP). This implies that from the DDC address bus [14 , 0], b0 is always set to “1” when the DDC is addressed. In the next revision of the DSP carrier board, the bits [15, 1] of the DSP address bus will be connected to the 15 bits of the DDC address bus thus doubling the addressed space.

Each one of the DDC register can be either written-to or read-from the DSP depending on the read/write bits activated by the DSP. Only the buffered registers do not fulfill this requirement. A buffered register is a double stage register with first the offline register that is written-to by the DSP and can be read back, and second the online register that take the value of the offline register when a “double tag” occurs after the proper bit has been set in the “next double tag load register”. This online register cannot be written to by the DSP but only read.

Resource R/W Offset address (hexadecimal notation)

DSP Base address [32 , 0] = 0x 00C8 0000 (site 1,2) 0x 00CA 0000 (site 3,4)

VME Base address [32 , 0] = 0x 00F0 0000 (site 1,2) 0x 00F2 0000 (site 3,4)

Global address spaceDDC internal registersSEL0 = 0

From 0x 0000To 0x 7FFF

DDC SRAM direct accessSEL 1 = 0Beware: the DSP has the priority to access the RAM with respect to the FPGA internal signal acquisition circuit. When reading from or writing to the SRAM you corrupt the acquisition if the acquisition is not ended.

From 0x 8000To 0x FFFF

47

DDC registers common to all channels From 0x 0000To 0x 0FFF

DDC registers for channel 1 From 0x 1000To 0x 1FFF




Asynchronous registers common to all channelsPage register for SRAM accessThe data 6 LSB’s will become the 6 MSB’s of the RAM address. b0 of page register = b14 of RAM addressNot used with the limited resources of the EP1S20F484C5 FPGA

R/W 0x 0001

Line 1-to-4 signal selection Note that the RAM is only 16 bits wide and thus the data read from if will cover the 16 LSBs of the DSP data word DSP_DATA[47..32].To avoid timing conflicts between lines at the highest sampling rates, the selected lines should have consecutive numbers (1, 2, 3 or 3,4…).

8 MSB’s: signal number for line 48 second MSB’s: signal number for line 38 third MSB’s: signal number for line 28 LSB’s: signal number for line 1

The hexadecimal value corresponding to each signal is shown below.

No signal = 00ch1 ADC = 01ch2 ADC = 02ch3 ADC = 03ch4 ADC = 04ch1 LO I = 05ch2 LO I = 06ch3 LO I = 07ch4 LO I = 08ch1 LO Q = 09ch2 LO Q = 0Ach3 LO Q = 0Bch4 LO Q = 0Cch1 I MIX out = 0Dch2 I MIX out = 0Ech3 I MIX out = 0Fch4 I MIX out = 10ch1 Q MIX out = 11ch2 Q MIX out = 12ch3 Q MIX out = 13ch4 Q MIX out = 14ch1 I CIC out = 15ch2 I CIC out = 16ch3 I CIC out = 17ch4 I CIC out = 18

R/W 0x 0003

48

ch1 Q CIC out = 19ch2 Q CIC out = 1Ach3 Q CIC out = 1Bch4 Q CIC out = 1CNot implemented due to the limited resources of the EP1S20F484C5 FPGALine 1 RAM start addressb51 = MSB, b32= LSB (20 bits)Not implemented due to the limited resources of the EP1S20F484C5 FPGA

R/W 0x 0005

Line 2 RAM start addressNot implemented due to the limited resources of the EP1S20F484C5 FPGA

R/W 0x 0007


R/W 0x 0009


R/W 0x 000B

Line 1 RAM stop addressb51 = MSB, b32= LSB (20 bits)Not implemented due to the limited resources of the EP1S20F484C5 FPGA

R/W 0x 000D

Line 2 RAM stop addressNot implemented due to the limited resources of the EP1S20F484C5 FPGA

R/W 0x 000F


R/W 0x 0011


R/W 0x 0013

Line 1 sampling clock b63: sampling clock = MDDS clock divided by 2 b62: sampling clock = Revolution tags b47 – b32: Down-sampling rate (b47 = MSB)

The maximum sampling frequency on each line is this of the MDDS clock divide by 2 and divided by the number of lines selected. Not implemented due to the limited resources of the EP1S20F484C5 FPGA

R/W 0x 0015

Line 2 sampling clockNot implemented due to the limited resources of the EP1S20F484C5 FPGA

R/W 0x 0017

Line 3 sampling clock Not implemented due to the limited resources of the EP1S20F484C5 FPGA

R/W 0x 0019

Line 4 sampling clockNot implemented due to the limited resources of the EP1S20F484C5 FPGA

R/W 0x 001B

General Next double-tag load register

b32: start acquisition of line 1b33: start acquisition of line 2b34: start acquisition of line 3b35: start acquisition of line 4Not implemented due to the limited resources of the EP1S20F484C5 FPGA

R/W 0x 001D

Error registerReading this register resets the errors at the end of the reading process; same when sending a reset via the Global control register (0x 002B)

b32: Address set by the DSP not in use in the DDCb33: RAM line 1 full N/Ab34: RAM line 2 full N/Ab35: RAM line 3 full N/A

b36: RAM line 4 full N/Ab37: Line 1 RAM sampling rate too high N/Ab38: Line 2 RAM sampling rate too high N/Ab39: Line 3 RAM sampling rate too high N/A

R 0x 0021

49

b40: Line 4 RAM sampling rate too high N/Ab41: CRC_ERROR, if this bit is active, the FPGA should be reconfiguredb42: CH1 ADC Out-of-Rangeb43: CH2 ADC Out-of-Range

b44: CH3 ADC Out-of-Rangeb45: CH4 ADC Out-of-Rangeb46: No sampling clock

Disable error-register bits

Any bit in this register put in the active state “high” will disable the corresponding error register (0x 0021) bit. For example, if b32 is set high, the “Address set by the DSP not in use in the SDDS” error bit will be disabled and thus will not trigger Irq0. Nevertheless it will still appear in the error register.

R/W 0x 0023

Compilation DateThe DDC design date will be used as the version number. The final word when written in hexadecimal will provide dd.mm.yy (yy being the year offset from 2000)

b55 - b48: day (2 digits in hexa)b47 - b40: month (2 digits in hexa)b39 - b32: year (2 digits in hexa)

R 0x 0025

Compilation time

b47 - b40: hour (2 digits in hexa)b39 - b32: minute (2 digits in hexa)

R 0x 0027

Status

b32: sampling clock received (detection of a transition within a window of 75ns)

b33: IRQ interrupt signal activated (high = interrupt) (on the DSP bus it is active-low)

b43: Ch 1 HLO ramping (equal to one when the local oscillator is ramping from one frequency value to another - see b43 of CHn Mode of Operation register))

b44: Ch 2 HLO rampingb45: Ch 3 HLO rampingb46: Ch 4 HLO ramping

R 0x 0029

Global control

b32: reset error register. The reset occurs the same way as when there is a read access to the error register. This register is reset automatically after the reset has occurred.

W 0x 002B

50

Channel distinct registersCH n Preset LO frequency (pre-load asynchronous register – waiting for a double-tag synchronous load) n Є [1 , 4]With the EPS1S20 FPGA there are only 2 LO sources. Channel 1 feeds CH3 and CH2 feeds CH4.

b63 =1 => fLO = frf clock /2 = fMDDS / 4b62 =1 => fLO = frf clock /4etc…

H LO word=

hLO

hMDDS⋅233

NB: It is foreseen to change on flight the Master DDS clock frequency scaled by a factor 1, 2, 4 or 8. The opposite factor should be applied to the LO frequency word to respond with the same output frequency. Unfortunately, the intrinsic pipe line delay from phase accumulator to sine wave output is actually 11 sampling clock periods; this means that the zero phase changes position with respect to the tag when the sampling frequency changes.

R/W 0x n001

CH n Online LO frequency (online register – read only) n Є [1 , 4] R 0x n003

CH n LO measured frequency Read only. Coded in the 24 LSB’s [b23..b0]Number of 80 MHz periods measured within the window specified in the “LO frequency measure Window“

R 0x n005

CH n LO frequency measure window Number of LO periods within which the 80 MHz counter will count. Coded in the 16 LSBs [b15..b0]

R/W 0x n007

CH n Preset CIC parameters (pre-load asynchronous register – waiting for a double-tag synchronous load)

b32 – b35 (4 bits; MSB = b35) = Decimation ratio R (max value = 15) Values 0 and 1 imply no decimation

b40 – b47 (8 bits; MSB = b47) = Number of delay M (max value = 255) in the differentiator. Value 0 implies no differentiation.

b48 – b50 (3 bits; MSB = b50) = Number of stages N (max value = 3) Value 0 implies no Integral and no differential filtering, but still decimation.

b52 –b57 (6 bits; MSB = b57) = normalization attenuation: A (0->36). The 18 bit word from the mixer will be attenuated by 2^A before being processed in the CIC. To maximize the signal-to-noise ratio, the typical value should be:

A = N.log2 (R.M) – 2When the CIC is bypassed, N should be set to 0 so that the 18 bit MSB

corresponds to the register MSB (b63).

R/W 0x n009

CH n Online CIC parameters (online register – read only)

b32 – b35 (4 bits; MSB = b35) = Decimation ratio R (max value = 15)b40 – b47 (8 bits; MSB = b47) = Number of delay in comb M (max value = 255)

R 0x n00B

51

b48 – b50 (3 bits; MSB = b50) = Number of stages N (max value = 3)b52 –b57 (6 bits; MSB = b57) = normalization attenuation

CH n Mode of operation

b32: enable CIC filterb33: enable FIR filter N/Ab34: Turn channel onb37: auto-range ADC (when the input signal has a low amplitude, the

analogue gain of the ADC input stage is multiplied by 2^4. The digital gain at the end of the processing is divided by 2^4 for an unchanged overall gain.

Not yet implemented, needs a new generation ADC circuit.b38: ADC analogue gain high/digital gain low (active when bit 37 is

not set). This bit should be activated when the input signal is expected to be low.

Not yet implemented, needs a new generation ADC circuit.b39: reset phase accumulator at each tagb43: Allow change of FLO without double tag. The new value of FLO will be obtained after a ramp duration expressed in the “LO Increment” register

R/W 0x n00D

CH n LO Freq Increment

b63: 231

b62: 230

etc…b32: 20

The LO frequency value will increase (resp. decrease) by the amount:ΔfLO = (F_LO_INCR word. FRF CLOCK) / 232 at every RF Clock period

The ramping is only achieved when b43 of the CH n mode of operation register is set (allow change of LO frequency without double tag).The slope sign is automatically set by the hardware taking into account the new LO frequency to be obtained. There is no need to check if the frequency increment brings exactly to the exact value of the new LO frequency. The hardware takes care of this.If the register value is zero, the F_LO value will change immediately without ramping. If a change of F_LO occurs while the ramping is not finished, the LO frequency will just start ramping to the new programmed value

R/W 0x n00F

CH n Next double-tag load registerThis register needs to be set before any change can occur in the rf synchronous registers

b32: load HLO b33: load CIC parametersb34: load FIR coefficients N/Ab36: load LO Phase accumulator offsetAll these actions reset the LO phase accumulator

R/W 0x n011

CH n I (in phase) outRead Only. Should be followed by a read Q requestThe very next I value following the read request and sampled on the

R 0x n013

52

DDC will be output. The Q value corresponding to the same time sample will be memorized and output on the next read “Q” sequence. The read sequence is completed only when both I and Q have been read.

CH n Q (in quadrature phase) out R 0x n015

CH n Measured Amplitude squared = I2 + Q2

Read Only. Should be followed by a “Measured Frequency times amplitude squared” read requestThe very next “Measured Amplitude squared” value following the read request and sampled on the DDC will be output. The “Measured Frequency times amplitude squared” value corresponding to the same time sample will be memorized and output on its next read sequence. The read sequence is completed only when both registers have been read.Binary value [b63 – b44], Full scale when both I and Q are in Full scale. (Actually, in the unlikely case where both I and Q = minus FS there is an overflow of 1 bit).

R 0x n017

CH n Measured Frequency times amplitude squaredRead OnlyAlways positive 2’s complement value (MSB =b63 = 0), the 17 following bits [b62 – b46] contain the information, [b45 – 32] are set to zero

R 0x n019

CH n LO phase offset preload (pre-load asynchronous register – waiting for a double-tag synchronous load) n Є [1 , 4]Value loaded synchronously with the double tag when b36 of the “CHn next tag load” register is set.The 32 bit value [b63 – b32] (b63 being the MSB) is added (non signed addition) to the 32 bit phase accumulator value. Use the 2’s complement for negative phase offsets => the value “FFFF FFFF” will create a -1 LSB phase offset (= -360o/232)

R/W 0x n01B

CH n LO phase offset Online (online register – read only) n Є [1 , 4] R 0x n01D

CH n Frequency discriminator filter poleNot implemented due to the limited resources of the EP1S20F484C5 FPGA

R/W 0x n01F

CH n FIR parameters (20)Not implemented due to the limited resources of the EP1S20F484C5 FPGA

R/W From 0x n021To 0x n033

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sl-note-98-099 md · web viewa novel rf beam control architecture has been successfully tested in...

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