single-phase transformerless photovoltaic inverter with

0885-8993 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2018.2886054, IEEETransactions on Power Electronics

Abstract— In low power applications of photovoltaic (PV)

systems, the transformerless grid-connected inverters have been preferred to increase the efficiency and reduce the cost, size and power losses when they are compared to the ones with the transformer. A transformerless single-phase inverter topology with a single DC link capacitor for the grid-connected PV systems is proposed in this paper. The proposed inverter has been simulated by using a cooperation process of the MATLAB and SPICE package programs and it has been implemented for experimental verification. The proposed inverter reduces the high-frequency common mode leakage current caused by parasitic capacitances of PV panels, while it is controlled with the unipolar sinusoidal pulse width modulation (SPWM). Also, the results show that the common mode voltage remains constant. The efficiency of the proposed inverter has been compared to that of the most common topologies having the DC link decoupling during the zero voltage states. This paper is accompanied by a video file demonstrating the power loss distribution in the inverter.

Index Terms—Photovoltaic (PV) system, transformerless

inverter, unipolar sinusoidal pulse width modulation (SPWM), common mode voltage, leakage current

I. INTRODUCTION

HOTOVOLTAIC systems among the other renewable energy sources have regularly increased in electrical energy production all around the world in the last decade.

The electrical power generation with the solar photovoltaic system has a rapid growth rate since its installation cost decreases and it becomes a cost competitive energy conversion process among the sustainable energy sources. A total of 99.1 GW of grid-connected solar power was installed in 2017 and it is exponentially increasing to be one terawatt installed by 2022 [1]. The PV systems have taken a significant role in satisfying the electrical power demand of residential and commercial applications [2]. The PV inverters can be connected to the grid directly when the grid codes and regulations accepted by the countries are satisfied. The ground leakage current limitation is among the grid specifications and safety regulations [3,4]. The

Authors would like to thank Turkish Scientific Research Council (TÜBİTAK) for founding this research at the Department of Electrical and Electronics Engineering at Dokuz Eylul University under the contract of research project no: 117E776 (Design and modelling of a high energy efficient solar energy conversion system).

The authors are with the Department of Electrical and Electronics Engineering, Dokuz Eylul University, Kaynaklar Kampusu, Buca, İzmir, Turkey (e-mail: [email protected]; [email protected]; [email protected]; [email protected]).

usage of leakage current protection devices is inevitable, because of the existence of the parasitic capacitance between the PV panel and ground [5]. The ground leakage current which circulates through PV parasitic capacitor can be suppressed in the inverter during the design stage by working either on the hardware modifications or on the software of modulation techniques. Its effective value (rms) should be kept less than 300 mA while any sudden current change is also expected to be less than the recommended values as indicated in [3, 6], otherwise, it triggers the leakage current protection device. The alternative solution is to use an isolation transformer either in high-frequency operation zone in the power electronic circuit or in the grid side at low frequency (50 Hz or 60 Hz). The power transformer increases the volume, weight, and cost while it reduces the efficiency of the system [7-9].

In the PV string applications, the inverters are commonly chosen in the voltage source category [2] and the conventional bridge structures have been modified to eliminate leakage current while keeping the power conversion efficiency as high as possible. The half bridge (HB) inverter has a constant common mode voltage with its basic configuration [10]. However, it generates a lower effective AC voltage level than that of the full bridge (FB) structure fed from the same constant DC voltage. Therefore, the HB structures require extra DC to DC converters or large PV strings due to the double input voltage requirement [11]. The leakage current can be suppressed at the FB structure by decoupling the PV panel from the grid side at zero voltage level of the inverter output voltage without using an isolation transformer. The structure of the single-phase topology and its modulation technique affect the amplitude of the fluctuation on common mode voltage [12]. The constant common-mode voltage can be obtained by using the single-phase bipolar switching techniques on the FB inverters because the zero voltage instant does not occur during the transition from negative to positive level or vice versa. However, their efficiencies are lower with respect to the unipolar switched FB inverters. On the other hand, the unipolar switching technique provides higher efficiency but it creates the leakage ground current. There are several topologies proposed with the unipolar voltage output and the mitigated leakage current under 300 mA [13-15]. These circuits are usually classified in two different categories based on the decoupling techniques which are applied either on the DC link side or on the AC grid side of the inverter for isolating the PV panel from the grid side.

Eyup Akpınar, Senior Member, IEEE, Abdül Balıkcı, Enes Durbaba, Buket Turan Azizoğlu, Member, IEEE

Single-Phase Transformerless Photovoltaic Inverter with Suppressing Resonance in

Improved H6

P



The PV inverters with two DC link capacitors need software solutions or some extra components to ensure that the capacitor voltages are balanced [16]. The difference between the capacitors instantaneous voltage values increases the ground current level. The hardware solutions to the problem can cause more losses or a complicated control algorithm in the software. The DC link capacitors are the most vulnerable components of the inverters and their lifetime should be considered for the whole system reliability and life span [17]. The failure rate of the capacitors is observed as 30 percent among the main components in the power electronic systems [18].

The improved H6 inverter in [19] and another single-phase inverter in [20] have the single DC link decoupling capacitor in order to increase the circuit reliability. The junction capacitances of the switching devices are taken into account for controlling the leakage current of the PV panel capacitor in the improved H6 inverter. Their values change device to device in the range of picofarads or nanofarads. Therefore, their effectiveness on the circuit operation is highly dependent on the distributed stray capacitors in the electrical network. The ground leakage current may not be sufficiently suppressed because of the possible resonance with the distributed stray inductances in the network [19, 21]. In this paper, a new circuit configuration for the inverter having a single DC link capacitor and seven IGBTs is proposed. The common mode voltage is kept at a constant value and the ground leakage current is suppressed. The efficiency of the inverters is usually given by using the manufacturer data of solid-state devices, testing the converter circuit or estimating it with the help of the simulation package programs [22]. The efficiencies of the proposed converter and two different topologies in the same decoupling classification are compared experimentally in this paper.

II. COMMON TOPOLOGIES FOR DECOUPLING THE DC LINK

The most common topologies for decoupling the PV panel from the grid are called as H5, H6, optimized H5 and improved H6 inverters given in Fig. 1. The H5 topology which has one DC link capacitor is proposed by adding one more switching device to the conventional H bridge structure [20]. In this topology, the common mode voltage is floating during the zero voltage level (i.e., freewheeling period) of the unipolar switching [23] and it assures a good performance only at unity power factor operation and this limitation reduces the wide spread use of it [13, 24].

The power loss of H6 topology is lower than that of H5 topology [14]. H6 topology with six switches and two diodes has a dedicated switching algorithm that is not compatible with the complementary PWM switching technique [12]. This causes a significant limitation on the use of PWM ports built in the digital signal processors. The reverse recovery current circulates in the diode during switching transition hence its switching characteristics should be compatible with the counterpart IGBTs.

The optimized H5 topology has higher efficiency than H5 and H6 topologies [14, 22]. Although H6 and optimized H5 topologies hold the common mode voltage constant, they require the voltage balancing across two DC link capacitors.

In improved H6 topology, the junction capacitances of the IGBTs are used effectively for holding the common mode voltage constant [19] as seen in Fig. 1(d). However, the capacitors and the inductances in the circuit create an active path for resonance current and the common mode voltage oscillates around the resonance frequency [19]. Although the common mode voltage oscillation is prominently caused by switches’ junction capacitors, it should be noted that the junction capacitances are very small and the operation of the circuit can also be affected from the distributed stray capacitances in the printed circuit board [25].

Fig.1. Transformerless grid-connected PV inverters a) H6 inverter b) H5 inverter c) Optimized H5 (oH5) inverter d) Improved H6 inverter



III. PROPOSED INVERTER TOPOLOGY AND OPERATION MODES

The proposed topology decouples DC link during zero voltage levels and keeps the common mode voltage constant with the standard unipolar switching. The effects of the IGBTs’ junction capacitors used in the improved H6 operation are removed by adding one more solid state switch S7 into the circuit. Two turn-off snubber circuits are added in parallel to the switches S5 and S6 in order for sharing the input DC voltage between the snubber capacitors.

A. Structure of the proposed topology,

The proposed topology consists of seven IGBTs as shown in Fig. 2 and it is named as active clamped snubber based inverter in this paper. The active clamping IGBT (S7) is operated only during the freewheeling instant and a small amount of snubber current( 𝑖𝑖𝑠𝑠(𝑡𝑡) ) flows through its collector when it is turned on to hold the common mode voltage constant. The collector emitter voltage of the S7 switch (VCE,S7 ) is equal to the DC link voltage (Vdc) when it is switched off. The capacitor of the snubber circuit (Cs) is charged to the half of DC link voltage level and it retains the common mode voltage constant as long as S7 is turned on. The snubber circuits can also reduce the

switching losses of S5 and S6 [26]. The PV panel capacitor (Cp) is used between the negative terminal of DC input voltage and the grounded neutral point of the grid.

Fig. 2. Proposed inverter topology (active clamped snubber based inverter)

B. Operation modes of the proposed topology

There are four modes of operation over one period of the grid voltage. The active current path in the inverter during the positive half cycle is seen in Fig. 3(a).

Fig. 3. Four operation modes of proposed inverter with grid connection. a) active current path for positive half cycle b) freewheeling modes for positive half cycle

c) active current path for negative half cycle d) freewheeling modes for negative half cycle



The common mode voltage in power converter systems is defined as the average of the voltage of each line with respect to the local common or ground. In a two wire-system, a common-mode voltage appears on both lines in phase with the equal amplitudes. Here, the common mode voltage of the inverter ( Vcm ) is written in terms of VA0 and VB0 as follows by selecting the local common point (0) on the negative terminal of DC link voltage. VA0 is the voltage difference between the inverter terminal A and the local common point (0). VB0 is the voltage difference between the inverter terminal B and the local common point (0).

Vcm= (VA0+VB0)

2 (1)

The differential mode voltage at the inverter output terminals ( Vdm ) can be written in terms of VA0 and VB0 as follows;

Vdm=VA0-VB0 (2)

The gate signals of the IGBTs used in the proposed inverter for the sinusoidal pulse width modulation are given in Fig 4. It is clearly seen that S1, S2, S3, and S4 are operated with the unipolar switching scheme while S5 and S6 work simultaneously as the complement of S7. The common mode voltage can be analyzed in two intervals corresponding to the positive half cycle and the negative half cycle of the reference sinusoidal signal.

During the positive half cycle of the reference sinusoidal signal, S1 is continuously conducting, whereas S3 is at off position. These two switches commutate alternately. S4, S5, and S6 complementarily commutates S2 at the frequency (switching frequency) of carrier wave. In this period, the common mode voltage is;

Vcm= (Vdc+0)

2= Vdc

2 (3)

In order to obtain the freewheeling path, S4 is turned off and S2 is turned on during the zero level of inverter output voltage. Also, S5 and S6 switches are turned off and active clamping switch S7 turns on simultaneously to keep the common mode voltage constant. During the conduction of the switch S7, the current flows through both snubbers as seen in Fig. 3(b) and each snubber capacitor charges to the half of the DC link voltage level. The common mode voltage is retained at the previous value as follows;

Vcm=Vdc

2 +Vdc2

2= Vdc

2 (4)

During the negative half cycle of the reference sinusoidal

signal, the active current path is depicted in Fig. 3(c). In this case, while S2 is always conducting, S4 is turned off. S2 and S4 are always commutating alternately. The common mode voltage is given in (5) during this mode of operation.

Vcm= (0+Vdc)

2= Vdc

2 (5)

In the freewheeling mode during the negative half cycle, the constant common mode voltage is obtained as shown in Fig. 3(d). The snubber capacitor voltages are equal to the half of the DC link voltage since the capacitance values are same. The common mode voltage is given below;

Vcm=Vdc

2 +Vdc2

2= Vdc

2 (6)

The common mode voltage in all operation modes is constant

during the unipolar switching and it is equal to the half of the DC link voltage (Vcm= Vdc

2 ). The snubber circuit ensures that the circuit remains at a constant common mode voltage without fluctuations during the freewheeling periods. The conduction of the switch S7 guarantees the voltage of the snubber circuit shared equally at the half of the DC voltage level. If the switch S7 was not operated, the snubber capacitors would not be charged since there was no current flowing through the snubber circuit at the freewheeling instant.

Fig. 4. Gate signals of the proposed inverter for the unipolar operation

C. Control of Inverter

The control block diagram of the inverter is given in Fig. 5. The real and reactive powers are calculated at the grid terminals by using the orthogonal components of the grid voltage ( Vgα 𝑎𝑎𝑎𝑎𝑎𝑎 Vg𝛽𝛽 ) and the grid current (igα 𝑎𝑎𝑎𝑎𝑎𝑎 igβ ). The phase lag orthogonal components (Vgβ 𝑎𝑎𝑎𝑎𝑎𝑎 igβ) are obtained from the grid voltage (Vg = Vgα) and the grid current (ig = igα) in the software loaded on the digital signal processing unit. The instantaneous values of real power (Pcal) and reactive power (Qcal) are computed by using (10) and (11).



Pcal=Vgαigα+Vgβigβ/2 (10)

Qcal=Vg𝛽𝛽igα-Vg𝛼𝛼igβ/2 (11)

These calculated values are compared to the reference values (Pref 𝑎𝑎𝑎𝑎𝑎𝑎 Qref ) and the errors are passed through the proportional integral controllers Gp1(s) and Gp2(s). The reference grid current (ig*) is obtained from (12) and it is compared to the actual grid current measured at the inverter output. The error is the input to the proportional resonant (PR) controller (G(s)) designed at the grid frequency [27-29]. The output of the proportional resonant controller is used as the reference signal for the modulation.

ig*= Pref-PcalGp1(s)Vgα+ Qref-QcalGp2(s)Vgβ / Vgα

2 +Vgβ2 (12)

Gp1(s)=kp1+ki11s (13)

where kp1 and ki1 are the proportional and the integral coefficients of Gp1(s) Gp2(s)=kp2+ki2

1s (14)

where kp2 and ki2 are the proportional and the integral coefficients of Gp2(s) G(s)=kp+ki

ss2+wf

2 (15)

where kp and ki are the proportional and the integral coefficients of G(s)

The gate signals are generated due to the comparison of the reference signal obtained from the output of the proportional resonant controller and the carrier signal. A dead time of 1.3 µs is used between the S7 and S6 (and S5) to avoid the DC link short circuit.

Fig.5. The controller block diagram for the inverter

D. Snubber Circuit Analysis

Two R-C snubber circuits are used in parallel to the switches S5 and S6 in order to share the DC link voltage across the two snubber capacitors when the switches S5 and S6 are simultaneously turned off and the switch S7 is turned on. The effective circuit for the snubber analysis is given in Fig. 6. The snubber resistance ( Rs ) and the snubber capacitor ( Cs ) create a network with the stray inductance Ls on the DC link side [30]. The differential equations describing the circuit operation are

(𝐷𝐷2 + 2𝜉𝜉𝜔𝜔0𝐷𝐷 + 𝜔𝜔0

2)𝑖𝑖𝑠𝑠 = 0 (16)

(𝑅𝑅𝑠𝑠𝐶𝐶𝑠𝑠𝐷𝐷 + 1)𝑖𝑖𝑠𝑠 = 𝐶𝐶𝑠𝑠𝐷𝐷𝑒𝑒𝑠𝑠 (17)

where 𝐷𝐷 = 𝑎𝑎 𝑎𝑎𝑡𝑡⁄ and es is the snubber voltage shown in Fig.6.

The damping coefficient, 𝜉𝜉 = 𝑅𝑅𝑠𝑠2

𝐶𝐶𝑠𝑠𝐿𝐿𝑠𝑠

(18)

The resonance frequency, 𝜔𝜔0 = 1 𝐿𝐿𝑠𝑠𝐶𝐶𝑠𝑠⁄ The snubber current 𝑖𝑖𝑠𝑠(𝑡𝑡) for the underdamped (0 < 𝜉𝜉 < 1) case is 𝑖𝑖𝑠𝑠(𝑡𝑡) = 𝑒𝑒𝑠𝑠

𝑅𝑅𝑠𝑠

2𝜉𝜉(1−𝜉𝜉2)

𝑒𝑒𝑒𝑒𝑒𝑒(−𝜉𝜉𝜔𝜔0𝑡𝑡) 𝑠𝑠𝑖𝑖𝑎𝑎(𝜔𝜔𝑡𝑡) (19)

where 𝜔𝜔 = 𝜔𝜔0(1 − 𝜉𝜉2)

The snubber current waveforms are recorded at two different snubber resistor values which are Rs = 1 ohm and Rs = 5 ohms, while the snubber capacitor Cs is equal to 22 nF, when the inverter is operated at the rated load (1 kW output power). The underdamped operation is observed from the snubber current waveform recorded, when these snubber parameters are used. The mathematical expression of the snubber current waveform is given in (19). The stray inductance Ls is computed as 0.7 µH from the resonance frequency (𝜔𝜔0) of the response during the underdamped case. Then the snubber resistance is fixed to the value of 10 ohms in order to obtain the critically damped response which causes the minimum effect on the leakage current icm. The mathematical expression of the snubber current for the critically damped response is given in (20). The measured results from the snubber circuit designed at critical damped case are given in Fig. 7 during the turn-off interval of S5 and S6. The snubber current has zero initial value and it has two critically damped waves in every turn-off interval. The first surge-current waveform takes place when S5 and S6 are turned off simultaneously. The second surge-current waveform appears when the S7 is turned on after the dead time of 1.3 µs between the S7 and S6 is elapsed. The snubber current 𝑖𝑖𝑠𝑠(𝑡𝑡) for the critically damped (𝜉𝜉 = 1) case is

𝑖𝑖𝑠𝑠(𝑡𝑡) = 𝑒𝑒−𝜔𝜔0𝑡𝑡(𝐴𝐴1 + 𝐴𝐴2𝑡𝑡) (20)

The initial value of the snubber current 𝑖𝑖𝑠𝑠(0) is equal to zero, therefore 𝐴𝐴1 = 0 and 𝐴𝐴2 = 𝑑𝑑𝑖𝑖𝑠𝑠(𝑡𝑡)

𝑑𝑑𝑡𝑡𝑡𝑡=0+

= 𝑒𝑒𝑠𝑠𝐿𝐿𝑠𝑠

. The power absorbed by the snubber resistor is determined from the following equation:



𝑃𝑃𝑅𝑅𝑠𝑠 = 𝐶𝐶𝑠𝑠 𝑉𝑉𝑑𝑑𝑑𝑑22𝑓𝑓𝑠𝑠𝑠𝑠 (21)

where 𝑓𝑓𝑠𝑠𝑠𝑠 is the switching frequency of the IGBTs.

Fig.6. Effective circuit for snubber analysis

Fig. 7. Measured results from the snubber circuit during the turn-off interval of S5 and S6: a) snubber voltage of S6, b) snubber current of S6, c) snubber voltage of S5 d) collector emitter voltage of S7.

Fig. 8 shows the measured results from the snubber circuit during the turn on interval of S5 and S6. The variation of collector-emitter voltage (snubber voltage) of S6 is given in Fig. 8(a) during the turn-on interval. The dead time between S7 and S6 is indicated in Fig. 8(d). The collector emitter voltage Vce,S7 and the emitter current of S7 is zero just before the turn off process is started for S7 since the DC link voltage is shared equally by the S5 and S6. The zero level of collector emitter voltage of S7 is retained until the S5 and S6 are turned on as it is clearly recognized from Fig. 8(c). The switches S5 and S6 are turned on when the dead time of 1.3 µs is elapsed after the S7 is turned off. Then the collector emitter voltage of S7 ( Vce,S7 ) changes to the value of voltage difference between the DC link voltage (V dc ) and the voltage drops on the snubber circuits ( 2es ). Fig. 8(b) shows the snubber current ( is ) when the snubber capacitor discharges through the snubber resistor and S6. The energy stored on the capacitor (21) is mostly transferred to the resistor during the on time of the device. The time constant (Rs Cs) also determines how much time is required to discharge the snubber capacitor. A time interval of three to five time constant is required for capacitor discharge.

Fig. 8. Measured results from the snubber circuit during the turn-on interval of S5 and S6: a) snubber voltage of S6, b) snubber current of S6, c) collector emitter voltage of S7 d) emitter current of S7.



IV. COMMON MODE VOLTAGE AND LEAKAGE CURRENT The equivalent circuit of the grid-connected inverter can be

obtained by using the common mode voltage of the inverter, the differential mode voltage of the inverter, the common mode voltage of the grid ( Vgcm ), the differential mode voltage of the grid (Vgdm ), the switching inductances (L1 and L2) and the PV panel parasitic capacitance (Cp) as it is given in Fig. 9. The common mode voltage of the grid appears on the both lines in phase with the equal amplitudes. This voltage with respect to the point n defined in Fig. 2 is given below.

Vgcm = Vg /2 (22)

The differential mode voltage is

Vgdm=Vg (23)

This circuit has the PV panel parasitic capacitance Cp between the ground of grid (point n) and the local common point (0) selected on the negative terminal of DC link voltage as shown in Fig. 2.

Fig. 9. Equivalent circuit for grid-connected inverter

The voltage across the parasitic capacitance (V0n) can be obtained by applying Thevenin theorem and superposition between the points a and b depicted on the circuit in Fig. 9. The single loop equation of the circuit is written in (24) by using the Kirchhoff’s voltage law.

V0n=-Vcm- Vdm

2 L2-L1

L1+L2+

Vgdm

2 L2-L1

L1+L2+Vgcm+ L1L2

L1+L2 dicm

dt (24)

The grid common mode voltage (Vgcm) and the grid differential mode voltage (Vgdm) in (24) are at the power frequency (50 Hz). The grid common-mode voltage mostly drops across the PV parasitic capacitor which has a high impedance at the low grid frequency. When the inverter switching inductances (L1 and L2) are selected equally, the differential mode voltages of the grid and the inverter (Vgdm and Vdm) do not have any effect on the leakage current (icm). The inverter common-mode voltage (Vcm) which consists of the high-frequency harmonic components creates the effective circulating current (leakage current) through the PV parasitic capacitor. The switching inductance has a significant effect on the circulating leakage current magnitude because it shows a high impedance at the frequency of the inverter common-mode voltage (Vcm).

V. SIMULATION AND EXPERIMENTAL RESULTS OF THE PROPOSED INVERTER

A prototype of the proposed inverter is built in the laboratory. The common mode voltage, the leakage ground current and the efficiency under the standard unipolar switching condition are investigated. This PV inverter with 1 kW of power capacity is connected to the grid and fed by a constant DC voltage source. The system parameters used in the analysis of the proposed topology are given in Table I. The total harmonic distortion of the grid current is analyzed by using Fluke 434 power quality analyzer. The average input power to the inverter and output power supplied to the grid are computed by using (25) and (26) and recorded precisely (10 GS/s) in the software facility of Lecroy WaveRunner 604ZI oscilloscope. The experimental setup of the system is given in Fig. 10.

Pin= 1

T∫ Vdc(t)·idc(t)dtT0 (25)

Pout=1T∫ (VA0(t)-VB0(t)) ∙ ig(t) dtT

0 (26)

The simulation and experimental results of the proposed inverter topology are given in Fig. 11. The entire system including the dead times, the current and voltage controllers have been simulated in the MATLAB. The grid current is kept sinusoidal at unity power factor under the proportional resonant current controller. The gate signals of the seven IGBTs are generated from the MATLAB simulation and transferred to the SPICE for the analysis of switching transients. The data of gate signals is extracted to the workspace in the format of “array”. Then it is stored in the text files for each IGBT. The source components located in the SPICE library execute the program by importing the seven text files corresponding to seven IGBTs. The V PWL_F_RE_FOREVER is one of the components in the source library and it calls the text files during the analysis of circuit at steady state operation. Fig. 11(a) shows the inverter output voltage and the grid current ( ig ). The grid current measurements are taken in the opposite direction to the reference direction indicated in Fig. 2 hence the grid current is

TABLE I PARAMETERS OF GRID CONNECTED INVERTER

Symbol Parameter Value

Vg Grid voltage 110 V RMS f Grid frequency 50 Hz. Vdc DC Bus voltage 200 V

Cdc DC Bus capacitor 10000 µF L1 Line filter inductance 3,6 mH Cs Snubber capacitor 22 nF Rs Snubber resistor 10 Ω S1-S7 IGBT SKM75GB123D fsw Switching frequency 10 kHz. Cp PV parasitic capacitance 100 nF P kp1 kp2 kp

Rated power Proportional gain of Gp1(s) Proportional gain of Gp2(s) Proportional gain of G(s)

1 kW 0.0005 0.0005 0.5

ki1 ki2 ki

𝑤𝑤𝑓𝑓

Integral gain of Gp1(s) Integral gain of Gp2(s) Integral gain of G(s) Grid frequency in rad/sec

0.05 0.05 0.005 2πf



multiplied by the minus sign in all measured results in order to protect consistency. The simulation result of the grid current is multiplied by the gain of 20 in order for keeping this waveform clearly visible with the voltage in the same screen. The grid current is in phase with the grid voltage, therefore the inverter output voltage has a phase difference with respect to the grid current at the amount of load (power) angle. The total harmonic distortion of this current is measured to be % 1.9 by using power quality analyzer. Fig. 11 (b) and Fig. 11(c) are the inverter terminal voltages (points A and B ) with respect to the local common point (0) selected on the negative terminal of DC link as shown in Fig. 2. These two recorded voltage waveforms (VA0 and VB0 ) are used in the signal processing unit of Lecroy WaveRunner 604ZI oscilloscope to display the common mode voltage of the inverter defined in (1). Fig. 11(d) shows the common mode voltage which is the half of the DC link voltage.

When the simulation and the experimental results in Fig. 11 are compared, it is clearly seen that the experimental waveforms have some more voltage spikes. The experimental results of the proposed circuit are zoomed in during two switching period in Fig. 12 in order to focus on the effect of switching transients on common mode voltage. The three-level inverter output voltage and the current supplied to the grid are shown in Fig. 12(a). The inverter output voltage has only turn on and turn off spikes of the IGBTs controlled by the pulse width modulated technique. Their effect on the leakage current can be suppressed by the switching inductance ( L1 // L2 ) in (24). The inverter terminal voltages with respect to the negative rail of the DC link voltage (VA0, VB0) and the common mode

voltage which is the half of (VA0+VB0), are shown in Fig. 12(b), Fig. 12(c) and Fig. 12(d), respectively. The proposed inverter generates a constant common mode voltage during the switching periods.

Fig. 10. Experimental setup for PV inverter in laboratory

Fig. 11. Simulation (on the left) and experimental (on the right) results of proposed converter a) Inverter output voltage at the grid side and the grid current b) VA0

c) VB0 d) (2xCommon mode voltage) VA0+VB0.



Fig. 12. Experimental results of proposed converter during two switching periods a) Inverter output voltage and the grid current b) VA0 c) VB0 d) (2xCommon mode voltage) VA0+VB0 .

Fig 13. Experimental results of proposed converter during one switching period. when S7 is not operated a) Inverter output voltage b) VA0 and VB0 c) (2xCommon mode voltage) VA0+VB0 d) Common mode current icm

When the switch S7 is left open during the entire operational modes, the proposed inverter has the same electrical network used for the improved H6 topology except the snubber circuits. The common mode voltage is not kept constant and causes the leakage current circulation. The inverter terminal voltages (VA0, VB0), the common mode voltage, and the leakage current (common-mode current) waveforms for this operation are shown in Fig. 13. A high-frequency resonance path appears during the freewheeling mode when the switch S7 is removed from the circuit. The stray inductances of the circuit (Ls), the switching inductances (L1 and L2), the junction capacitors of switching devices and the stray capacitor of the PV (Cp) are creating a resonance circuit. Hence, the oscillating leakage current during every switching interval circulates in the PV panel stray capacitor. The instantaneous value of the leakage current increases up to 400 mA as shown in Fig. 13(d). Although the rms value of this current is measured around 100 mA during the test, it may go to some higher values due to the existence of uncontrollable resonance circuit parameters in the network.

The experimental results of the inverter output voltage, the inverter terminal voltages with respect to the negative terminal of DC link, the inverter common mode voltage and the leakage current are given in Fig. 14 for the improved H6 and the proposed inverter topologies. The peak value of the leakage current for the improved H6 is around 200 mA and for the proposed inverter is around 100 mA. The safety limit is 300mA rms according to the standard VDE0126-1-1. The measured rms value of the leakage current of improved H6 inverter is 19.53 mA while that value of the propsed inverter is 32.54 mA in Fig. 14(d) calculated by Lecroy Waverunner 604ZI oscilloscope.

The transient response of the proposed inverter is investigated by changing the active power reference from 500 W to 1000 W during the operation. The time at which the active power is changed is marked on the waveform of the grid current in Fig. 15(a). The rms value of the grid current changes from 4.35 A to 8.7 A as the response to the active power change. The unity power factor operation is retained during the both reference values of active power. The common mode voltage is kept at the same envelope during the transient operation. There is no any significant change in the leakage current during the transients.

Fig. 16 shows the measured results of proposed inverter under the inductive loading. The inverter is operated with the real power and reactive power supplied to the grid. The reference values of the real power and reactive power are set to 500 W and 500 VAR, respectively. The inverter output voltage, the grid current, the DC link current idc (labelled in Fig. 2 to show the reference direction) and the leakage current are recorded. The results show that the proposed inverter work proporly even if the power factor is not equal to unity. The negative values of DC link current shows that the instantaneous value of the input power goes to the negative values because of the reactive power supplied to the grid. The negative current also shows that the antiparallel diodes of the IGBTs (labelled as S5 and S6 in this paper) are forward biased and carrying this current.



Fig. 14. Experimental waveforms of improved H6 (on the left) and proposed inverter (on the right) a) The inverter output voltage b) VA0, VB0 c) VA0+VB0 (2xCommon mode voltage) d) The leakage current icm.

Fig. 15. Experimental results of proposed inverter during the transients: a) The grid current, b) the inverter terminal voltages (VA0 and VB0), c) VA0+VB0 (2xCommon mode voltage) d) The leakage current icm .

Fig. 16. Measured results of proposed inverter under the real power (500 W) and the reactive power (500 VAR) supplied to the grid: a) The inverter output voltage, b) The grid current, c) The DC link current, d) The leakage current



VI. COMPARISON OF PROPOSED INVERTER WITH EXISTING TOPOLOGIES

The advantages and disadvantages of the proposed topology are compared with H6, H5, optimized H5 and improved H6 as given in Table II. Although H6 and optimized H5 topologies have constant common mode voltages, they require capacitor voltage balancing [31, 32]. Despite the fact that H5 and improved H6 topologies do not require voltage balancing due to the one capacitor in their structure, the common mode voltages of them are floating. The common mode voltage is maintained constant in the proposed inverter having one DC link capacitor. In the proposed topology, the resonance current path does not occur and a standard unipolar switching can be applied. The proposed inverter consists of one switch more (S7) when it is compared to improved H6 topology, but that IGBT does not need antiparallel diode since the current is unidirectional in the branch that S7 is located, if the snubber circuit is critically damped. Even though the proposed topology has an additional switch (S7), the emitter current capacity of this IGBT can be selected according to the peak of the second surge-current circulating through the snubber circuit as it is indicated in Fig. 7(b).

The improved H6, the optimized H5 and the proposed inverter topologies are tested in the laboratory by using the same hardware circuit given in Fig. 10 under the same operating conditions and the system parameters given in Table I, since their switching logic and hardware design are compatible with the proposed inverter.

The efficiency variations of these inverter topologies with respect to the output power are given in Fig. 17. The input power is calculated from the measured values of the DC bus voltage ( dcV ) and the DC link current ( dci ) by using (25). The output power is calculated from the measured values of the voltage ( ABV ) and the current ( gi ) of the converter output by using (26). The inverter efficiency is calculated by using the output and input power computed from (25) and (26). The inverter efficiencies decrease as the real power demand is

decreasing because of the reduction of power factor due to the total harmonic distortion in the grid current.

Fig. 17. Efficiency comparison of optimized H5, improved H6 and proposed inverter The input active power (Pin), the DC link voltage (Vin, dc), the average value of DC link current (Iin dc), the rms value of grid voltage (Vg rms), the rms value of grid current (Ig rms), the power factor (pf) at the grid terminal, the apparent power at the grid terminal (Sg), the total harmonic distortion of the grid current (THD Ig) and the inverter efficiency are measured at every loading condition. During the experimental work on three inverters, it is observed that there are oscillations on the variables due to the variation of instantaneous power flow. The variation of the active power is around 10 watts when the inverters are loaded to 1 kW real power. It is causing an oscillation in efficiency around 0.1%, too. The readings are directly taken from the Lecroy WaveRunner 604ZI oscilloscope except the total harmonic distortion of the grid current read from Fluke 434 power quality analyzer. The order of having highest efficiency among the three inverters is changing in time under the same loading. The measured data on the proposed inverter, the improved H6 inverter and the optimized H5 is given in Table III, Table IV and Table V, respectively.

TABLE II COMPARISON OF TOPOLOGIES

H6 H5 Optimized H5 Improved H6 Proposed

Number of Devices 6 IGBTs 2 Diodes

2 Capacitors

5 IGBTs 1 Capacitor

6 IGBTs 2 Capacitors

6 IGBTs 1Capacaitor

7 IGBTs 1 Capacitor 2 Snubbers

Common Mode Voltage Constant Float Constant Float Constant Unipolar Switching Logic Complicated Complicated Standard Standard Standard Capacitor Voltage Balance Required Not Required Required Not Required Not Required Resonance Current Circuit Not Occurred Occurred Not Occurred Occurred Not Occurred



TABLE III PROPOSED INVERTER EFFICIENCY DATA

TABLE IV IMPROVED H6 EFFICIENCY DATA

Pin Vin_dc Iin_dc Vg_rms Ig_rms pf Sg THD Ig η (%)

229.2 201 1.139 112.83 1.909 0.955 222.2 8.3 92.5 320.3 200 1.595 112.83 2.647 0.998 296.9 6.1 92.5 428 201.3 2.127 113.36 3.57 0.993 404.9 4.7 93.8

543.4 200 2.714 113.69 4.539 0.994 516 3.9 94.3 648.3 201.8 3.211 114.26 5.382 0.983 622 3.3 94.2 751.6 200 3.757 114.2 6.295 0.989 722.9 2.8 95.1 865 201.8 4.286 114.7 7.222 0.995 826.8 2.3 95.1 971 200 4.84 115.21 8.078 0.998 927.4 2.1 95.3 1075 200 5.393 115.74 8.93 0.994 1033 1,9 95.5

TABLE V OH5 EFFICIENCY DATA

Pin Vin_dc Iin_dc Vg_rms Ig_rms pf Sg THD Ig η (%)

211.7 201 1.052 113.26 1.732 0.982 197.4 8.9 91.6 319.3 200 1.598 113.71 2.625 0.991 2988 6.2 92.7 430.3 200 2.141 113.9 3.634 0.994 413.5 4.7 95.5 517.6 200 2.58 112.7 4.42 0.996 497 3.9 95.7 624.4 200 3.11 113.7 5.277 0.994 600 3.4 95.6 756.4 201 3.745 114.9 6.346 0.989 732 3 95.6 839.1 200 4.193 114.6 7.1 0.996 813 2.7 96.5 962.6 200 4.816 115.1 8.091 0.998 927 2.5 96.1 1079 200 5.419 115.5 8.969 0.997 1033 2.2 95.4

The power losses on the switching devices are measured to supplement the efficiency calculation and identify the percentage of loss distribution on the components in the proposed inverter. The measurements in Table VI are performed at five different output power levels by recording the voltage across the component and the current circulating through it. The power losses on the snubber and the switch S5 are measured together since the snubber is soldered at a very near position to the IGBT and there is no access to the collector current of the IGBT alone. In order to calculate the total loss of inverter, the switching losses of the S1, S2, S3 and S4 in the bridge structure are considered identical. The lowest power loss and its percentage belong to the switch S7 (carrying surge-current) and its value is around 1 %, hence the efficiency of proposed inverter is near to the efficiency of improved H6. The loss on the switch S5 and its snubber circuit is slightly different than the loss on the switch S6 and its snubber. Because the PV panel stray capacitor is represented by a unique capacitor connected between the negative rail of DC link and the ground

of the grid. The leakage current through this capacitor in the circuit creates unequal power loss distribution on the S5 and S6 with their snubbers.

TABLE VI

POWER LOSS DISTRIBUTION IN PROPOSED INVERTER

Pin Vin_dc Iin_dc Vg_rms Ig_rms pf Sg THD Ig η (%) 225 202 1.114 112.4 1.86 0.973 213 8.6 92.1 319 200 1.589 113.08 2.26 0.986 302 5.8 93.4 436 201 2.16 114.1 3.62 0.982 417 4.4 93.8

569.8 201 2.83 114.7 4.748 0.997 543 3.6 94.9 664.6 200 3.309 114.3 5.564 0.991 638 3 95 764.1 201 3.783 115.32 6.335 0.996 729 2.6 95 893 202 4.421 115.6 7.398 0.993 856 2.4 95.2

981.6 200 4.903 115.3 8.209 0.991 950 2.1 95.8 1098 200 5.48 115.9 9.127 0.999 1052 1.9 95.7

Output Power Component power loss

1 kW 800 W 600 W 400 W 200 W

S2 7 5 3.8 2.6 1.3 S5 with snubber 6 4.6 3.4 3.7 1.9 S6 with snubber 8.8 7 4.8 3.5 1.7

S7 0.76 0.63 0.28 0.12 0.08 Total power loss (W) 43.6 32.2 23.7 17.7 8.88

S2 (%) 16.1% 15.5% 16% 14.7% 14.6% Total power loss of bridge (%) = (4*S2) 64.4% 62.0% 64% 58.8% 58.4%

S5 with snubber ( %) 13.8% 14.3% 14.3% 20.9% 21.4% S6 with snubber (%) 20.2% 21.7% 20.3% 19.8% 19.1%

S7 (%) 1.7% 1.96% 1.18% 0.68% 0.9%



VII. CONCLUSION

In this paper, an alternative inverter topology is proposed for the PV system connected to the single-phase grid under the safety regulation. The main principle of operation of this topology depends on decoupling the DC link from the AC side during the zero voltage levels of inverter output voltage. The proposed inverter topology has the advantages of using a single DC link capacitor, eliminating the possible resonance due to the junction capacitors and oscillations in the common mode voltage of improved H6. It keeps the common mode voltage constant while providing almost the same efficiency. The use of single DC link capacitor eliminates possible voltage unbalance with the existence of two or more capacitors and it reduces the failure probability of more electrolytic capacitors used in the system. Also, this proposed inverter topology is fully compatible with the standard unipolar switching enabling the use of PWM ports of digital signal processors.

REFERENCES

[1] European solar energy association, Available: http://www.solarpowereurope.org/home/ [2] Y. Yang , and F. Blaabjerg, “Overview of single-phase grid-connected photovoltaic systems,” Electric Power Components and Systems, vol:43, no:12, pp:1352–1363, July 2015. [3] DKE Deutsche Kommission Elektrotechnik Elektronik Informationstech-nik im DIN und VDE, DIN V VDE V 0126-1-1, 2006. [4] W. Li, Y. Gu, H. Luo, W. Cui, X. He, and C. Xia, “Topology review and derivation methodology of single-phase transformerless photovoltaic inverters for leakage current suppression,” IEEE transactions on industrial electronics, vol.62, no.7, pp.4537-4552, July 2015. [5] L. Zhang, K. Sun, Y. Xing, and M. Xing “H6 transformerless full-bridge PV grid-tied inverters,” IEEE Transactions on Power Electronics vol. 29, no. 3,pp. 1229 - 1238, March 2014. [6] D. Meneses, F. Blaabjerg, O. Garcia, and J. A. Cobos, “Review and comparison fo step-up transformerless topologies for photovoltaic ac-module application,” IEEE Transactions on Power Electronics, vol. 28, no. 6, pp. 2649–2663, Jun. 2013. [7] T. Kerekes, R. Teodorescu, P. Rodríguez, G. Vázquez, and E. Aldabas, “A new high-efficiency single-phase transformerless PV inverter topology,” IEEE Transactions On Industrial Electronics, vol. 58, no. 1, pp.184-191, Jan. 2011. [8] D. Barater, G. Buticchi, A. S. Crinto, G. Franceschini, and E. Lorenzani, “Unipolar PWM strategy for transformerless PV grid-connected converters,” IEEE transactions on energy conversion, vol.27, no. 4, pp. 835-843, December 2012. [9] B. N. Alajmi, K. H. Ahmed, G. P. Adam, and B. W. Williams, “Single-phase single-stage transformerless grid-connected PV system,” IEEE Transactions on Power Electronics, vol. 28, no. 6, pp. 2664–2676, Jun. 2013. [10] R. González, E. Gubía, J. López, and L. Marroyo, “Transformerless single-phase multilevel-based photovoltaic inverter,” IEEE Transactions on Industrial Electronics, vol. 55, no. 7, pp. 2694–2702, Jul. 2008. [11] S. B. Kjaer, K. P. John, and F. Blaabjerg, “A Review of single-phase grid-connected inverters for photovoltaic modules,” IEEE Transactions On Industry Applications, vol. 41, no. 5, September/October 2005. [12] R. González, J. López, P. Sanchis, and L. Marroyo, “Transformerless inverter for single-phase photovoltaic systems,” IEEE Transactions On Power Electronics, vol. 22, no. 2, pp. 693-697, March 2007. [13] D. Barater, E. Lorenzani, C. Concari, G. Franceschini, and G. Buticchi, “Recent advances in single-phase transformerless photovoltaic inverters,” IET Renewable Power Generation, vol.10, no..2, pp. 260-273, August 2015. [14] H. Xiao, S. Xie, Y. Chen, and R. Huang, “An optimized transformerless photovoltaic grid-connected inverter,” IEEE Transactions on Industrial Electronics, vol: 58, no: 5, pp. 1887–1895, May 2011. [15] H. F. Xiao, K. Lan, and L. Zhang, “A Quasi-unipolar SPWM full-bridge transformerless PV grid-connected inverter with constant common-mode voltage,” IEEE Transactions on Power Electronics, vol. 30, no. 6, pp. 3122-3132, June 2015.

[16] G. Buticchi, D. Barater, E Lorenzani, G. Franceschini “Digital control of actual grid-connected converters for ground leakage current reduction in pv transformerless systems,” IEEE Transactions on Industrial Informatics vol. 8, no. 3, pp. 563–572, August 2012. [17] H. Wang, and F. Blaabjerg, “Reliability of capacitors for DC-Link applications in power electronic converters—An Overview,” IEEE Transactions on Industry Applications, Vol. 50, No. 5, September/October 2014. [18] H. Wang, M. Liserre, and F. Blaabjerg, “Toward reliable power electronics: challenges, design tools, and opportunities,” IEEE Industrial Electronics Magazine, vol.7, no.2, pp. 17-26, June 2013. [19] B. Yang, W. Li, Y. Gu, W. Cui, and X. He, “Improved transformerless inverter with common-mode leakage current elimination for a photovoltaic grid-connected power system,” IEEE Transactions on Power Electronics, vol. 27, no. 2, pp. 752–762, Feb. 2012. [20] M. Victor, K. Greizer, and A. Bremicker, “Method of converting a direct current voltage from a source of direct current voltage, more specifically from a photovoltaic source of direct current voltage, into an alternating current voltage,” U.S. Patent 2005 028 6281 A1, Apr. 23, 1998. [21] A. Khan , L. Ben-Brahim, A. Gastli, and M. Benammar, “Review and simulation of leakage current in transformerless microinverters for PV applications,” Renewable and Sustainable Energy Reviews, vol. 74, pp. 1240–1256, July 2017. [22] W.J. Cha, K.T. Kim, Y.W. Cho, S.H. Lee, B.H. Kwon, “Evaluation and analysis of transformerless photovoltaic inverter topology for efficiency improvement and reduction of leakage current,” IET Power Electronics vol. 8, no. 2, pp. 255 – 267, February 2015. [23] T. K. S. Freddy, N. A. Rahim, W. P. Hew, and H. S. Che, “Comparision and analysis of the single phase transformerless grid connected pv inverters,” IEEE Transactions on Power Electronics, vol. 29, no. 10, October 2014. [24] H. Jedtberg, A. Pigazo, M. Liserre, G. Buticchi, ” Analysis of the Robustness of Transformerless PV Inverter Topologies to the Choice of Power Devices,” IEEE Transactions on Power Electronics, vol. 32, no. 7, pp. 5248-5257, July 2017. [25] Z. Ahmad, S.N. Singh “Single phase transformerless inverter topology with reduced leakage current for grid connected photovoltaic system”, Elsevier Electric Power Systems Research, vol. 154, pp. 193–203, 2018. [26] R. T. Naayagi, R. Shuttleworth, and A J. Forsyth, “Investigating the effect of snubber capacitor on high power IGBT turn-off,” 1st International Conference on Electrical Energy Systems(ICEES), India , pp. 50-55, 2011. [27] H. Hafezi, E. Akpinar, and A. Balikci, “Cascade PI controller for single phase-phase STATCOM,” 16th International Power Electronics and Motion Control Conference and Exposition (PEMC), Turkey, pp. 127-132,2014. [28] M. Islam, N. Afrin, S. Mekhilef, “Efficient Single Phase Transformerless Inverter for Grid-Tied PVG System With Reactive Power Control,” IEEE Transactions on Sustainable Energy, vol. 7, no. 3, pp. 1205-1215, July 2016. [29] A. Balikci, E. Akpinar, “A three-phase four wire static synchronous compensator with reduced number of switches for unbalanced loads,” IET Power Electronics, vol.6, no. 6, pp. 1630-1643, 2014. [30] T.C. Lim, B.W. Williams, S.J. Finney, “Active snubber energy recovery circuit for series-connected IGBTs,” IEEE Transactions on Power Electronics, vol. 26, no. 7, pp. 1879-1889, July 2011 [31] M. Shayestegana, M. Shakeria, H. Abunimaa, S.M. S. Rezaa, M. Akhtaruzzamanb, B. Baisb, S. Matb, K. Sopianb, N. Amina “An overview on prospects of new generation single-phase transformerless inverters for grid-connected photovoltaic (PV) systems,” Elsevier Renewable and Sustainable Energy, vol. 82, pp. 515–530, 2018. [32] J.Jana, H. Saha,K. D. Bhattacharya, “A review of inverter topologies for single-phase grid-connected photovoltaic systems,” Elsevier Renewable and Sustainable Energy, vol. 72, pp. 1256-1270, 2017.

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Eyup Akpınar (M’91, SM’16) obtained the BSc, MSc and PhD degrees in electrical engineering from the Middle East Technical University, Ankara, Turkey in 1981, 1984 and 1991, respectively. He was awarded a scholarship by the British Council to do part of his PhD thesis at the University of Newcastle upon Tyne in the UK. He was a Research Associate at the

Center for the Industrial Application of Electrical Power and Instrumentation at the University of New Orleans in the USA in 1991. He was a Visiting Assistant Professor in the Electrical Engineering Department at the University of New Orleans in 1993. He was awarded the Overseas Premium Paper Award by the IEE in the UK in 1993. He worked for Leviton Mfg. Co. as a senior electronics engineer in 1995. He is now working as a professor at the Department of Electrical and Electronics Engineering at the Dokuz Eylul University in İzmir in Turkey. His research area is the power electronics and electrical machines.

Abdul Balikci received the B.Sc., M.Sc, and Ph.D degrees in electrical engineering from the Dokuz Eylul University, Izmir, Turkey, in 2005, 2008 and 2014, respectively. He is working as assistant professor at the same department. He did Ph. D on the STATCOM on power electronics converters with reduced

number of switches. His current research interests include photovoltaic grid-connected inverters.

Enes Durbaba received the B.Sc. degree, in 2014 from Eskisehir Osmangazi University, Eskisehir, Izmir, and M.Sc., in 2018 from Dokuz Eylul University, Izmir, Turkey, both in electrical engineering. He is currently working toward the Ph.D. degree in electrical engineering at Dokuz Eylul University. Since December 2014, he

has been a Research Assistant in same department. His current research interests include photovoltaic grid-connected inverters.

Buket Turan Azizoglu (S’14) was born in Mersin, Turkey, in 1981. She received the B.S. degree in electrical-electronics engineering from Cukurova University, Adana, Turkey, in 2005, and the M.S. and Phd degrees in electronics engineering from Dokuz Eylul University, Izmir, Turkey, in 2007 and 2014. Since November 2008, she has been a Research Assistant in the

Department of Electrical and Electronics Engineering, Dokuz Eylul University. Her research interest includes high-frequency power converters, driver circuits, and semiconductor’s switching characteristics.

single-phase transformerless photovoltaic inverter with

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