sinano workshop, montreux, sept 2006 new generation of virtual substrates t. grasby dept. of...
TRANSCRIPT
![Page 1: SiNANO Workshop, Montreux, Sept 2006 New Generation of Virtual Substrates T. Grasby Dept. of Physics, University of Warwick](https://reader036.vdocuments.us/reader036/viewer/2022070412/5697bf881a28abf838c89222/html5/thumbnails/1.jpg)
SiNANO Workshop, Montreux, Sept 2006
New Generation of
Virtual Substrates
T. Grasby
Dept. of Physics, University of Warwick
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SiNANO Workshop, Montreux, Sept 2006
Straining Silicon with a Virtual Substrate
Si template (i.e. wafer)
New template(virtual substrate)
Si wafer
strained silicon (biaxial tensile)
Device Layer
SiGex(z)
unstrained silicon
z
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SiNANO Workshop, Montreux, Sept 2006
Why Global Strain?
Non, Non
•Uniaxial process-induced strain more effective, more flexible
•Riddled with defects
•Expensive to produce
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SiNANO Workshop, Montreux, Sept 2006
Why Global Strain?
GLOBAL STRAIN FOR EVER• Enables high (biaxial) stress levels ~ 0.9 GPa per 10% Ge concentration (y)
• Comparably high uniaxial strain via patterning
• Hybrid strain regime – global + process induced top-up
• Platform for n-sSi/p-SiGe dual channel CMOS devices
• Contender for 32-22nm node FDSOI
• Needed for R&D on strained Ge devices
• Route to Si-Ge-GaAs integration?
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SiNANO Workshop, Montreux, Sept 2006
Big Questions
is the quality there?
is there a route to production?
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SiNANO Workshop, Montreux, Sept 2006
First Generation VS (linear Ge grade) – Quality Issues
Ge conc(y) ~ 20% - good for nMOS performance
→ threading (field) dislocation density (TDD) ≥ 105 cm-2
→ pile-up densities (PUD) ~ 0.1 – 10 cm-1
→ surface roughness ~ 1 – 3 nm
involve CMP
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SiNANO Workshop, Montreux, Sept 2006
Linear Grading – State of the Art
From Y. Bogumilowicz et al., LETI and IQE
1.00E+04
1.00E+05
1.00E+06
15 20 25 30 35 40 45 50 55
0
2
4
6
8
10
12T
DD
(cm
-2)
RM
S roughness (nm
)
Germanium composition (%)
Pile-up TDD
Field TDD
RMS
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SiNANO Workshop, Montreux, Sept 2006
Linear Grading – State of the Art
From Y. Bogumilowicz et al., LETI and IQE
1.00E+04
1.00E+05
1.00E+06
15 20 25 30 35 40 45 50 55
0
2
4
6
8
10
12
TD
D (
cm-2)
RM
S roughness (nm
)
Germanium composition (%)
Pile-up TDD
Field TDD
RMS
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SiNANO Workshop, Montreux, Sept 2006
Terrace Grading
Thickness (m)
2 4 6 8
10%
20%
0
Ge
Co
nce
ntr
atio
n
Linear grade
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SiNANO Workshop, Montreux, Sept 2006
UK SiGe:C Epitaxy Centre
MBE - V90S-ANTLP-CVD - ASM Epsilon 2000E
...from Lab to Fab
SS-MBE
GS-MBE/-CVD mode
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SiNANO Workshop, Montreux, Sept 2006
Terrace Grading – development work (SS-MBE)
30% - 3 tier
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SiNANO Workshop, Montreux, Sept 2006
Terrace Graded - TEM60% 6 Tier
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SiNANO Workshop, Montreux, Sept 2006
≈105 cm-2 TDD Pile-up ≈1 cm-1
LG 30%
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SiNANO Workshop, Montreux, Sept 2006
Defect reveal in 104 cm-2 range
TDD ≈ 4 x 104 cm-2
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SiNANO Workshop, Montreux, Sept 2006
Defect Reveal in 103 cm-2 rangeLG 15%, 850ºC
Pseudo Pile-up
EPD = 6x103
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SiNANO Workshop, Montreux, Sept 2006
Hardly an etch pit in sight!
Pile-up < 0.1cm-1
TDD ≈ 3x103 cm-2
PUD = 0
TD
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SiNANO Workshop, Montreux, Sept 2006
Pile-up ≈ 5cm-1
LG 40%
TDD ≈ 106 cm-2
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SiNANO Workshop, Montreux, Sept 2006
TDD ≈ 3x105 cm-2
Pile- up = 0?
TG 40%
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SiNANO Workshop, Montreux, Sept 2006
Terrace Grading – Elimination of Pile-ups?SiPHER Analysis
TG (3 tier) up to 30% (SS-MBE)
Measurements taken by Accent Optical Technologies near wafer centres
Photoluminescence image Surface image
6x6 mm area
Pile-up density: ≤ 0.1 cm-1
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SiNANO Workshop, Montreux, Sept 2006
Terrace Grading – Elimination of Pile-ups?SiPHER Analysis
6x6 mm area
Pile-up density: ≤ 0.1 cm-1
3 tier up to 30% (SS-MBE)
Measurements taken by Accent Optical Technologies near wafer centres
Photoluminescence image Surface image
2x2 mm area
Pile-up density: 3.5 - 6 cm-1
Photoluminescence image
LGTG
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SiNANO Workshop, Montreux, Sept 2006
How does Terrace Grading do it?
LG LG
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SiNANO Workshop, Montreux, Sept 2006
What can Terrace Grading do?
LG LG
TG TGTerrace Grading ≡ Virtu
al CMP
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SiNANO Workshop, Montreux, Sept 2006
30% Terrace Graded Properties(MBE growth)
High T growth (850 790C)
y = 0.3
LG
High T
TG
High T
TDD (cm-2)
PUD (cm-1) ~ 1.0 0
RMS roughness (nms)
(20x20μm)~ 5 3.2
3.5x105 2x105
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SiNANO Workshop, Montreux, Sept 2006
30% Terrace Graded Properties(MBE growth)
High T growth + anneal
y = 0.3
LG
High T
+ anneal
TG
High T
TDD (cm-2)
PUD (cm-1) ~ 1.0 0
RMS roughness (nms)
(20x20μm)~ 5 3.2
3.5x105 2x105
+ anneal
3x105 5x103
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SiNANO Workshop, Montreux, Sept 2006
30% Terrace Graded Properties(MBE growth)
Low T growth 800 700C
y = 0.3
LG
High T(850-790°C)
TG
High T
TDD (cm-2)
PUD (cm-1) ~ 1.0 0
RMS roughness (nms)
(20x20μm)~ 5 3.2
3.5x105 2x105
+ anneal
3x105 5x103
TG
Low T
3x103
0
1.9
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SiNANO Workshop, Montreux, Sept 2006
30% TG
TDD ≈ 3x103 cm-2
PUD = 0
TD
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SiNANO Workshop, Montreux, Sept 2006
Terrace Grading – (SS-MBE)TDD for y 50%
High T growth - 850790C
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SiNANO Workshop, Montreux, Sept 2006
Transfer to CVD
• TG virtual substrates up to y = 0.2 grown on ASM Epsilon 2000E™ RP-CVD reactor using SiH4, SiCl2H2 and GeH4 precursors.
• Optimisation work - growth temperatures, growth rates, strain gradients, no. of terraces, terrace widths, throughput, etc
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SiNANO Workshop, Montreux, Sept 2006
Terrace Grading Properties (CVD) y→0.2
Sample 1065: Ge & Si fraction Job:AA1704
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
0.22
0 1000 2000 3000 4000 5000 6000 7000 8000 9000
Depth (nm)
Ge
(fra
ctio
n)
0.80
0.82
0.84
0.86
0.88
0.90
0.92
0.94
0.96
0.98
1.00
1.02
Si (
frac
tion)
Ge (fraction)
Si (fraction)
4 tiers
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SiNANO Workshop, Montreux, Sept 2006
Terrace Grading Properties (CVD) y→0.2
Reciprocal space maps (000 and 220) of 2 tier TG 20% sample taken
with XRD
AFM images showing 10x10μm area and 2x2μm area
Typical etch pit image of TG sample capped with 10nm of strained silicon. TDD ~ 105
TD
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SiNANO Workshop, Montreux, Sept 2006
Pile-Up FreeTG (2 tier) up to 17% (LPCVD)
Measurements taken by Accent Optical Technologies
6x6 mm area
Pile-up density: 0
Photoluminescence image Surface image
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SiNANO Workshop, Montreux, Sept 2006
Terrace Graded Props (CVD) y = 0.2
y = 0.2 AdvanceSisOther Expert Assessment
TDD (cm-2) ≈ 1x104
PUD (cm-1) < 0.1
Relaxation (%) > 96
RMS roughness (nms)
(20x20μm)< 1.8
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SiNANO Workshop, Montreux, Sept 2006
Terrace Graded Props (CVD) y = 0.2
y = 0.2 AdvanceSisOther Expert Assessment
TDD (cm-2) ≈ 1x104
PUD (cm-1) < 0.1 0.0
Relaxation (%) > 96 --
RMS roughness (nms)
(20x20μm)< 1.8 1.65
1.1x105
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SiNANO Workshop, Montreux, Sept 2006
Terrace Graded Props (CVD) y = 0.2
y = 0.2 AdvanceSisOther Expert Assessment
TDD (cm-2) ≈ 1x104
PUD (cm-1) < 0.1 0.0
Relaxation (%) > 96 --
RMS roughness (nms)
(20x20μm)< 1.8 1.65
1.1x105
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SiNANO Workshop, Montreux, Sept 2006
Misfits at the sSi/VS interface
MD
TD
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SiNANO Workshop, Montreux, Sept 2006
Misfits at the sSi/VS interface
MD
TD
…….but tsSi = 10nm which is < tc (17nm)
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SiNANO Workshop, Montreux, Sept 2006
EPD Reveal in VS with sSi layer
Additional etch pit
Strained silicon
Virtual substrate
TD
MD
TD
Chemical etchant
Etched surface
100% increase in EPD
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SiNANO Workshop, Montreux, Sept 2006
Terrace Grading – basic studies (y→0.2)(with sSi layer)…CVD
y
Thickness (μm)2 4 6 8
0.1
0.2
0.0
1.0E+04
1.0E+05
1.0E+06
0 1 2 3 4 5
0
20
40
60
80
100
Number of terraces
TD
D (
cm-2)
Relaxation of upper terrace (%
)
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SiNANO Workshop, Montreux, Sept 2006
50% terrace graded (for sSi)
TDD = 3x105 cm-2
PUD = 0
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SiNANO Workshop, Montreux, Sept 2006
80% terrace graded (for sGe)
TDD = 3x105 cm-2
PUD = 0
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SiNANO Workshop, Montreux, Sept 2006
Terrace graded VSs – smoother!
CMP
LG data from LETI
….and no CMP
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SiNANO Workshop, Montreux, Sept 2006
The Future• Terrace grading Heralds a new generation in VS quality:
eliminates pile-up
low TDD
potential to avoid CMP
route to production√
• Current work Examining new designs which directly manage the relaxation process:
→ thinner virtual substrates
→ TDD and PUD → zero
→ smooth enough for wafer bonding
• And finally
Still a lot of parameter space to be explored
– and if you thought Si-Ge relaxation was fully understood ..….……
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SiNANO Workshop, Montreux, Sept 2006
THINK AGAIN!
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SiNANO Workshop, Montreux, Sept 2006
Linkage with SiNANO
• Many VS-based sSi layers supplied to WP1 and WP2 partners for device processing
• VSs characterised by partners
• VS-based sGe layers supplied to partner for device processing
• VS-based sSiGe and sGe layers to be supplied to Jeulich for OI bonding trials
• VS work enabled a presence on PULLNANO project
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SiNANO Workshop, Montreux, Sept 2006
END