simultaneous switching noise

8/6/2019 Simultaneous Switching Noise

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ELE863/EE8501 VLSI Systems

Simultaneous Switching Noise (SSN)

B0

B1

B63

VDD

VSS

VDD

VDD,on-chip

VSS,on-chip

0

1

63

C

C

C

0

0

1

6363

Fei Yuan, Ph.D, P.Eng.

ProfessorDepartment of Electrical and Computer Engineering

Ryerson UniversityToronto, Ontario, Canada

Copyright cFei Yuan, 2011

Copyright (c) F. Yuan 2011 (1)


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Preface

This chapter deals with simultaneous switching noise (SSN). Thereduction of SSN is critical for mixed-mode circuits. In this chapter,we investigate the sources of SSN and the effect of SSN. Techniquesthat reduce the effect of SSN are examined in detail. The designcriteria for SSN are studied. The grounding schemes of analog anddigital circuits are investigated.



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OUTLINE


Effect of SSN

Analysis of SSN

SSN Reduction Techniques

Design Criteria for SSN

Analog and Digital Grounding



4/51

SSN

Figure 1: Bonding wires, bonding pads, traces, and pins.

Bonding wires, bonding pads, traces, and pins form the interface

path between circuits on the chip and circuits on boards.

The resistance, capacitance, and inductance of the interface pathslargely determine the performance of systems.



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SSN (contd)

Figure 2: Bonding wires, bonding pads, traces, and pins.

Bonding wires at the corners are the longest - These wires have thelargest resistance and inductance.

The use of the bonding pads at the corners and the bonding wiresconnected to these pads should be avoided.

The design rules of most CMOS technologies typically prohibit theuse of the bonding pads at the corners. These pads should be usedas dummy, i.e. no electrical connections to these pads.



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SSN (contd)

Figure 3: Bond pads and bond wires.

Bond Pads Bond pads are on-chip metal rectangles large enough to be soldered

to leads, typically 70x70 m2 - 100x100 m2.

Each pad is typically formed by the two top-most metal layersconnected to each other by many vias on the perimeter in order toavoid the lift-off of the top metal layer during bonding.

Some CMOS processes require that all metal layers to be connectedtogether for bond pads. Because the top metal layer has a smaller

capacitance to the substrate as compared with the bottom metallayer, connecting all bond-pad metal layers together willdramatically increase the capacitance of the pad to the substrate.

Do not lay pads at the corners of the chip. Add dummy pads at thecorners instead.



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SSN (contd)

The capacitance of bond pads consists of two components : (i) thearea capacitance and (ii) the fringe capacitance

CPadox

1.15A

H+ 2.8

T

H

0.222P

, (1)

where A=pad area, P=pad periphery, H=height of pad aboveconductive silicon substrate, T=thickness of pad, ox=dielectric

constant of silicon dioxide. The first term gives the area capacitancewhereas the second term quantifies the fringe capacitance (Ref. T.Sakurai and K. Tamaru, Simple formulas for two- andthree-dimensional capacitances, IEEE Trans. Electron Devices,Vol.30, No. 2, pp.183-185, Feb. 1983.)

H increases Cpad decreases. For high-speed applications, onlythe top metal layers, such as top two metal layers, should be used

for signal pads. For VDD and VDD pads, all metal layers can beconnected together to form pads.

w

h1h2

t1

t2

w

CaCf1

Cf2

Substrate

Topmetallayers

Vias

Figure 4: Bonding pads are formed by topmost metal layers.

Typically Cpad = 0.2 0.4 pF for a 100 100m pad.



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SSN (contd)

Inductance of Package Self-Inductance:

Lij =ijIj

=

Bij dsij

Ij, (2)

ij and Bij are the flux and intensity of the magnetic field that isgenerated by Ij and passes through loop i. Ljj , is called theself-inductance quantifying the relation between the magnetic fluxof loop j and the current of loop j, Lij, i=j is called mutualinductance.

I

Loop

Returnpath

B

Groundplane

Figure 5: Self-inductance definition.



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SSN (contd)

Inductance of Package (contd) Self inductance of a round bond wire

R

H

Figure 6: Self-inductance of a round wire.

Lol2

ln

2H

R

0.75

, (3)

where L=inductance per unit length, R=radius of the conductor, H

distance from the conductive substrate, and o=permittivity of freespace. Typically, L1nH/mm for bond wires. (Ref. T. Lee, TheDesign of COS Radio-Frequency Integrated Circuits, 2nd ed.,Cambridge University Press, 2004).

Self-Inductance of a rectangular trace

H

Figure 7: Self-inductance of a rectangular trace.



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L1.6

Kf H

W, (4)

where L= inductance per unit length, Kf0.72( HW

) + 1 (fringe

factor), W=width of the trace and H=distance from the trace tothe conductive substrate.



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SSN (contd)

Mutual Inductance of two round wires of equal length

I

Returnpath

I

Loop

Returnpath

B

Groundplane

Conductor1 Conductor21 2

1

Figure 8: Mutual-inductance definition.

H

d

Figure 9: Mutual-inductance of two round wires.

M =ol

2

ln

2l

d

1 + d

l

, (5)

where L=inductance per unit length, l=length of bond wires,d=distance between bond wires

For 10-mm length and 1-mm spacing, M4 nH. Since L10 nH,the coupling coefficient is 40% approximately.



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SSN (contd)

The Max. Frequency of Interfaces The capacitance of band pads and the inductance of bond wires

form a 2nd-order low-pass. The upper limit of I/O frequency is setby the cutoff frequency of the low-pass. From

H(s) =Vo(s)

Vin(s)

=1

s2

LwireCtotal + 1

, (6)

where Vin and Vo are the voltage at the pin and the pad of theinterface, respectively, we have

6dB =1

LwireCtotal, (7)

where Ctotal = Cpad + Cpkg.

When choosing packages, the highest design frequency of yourdesign must not exceed the cutoff frequency of the I/O package.



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SSN (contd)

Lumped Model of Bond Wires

vin vo

Lss

RssCss

Ldd

Rdd

ddC

vin vo

Cpad

Cpad Cpad

Cpad

VDD,off-chip VDD,off-chip

VSS,off-chipVSS,off-chip

Bondingwire

s

s s

s

Substrateground

Bondingpad

Figure 10: Lumped model of bond wires.

Rss=series resistance of bonding wires, Lss=self and mutualinductances of bonding wires, Css=package capacitance.

Bond wires are mainly inductive at high frequencies. TypicalLss5nH, and are usually modeled as an inductor.

If a high-frequency current flows through a bonding wire, a voltage

drop across the bonding wire quantified by VL(t) = Lssdi(t)

dtis

generated.

This voltage drop affects on-chip VDD and Vss for VDD and Vss padsand on-chip signals for signal pads.



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SSN (contd)

Output Buffers

VDD,off-chip

VSS,off-chip

CL

VL

VL

VDD,on-chip

VSS,on-chip

Cleanground

Chipboundary

Cleansupplyvoltage

Bondingpad

v in

Bondingwire

v o

iC

L

Lss

dddd

ss

Figure 11: On-chip VDD & Vss fluctuate due to switching noise.

Load capacitance of the inverter includes (1) Output capacitance ofoutput buffer, (2) Capacitance of bond pads, (3) Capacitance ofpackage, and (4) Capacitance of off-chip printed-circuit-board(PCB) traces.

Off-chip capacitances are typically much larger than on-chipcapacitances.

To meet timing constraints, large output buffers (wide inverters) are

needed to drive off-chip capacitive loads.

W/L Ron .

W/L Cout CL.



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SSN (contd)

Output Buffers (contd) The load capacitance is typically 1 30 pF. Typical size of output

buffers 500 1000m.

The size of inverter should be increased by a factor of e = 2.71828.The optimal number of inverters is such that the input capacitanceof the last inverter should be 1/e that of the load capacitance (Ref.

C. Mead and L. Conway, Introduction to VLSI systems,Addison-Wesley, 1980).

Typical ratio of 4 5 is used in sizing output buffers in order tosave silicon area.

Static inverter-based output buffers can be used for clock speed upto a few hundred MHz. These output buffers can not be used for

very high-speed clock speeds.



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SSN (contd)

Charging/discharging Currents of Output Buffers Large charging/discharging current spikes

1) CL is large, because iC(t) = CLvC(t)dt iC(t) is large.

2) Sharp rising/falling edges vC(t)dt is large iC(t) is large.

v

t

t

t

iC

VOH

VOL

in

v

VOH

VOL

o

t

VDD,on-chip

t

VSS,on-chip

VL

VL

VDD

0

dd

ss

Figure 12: Large charging/discharging current spikes and the fluctuation of on-chip VDD and Vss.



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SSN (contd)

Switching NoiseV

DD

Vss

CL

VL,DD

VL,ss

VDD,on-chip

Vss,on-chip

Cleanpower

Cleanground

Outputbuffer

Chip

Off-chipcapacitiveload

Noisypower

Noisyground

Figure 13: Noisy on-chip VDD & Vss.

When sharp charging/discharging currents of output buffers flowthrough the bond wires of VDD and Vss, large voltage drops vL,DDand vL,ss across the bond wires are generated

On-chip VDD and Vss vary with switching power fluctuation andground bouncing:

vDD,onchip = VDD vL,DDvSS,onchip = Vss vL,ss (8)



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SSN (contd)


B0

B1

B63

VDD

VSS

VDD

VDD,on-chip

VSS,on-chip

0

1

63

C

C

C

0

0

1

6363

Figure 14: Simultaneous switching noise.

Large switching noise at power and ground rails exist if multiplebuffers switch simultaneously Simultaneous switching noise (theWorst Case).

.

VDD,onchip = VDD vL,DD,

vL,DD = LDDiDDdt

= LDD63n=0

diC,ndt

.

(9)



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Effects of SSN

Fluctuation of on-chip VDD and Vss.

VDD,onchip = VDD vL,DD,Vss,onchip = vL,ss.

(10)

Reduce noise margins of digital circuits

v in

vo

VOH

VOL

VOHVOL VIL VIH NM NMH L

Noisemarginswithswitchingnoiseconsidered

VL

VL

NM NMH L

Noisemarginswithoutswitchingnoiseconsidered

ss

dd

Figure 15: Reduction of noise margins due to switching noise.

NML = (VOH VLdd) VIH,NMH = VIL (VOL + VLss).

(11)



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Effects of SSN

Change the Operating Point of Analog Circuits Consider a MOSFET biased in saturation, the transconductance gm

is given by gm =iD

vGS 2ID

VGS VT , where ID and VGS are channelcurrent and gate-source voltage at dc biasing point. Both ID andVGS are functions of VDD,onchip.

SSN imposes stringent requirements on analog circuits. Analogcircuits need to be differentially configured in mixed analog/digitalcircuits increased circuit complex.

CL

VL

VL

VDD,on-chip

VSS,on-chip

vin vo

VB

VB

v in

v+in

v-in

v+v-o o

M1

M2

vo

J

dd

ssAnalogportion Digitalportion

Figure 16: Mixed analog/digital circuits.



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Effects of SSN (contd)

Change of Operating Point of Analog Circuits(contd)

High power noise rejection difficult to design. If VDDfluctuation is of a critical concern, Fig.17(a) should be used. Thehead biasing current source behaves as an OPEN-CIRCUIT for VDDswitching noise and isolates the circuit from VDD rail.

If Vss fluctuation is of a critical concern, Fig.17(b) should be used.The tail biasing current source behaves as an OPEN-CIRCUIT forVss switching noise and isolates the circuit from Vss rail.

Cascodes and regulated cascodes are widely used in realizing thesebiasing current sources to maximize the resistance of the currentsources.

(a) (b)

Fluctuating VDD

Fluctuating Vss

Figure 17: Differential configurations.



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Effects of SSN (contd)

Increase the Timing Jitter of Oscillators/Clocks

VDD,on-chip

Vss,on-chip

C

Vo1

t

Vo1

Vo2

t

VTH

tVTH

tVTH

Clean VDD Noisy VDD

Dt

Figure 18: Timing jitter due to switching noise.

The threshold crossing points of ring oscillators vary due to thenoise (thermal and flicker noise) of the transistors. Such a variation

is quantified by 2

- the timing jitter.

Assume threshold voltage VTH = VDD,onchip/2. For rising edge,

VDD,onchip = vC + RpCdvCdt

, (12)

where Rp is the equivalent channel resistance of pMOS. It is seen

that vC, subsequently, the threshold-crossing point, vary withVDD,onchip, which is a function of switching noise.



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Analysis of SSN

Simplified Analysis of SSN

SSN in Sub-micron CMOS Circuits



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Simplified Analysis of SSN

Assumptions Triangle waveform of charging/discharging current.

Neglect channel resistance of transistors.

v

v

iLDD

iLSS

Imax

Imax

t/2s ts0

t

t

t

t

out

in

Figure 19: Simplified analysis of SSN.



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Simplified Analysis of SSN (contd)

Analysis Total charge stored in CL before discharging Q = CLVDD.

Total charge through L when CL is completely dischargedQ =

ts0 iL(t)dt = Iavgts =

Imax2

ts.

Charge conservation : CLVDD =Imax

2ts

Because

iL(t)dt

max

= Imax0ts/20 =2Imaxts

, we have

diLdt

max

=4CLVDD

t2s(13)

Example: L = 5nH, ts = 5ns, CL = 10pF, VDD = 5V, L

diLdt

max

=40

mV.

SSN is extremely sensitive to ts. Trade-offs between speed (ts) andSSN are made in design of output buffers. The speed of outputbuffers should be set to the lowest possible value to minimizeswitching noise.



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SSN in Sub-micron CMOS Circuits

Sub-micron MOSFETs Sub-micron : channel length is less than 1m.

Sub-micron MOS transistors exhibit velocity saturation due toexcessive lateral electric field and mobility degradation due toexcessive vertical electric field.

E(V/um)

Velocity(cm/s)Vsat=107

E(V/um)

Velocity(cm/s)

Esat=1.5

Vsat=107

Et(V/um)

Mobility(cm^2/Vs)

700

250

000

Figure 20: Velocity saturation and mobility degradation.

Square-law does not hold for sub-micron MOS transistors. Instead,-power law applies.

iD =

0 ifvGS < VT (cutoff)kl(vGS VT)/2 ifvDS < vDS,sat (Triode)ks(vGS VT) ifvDS > vDS,sat (Saturation)

(14)

where kl = nCox(W/L), ks =1

2 nCox(W/L). Typically, 1 < < 1.2



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SSN in Sub-micron CMOS Circuits (contd)

Analysis For a total of n output drivers that switch simultaneously, the total

current

iDS,total = niDS = nks(vin VT vn) (15)

SSN

vn = LssdiDS,total

dt

= Lssnks(vin VT vn)1 d(vin vn)dt

(16)

Because a1, (vin VT vn)11 We therefore have

vn = Lssnks(dvin vn)

dt

= Lssnksdvindt

Lssnksdvndt

(17)

This gives

dvndt

+ vnnLssks

= dvindt

(18)



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Input waveform

VDD

VT

tn

t

r

tf

Vin

Figure 21: SSN analysis.

Slopes

Slope of the rising section of the input

dvindt

= Sr = VDDtr

(19)

Equation for the rising section

Substituting the slope (the rising section of the input)

dvn

dt

+vn

nLssks= Sr, vn(tn) = 0, tn =

VT

Sr, tn

t

tr (20)

This is a first-order ODE.



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Solution

Homogeneous ODE - general solution

dvndt

= vnnLssks

(21)

vn = Ae(ttn)nksLss

, ttn (22) Special solution (vn = C (constant))

C

nksLss=

VDDtr

(23)

which gives

C =

VDDtr nksLss (24)

Complete solution

vn(t) =VDD

trnksLss + Ae

(ttn)nksLss (25)

Match the initial condition at tn = VTSr , vn(tn) = 0

A = VDDnksLsstr

(26)



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Complete solution

vn(t) =VDDnksLss

tr

1 e (ttn)nksLss

, tnttr. (27)

Remarks:

vn(t) is proportional to

n (number of switching buffers) Lss (bond wire inductance) ks = 12 nCox(W/L)n (buffer size) 1/tr (switching time)

The maximum SSN

Vn,max =VDDnksLss

tr(28)

For a reliable operation, Vn,maxVT is generally required. Thisyields the limiting condition

VDDnkLsstr

= VT (29)

from which n and W can be determined for given VT and tr.



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SSN Reduction Techniques

Separate power and ground pins and pads for analogand digital circuits whenever possible

VDD

Chip

Bondwires

VDD

Toanalogcircuits

Todigitalcircuits

Bondwires

Analogpad

Digitalpad

Digitalpin

Analogpin

Figure 22: Separate analog and digital pins and pads.

Switching noise generated by the digital portion of the system willnot affect the operation of the analog portion of the systems.



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SSN Reduction Techniques (contd)

Multiple pads and pins for power and ground

V

Chipboundary

Bondwires

Tocircuits

DD

Off-chipdecouplingcapacitor

PAD

Figure 23: Multiple pins and pads.

Increase the number of pins smaller inductance lower SSN.



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Multiple pads and pins for power and ground(contd)

Pin=1

Pin=2

Pin=5

Pin=10

NumberofDrivers

SSN

Figure 24: Effect of multiple pins.

Increase the number of pins better linearity of SSN.



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Avoid using corner pads Corner pads have long bonding wires large self-inductances.

Most design rules require dummy pads (pads with no connection) atcorners.

Use center pads for VDD and Vss

smaller

inductance, smaller SSN.

Short bond wires, small self-inductances.



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Pre-driver skewing

To prevent the entire buffer (multi-finger layout - multiple

smaller inverters connected in parallel) to switch at the same

time.

Use RC Delay Lines

G

S

D

n+1 2 3 4

Metal-1Metal-2

Contact/via

Figure 25: Multi-finger layout of output buffers. Both drain and source are shared by neighboringfingers.

M1 M2 M3 M4

G

D

S

Figure 26: Schematic of the equivalent circuit of output buffers with a multi-finger layout.



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Pre-driver skewing (contd)

CL

vo

Cn

Cp

Cn

Cp

Rn

Rpvin

Ldd

Lss

VDD

Figure 27: Output buffer with pre-skew.

Rn, Rp = lumped n-well or poly resistors, Cn, Cp = gate-sourcecapacitance. P1/N1 turn on first, P1/N1 turn on second, and

PM/NM turn on the last.

Drawback - reduced speed. Compromise between SSN and speedmust be made.



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Pre-driver skewing (contd)

Use Gate Series Resistance for skewing

G

S

D

n+ diffusion

Gate series resistances

Figure 28: Pre-driver skewing using the gate series resistance.

Less effective for silicide processes because the sheet resistance ofgate ploy is small (approximately 7/2).



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On-chip decoupling (bypass) capacitorsVDD

CL

L

Lss

VDD,on-chip

VSS,on-chip

Digitalcircuits

On-chipdecouplingcapacitor

dd

Figure 29: On-chip decoupling (bypass) capacitors.

On-chip decoupling capacitors are effective in reducing SSNgenerated by internal logic circuits because they prevent currentspikes generated by the internal logic circuits from going to Lss andLDD by providing a local AC path. On-chip decoupling capacitorsserve as local charge reservoirs.

On-chip decoupling capacitors must be very large in order to beeffective, usually comparable to the total area of all transistors onchip (10-20% of total silicon area) - very expensive !

Resistance is needed to avoid the self resonance formed by theon-chip decoupling capacitors and bond wires on-chipdecoupling capacitors are typically implemented using MOScapacitors. The channel resistance of MOS capacitors are beneficialin minimizing the self resonance of the preceding LC networks.



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Most CMOS fabrication processes require certain percentage ofmetal fill ratio for each metal layers (required for minimizing

mechanical stress reasons). Dummy metal sections are oftenemployed in each metal layer to fulfill this requirement. Thesedummy metal sections can be arranged in such a way that theyform on-chip decoupling capacitors to improve the performance ofdesigned chips.



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Hierarchy of decoupling capacitors (contd)

PCBboardboundary

Chipboundary

On-boarddecouplingcapacitor

On-chipdecouplingcapacitor

Externalsupplyvoltage

Locallogic

Locallogic

Locallogic

Transientcurrent

Figure 30: Hierarchy of on-chip de-coupling capacitors.

Both off-chip and on-chip decoupling capacitors are required

to minimize switching noise.

Decoupling capacitors must be placed as close as possible to

hot spots (noise sources) to eliminate generated switching

noise locally.

Traces and interconnects for decoupling capacitors must have

a low impedance at high frequencies such that a

low-impedance path exists to eliminate switching noise.



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Fully-balanced buffers

D 1

D 2

DN

RL

RL

RL

Ldd

Lss

Figure 31: Balanced buffers.

Each buffer conveys a fully differential current to the channel. Eachbuffer draws a constant current from the supply and injects aconstant current to the ground. No net rate change of the currentflowing through VDD and ground pins - no switching noise.



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Fully-balanced buffers (contd)

DD

Channel

I

D D

I

D D

Channel

I

z T z T

Figure 32: Balanced buffers.

In the left figure, low-voltage-differential-signaling (LVDS) is used.The logic state of the output is represented by the direction of theoutput current. The channel is terminated at the far end by thetermination resistor. The resistor also converts the current into a

voltage.

In the right figure, the channel is terminated with the linecharacteristic impedance at the near end of the channel.



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Current-mode logic circuits Use logic circuits that draw a constant current from VDD and inject

a constant current to Vss. Current-mode logic (CML) circuits, fullydifferential logic circuits belong to this category.

I

Vb

J

Vb VbM7 M8

A A

B B A A

AB AB

J

Vb Vb

B B

B B A A

A+B A+B

A A

A A

Figure 33: Current-mode logic gates.

CML circuits draw a constant static current from VDD regardless of

its logic states

CL

diL

dt

= 0, resulting in zero switching noise.

CML circuits consume static power. They are typically used forI/Os or in applications where switching noise is critical.

CML circuits consume less power as compared with static logiccircuits at very high frequencies. This is because the dynamic powerconsumption of static circuits is governed by Pd = aCfV2DD, wherea=switching activity parameter, f=frequency. It is evident that Pd

is directly proportional to f. The power consumption of CMLcircuits is independent of f!



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Design Criteria for SSN

SSN must less than Threshold Voltages For a reliable operation, Vn,max < VT is generally required.

Switching noise derived before

vn(t) =VDDnksLss

tr 1 e

(ttn)nksLss , tn

t

tr. (30)

This yields

VDDnkLsstr

= VT, (31)

from which n and W can be determined for given VT, f, and tr.



45/51

Analog and Digital Grounding

Substrate Modeling Resistive paths exist from p+ contacts to p-substrate. A voltage

change of p+ contacts affects the voltage of substrate.

Capacitive paths exist from p+/n-well, n+/p-substrate, andn-well/p-substrate junctions.

p+ p+ n+

Rp+

CJ 12

R11 R22R11 R22

R12

Backplane

Figure 34: Lumped models of heavily doped substrates.

R12R11, R22. R12 = resistance between contacts, R11,R22=resistance from contacts to the backplane. Most of substratenoise will travel vertically down to the backplane. The backplanemust be grounded properly to avoid the distribution of substratenoise to the entire chip. (Ref.: B. Owens et al. Simulation andmeasurement of supply and substrate noise in mixed-signal ICs,IEEE J. Solid-State Circuits, Vol.40, No.2, pp. 382-391, Feb. 2005).



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Analog and Digital Grounding (contd)

Separate analog and digital power pads and bondingwires for analog and digital circuits.

V

Chipboundary

Bondwires

Analogpad

Digitalpad

DD

Off-chipdecouplingcapacitor

ovin

v

vin

ov

Figure 35: Separate analog and digital VDD pads and bonding wires for analog and digital circuits.

Digital VDD rails are much more noisy as compared with analogVDD.



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Separate analog and digital ground pads andbonding wires for analog and digital circuits.

Chipboundary

Bondwires

Analoggroundpad

Digitalgroundpad

o

vin

v

vin

ov

Figure 36: Separate analog and digital Vss pads and bonding wires for analog and digital circuits.

Digital Vss rails are much more noisy as compared with analog Vss.



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Separate analog and digital substrate connections.Chipboundary

Analoggroundpad

Digitalgroundpad

o

vin

v

vin

ov

Substratepad

Figure 37: Separate analog and digital substrate connections.

Analog substrates are typically protected by guard rings. They areless noisy as compared with digital substrates.

Connecting analog substrate to the outside ground directly canlower the voltage fluctuation of the analog substrate. Downside:body effect occurs as VT = VTo +

Vsb + |2F|

|2F|), where

is body-effect coefficient and F 0.6V is the Fermi potential.

If analog substrates are well protected, then the source ofMOSFETs and analog substrates can be tied together to eliminatethe body effect. Example - differential pairs.



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Figure 38: Differential configuration.

Single-ended configuration - vGS is directly affected by groundbouncing.

The output of differential-mode configurations is insensitive of SSNas the biasing circuitry provides a constant biasing current to thedifferential pair regardless of ground bouncing.

Deep sub-micron MOS transistors have a small output impedance,reducing the effectiveness of the biasing circuitry. Cascode isgenerally mandatory in biasing circuits to minimize the effect ofground bounding.



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Passive Guard-Rings Use passive guard-rings to isolate sensitive circuits from noisy

digital circuits.

p+ guard rings - p+ diffusion contacts on p-substrate to collectholes. n+ guard rings - n+ diffusion contacts in n-wells to collectelectrons.

Guard ring resistance should be made as low as possible guardrings should be made as wide as possible.

Guard rings should be placed as close as possible to noise sources.

Analogcircuits

p+

Metallayer

Contact

Analogcircuitsp+p+

p-substrate

Metallayer

Contact

Chipboundary

Bondingpad

Bondingwire

(a) Topview (b)Sideview

Off-chipground

Figure 39: p-type passive guard rings.



51/51


Active Guard Rings

p-substrate

Activeguardring

Dvvo

p+ p+

Digitalcircuits

Analogcircuits

vo

vn

Substratenoiseis

representedby Vn

RR

R

R

Figure 40: Active passive guard rings (Ref. K. Fukuda et al., Substrate noise reduction using activegrant band filters in mixed-signal integrated circuits, IEICE Trans. Fundamentals of Electronics,Communications and Computer Sciences, Vol. E80-A, pp.313-320, Feb. 1997).

Use active guard-rings to ACTIVELY isolate sensitive circuits fromnoisy digital circuits. Active guard rings perform better as

compared with passive guard rings.

The inverting voltage buffer must have a large bandwidth in orderto be effective in suppressing substrate noise. This is because vncontains a significantly large number of high-frequency componentsand these components must appear at the output of the buffer inorder to suppress substrate noise.

simultaneous switching noise

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