DesignCon 2006

Analysis of FPGA Simultaneous Switching Noise in Three Domains: Time, Frequency, and Spectrum Hong Shi, Altera Geping Liu, Altera Alan Liu, Altera

Abstract Simultaneous switching noise (SSN) and its behavior have become increasingly important in high-performance FPGA system design featuring hundreds of I/Os transmitting in parallel at low supply voltage standard. In this paper, we present an in-depth study on SSN by analyzing its behavior in three different domains: time, frequency, and noise spectrum. Cross correlation in these three domains reveals two dominant cause mechanisms: frequency dependent PDN impedance and crosstalk from package-PCB breakout region. Each mechanism has its manifestation in time-domain SSN waveform. Furthermore, simulation confirms our postulations made on examination of experimental data and validates the methodology practical to SSN assessment in FPGA applications. Author Biographies Hong Shi is technical lead for electrical design in thePackaging Technology Group of Altera Corporation. His current responsibilities include developing strategy for high-density and high-performance FPGA packaging, simulating system level electrical performance, and developing chip-package-board interconnect co-design capability. Before joining Altera, Hong was with HP and Agilent Technologies where he was principal engineer and project leader for Agilent’s first 40-Gbps digital communications analyzer module. Hong has published over 30 technical papers in areas of optoelectronics, microwave circuits, and digital circuit packages. Hong obtained his BSEE from Xi’an Jiaotong University, a MS Physics from DePaul University, and a PhD in electrical engineering from CREOL College of Optics at University of Central Florida. Geping Liu received his BS and MS degrees in electrical engineering from Tsinghua University, Beijing, China in 1997 and 1999, respectively, and a Ph.D. degree in electrical engineering from the University of Missouri-Rolla in 2004. From 2000 to 2004, he was with the Electromagnetic Compatibility Laboratory, University of Missouri-Rolla, as a graduate research assistant. He is currently with Altera Corporation as a senior characterization engineer. His research interests include signal integrity, power integrity and electromagnetic compatibility (EMC) designs in high-speed digital systems, and development and application of numerical and experimental methods in resolving signal integrity and EMC problems. Alan Jian Liu is a packaging design engineer at Altera Corporation. He received his MSEE from University of Utah. His interests include package level signal integrity analysis and high-speed digital system design. Currently he is working on characterization, modeling, and correlation of complex FPGA packages.

I. Introduction With silicon technology going to nanometer feature dimension, I/O buffers are driven by ever lower supply voltages. The increasing number of I/Os in simultaneous transmission demand significant amount of transient current in power distribution networks. As a result, the system noise margin is seen as close and progressively more sensitive to supply voltage noise. For FPGA end users, it is necessary to have a clear understanding on the cause of simultaneous switching noise (SSN) and its behavior in FPGA chip-package-board environment. We present here an analysis on SSN in FPGA devices and systems by studying its behavior in three different domains: time, frequency, and spectrum. The paper is divided into four main sections. The first section starts with an overview of general FPGA system and commonly known SSN mechanisms. The second section describes SSN behavior in time domain and measurement methodology widely used for FPGA devices. The third part looks at SSN from the perspective of frequency response of the power distribution network and the system noise spectrum. The fourth part employs simulation methodology to validate analysis performed on experimental data. With cross-domain examination, we hope to provide a complete picture of SSN characteristic behavior and its relationship to cause scheme in FPGA systems. This study methodology can help us understand its complex nature and decode its fundamental mechanisms. II. Overview of SSN in FPGA Systems FPGA devices have unique features of programmability in interface types, I/O bus width, current drive strength, and multi-chip vertical migration. In the meantime, flexibility brings challenges to device designs. In this section, we start with an overview of SSN in FPGA systems. It has been widely acknowledged that SSN is caused by two main physical mechanisms, delta-I noise in power distribution network (PDN) and mutual inductive coupling among many switching I/Os. Figure 1 illustrates a symbolic FPGA system diagram, in which contributions of PDN delta-I noise and mutual coupling are labeled with noise-like waveforms near the problematic regions. Briefly, delta-I noise in PDN is governed by: Δv = L dI/dt where L is the series inductance of package and PCB PDN. dI/dt, or delta-I, is a source-drain current transition when input to a gate is changed from logic low to logic high or vice versa. The amount of current taken into account is the sum of all toggling I/Os hanging on the power rail, which can be estimated with individual drive strength. Δv is

referred as voltage dropped over PDN such that VCCIO at I/O buffer is Δv less supply voltage. Drawn by a piece-wise waveform close to PDN represents power sag caused by delta-I mechanism. A non-toggling I/O, often referred as “quiet” or “victim” pin, is pulled logic high to act as a voltage probe passing power rail noise through I/O trace to the outside of the package where it can be measured. On its way out of the package, the quiet pin is coupled with crosstalk voltage from adjacent toggling I/Os in the package-PCB breakout region. The underlying reason is that multiple I/Os share a common return path such that magnetic field is coupled among loops formed by the I/O and the common return path. This mechanism is best described by: Δv’ = ∑Miq di/dt where Miq is mutual inductance between the quiet, q, and each single toggling pin, i, in the package-PCB breakout area. In this case, di/dt is from every single neighboring I/O current transition. Noise voltage Δv’ is directly coupled to the quiet pin and shown as noise spikes lining up with switching edges where di/dt is the greatest.

Figure 1. Symbolic FPGA System Under the Influence of SSN It seems apparent from the overview that both SSN mechanisms play a role in FPGA devices and systems. However, questions still remain in regards to validation on a real-world FPGA devices and systems, as well as detailed behaviors and their relationship to cause mechanisms. III. Simultaneous Switching Noise in Time Domain In this section, extensive analysis is performed on a real-world system and its associated measurements. The study will make use of both experimental data as well as simulations to reveal SSN features from multiple angles.

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Many recent studies have been performed on SSN noise from a time domain perspective. The general tactic here is to capture noise waveform, comparing noise amplitude and timing delay as performance criteria among different devices and systems. It provides an intuitive understanding of the magnitude of SSN for digital design engineers as it examines input threshold voltage violations and timing delays directly. In Figure 2, a typical SSN measurement setup is given for a FPGA characterization. In this example, the FPGA device is configured as a SSTL18 Class II interface. A varying number of I/Os act as aggressors and toggle simultaneously in repetitive format. A single victim I/O net is kept either static high or static low, which is realized by shorting its output to power rail or ground by FPGA programming. A typical application load of 10pF is applied to both aggressor and victim. Noise is captured on the victim net referring to a local ground at the far end of the system with a high-impedance high-speed oscilloscope probe.

Figure 2. Experiment Setup for SSN Characterization in FPGA Applications In this measurement, the repetition rate is lowered to 10 MHz such that ripples are allowed to settle completely before the next switching event. Aggressor I/Os can have 1, 10, 40, or a maximum number in a bank toggling at once. The oscilloscope and probe are chosen to guarantee measurement system bandwidth of greater than 5 GHz so as to truthfully detect the wideband nature of noise. Figure 3 shows the measurement results of 60 I/Os toggling at the same time in the same repetitive pattern.

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Figure 3. Measured SSN Waveform in Time Domain Notes to Figure 3:

1. Top trace: voltage sag on a quiet pin pulled high, middle trace: toggling I/O at 10-MHz repetition rate, bottom trace: ground bounce on a quiet pin pulled low

In time-domain SSN noise waveform, VCCIO sag and ground bounce are the most noticeable and understood. However, the remaining results are not readily understood and seem puzzling. To facilitate the analysis, we tabulate all features and fill in numerical values from the measurements in Table 1. A simple question to ask is what these parameters mean to an FPGA system SSN and how they relate to the cause mechanism. We need to peel away the layers to get inside the puzzle. Comparing parameters reveals that ∆V and ∆T are unique to the power rail. Thus, it is worthwhile to look closely at the power distribution network. Since PDN involves frequency dependent impedance, the most intuitive strategy is to study it from the frequency domain viewpoint. Furthermore, it has been known in the RF and microwave world that spectrum analysis has a great dynamic range and harmonics diagnostic capability, making it effective to study noise-like signals with a random nature. We will adopt both methodologies in the following sections. By the end, the results from the frequency and spectrum domain will be brought back to the time domain to correlate the noise features and close the loop. Table 1.

VCCIO Sag

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∆ vQuiet Pin High

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Time-Domain Parameters Value From Measurement VCCIO sag 200 mV

Ground Bounce 200 mV- ∆V 20 mV ∆T 5.5 ns ∆t 950 ps τ sag 5.3 ns (≈∆T) τ bnce 2 ns

IV. SSN in Frequency and Spectrum Domain [1] PDN Impedance in Frequency Domain As depicted in the symbolic FPGA system in Figure 1, a PDN consists of three main parts: chip, package, and board. The series inductance is sum of individual inductance from package and board. As a common practice for high performance IC, the chip is often equipped with on-chip bypass capacitors to provide instantaneous charges from a nearby location to buffers and to replenish source-drain current rush upon gate transition. From the point of view of the I/O buffer, the on-chip bypass capacitor and series inductance of the system PDN form a parallel resonance circuit. At certain frequency, fc, the parallel resonance circuit becomes high impedance or open circuit in an ideal situation, which produces a significant voltage drop at this frequency.

Figure 4. PDN Section in an FPGA System, With Factors of Chip, Package, PCB In order to characterize fc, we need to extract the whole system PDN including chip, package, and board PDN. Since the chip PDN is considered mainly capacitive, its inductance is neglected, which can be justified when compared to the great inductance value of the package and PCB. Package PDN is extracted from measurements performed with the 2-port self-impedance VNA method. While this method has been widely adopted

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in this field, the difference in our application is that we measure a package with the chip already mounted and probe it from the ball side with different bias voltages simultaneously applied to it. As compared to the bare substrate measurement, the benefit is to have an on-chip capacitor naturally connected between the nodes of the package VCCIO and the ground bumps. In this way, the measurement will extract not only the package PDN RLC, but also an on-die bypass capacitance value, which is often difficult to measure directly. A well-designed SSN characterization board is also measured in terms of s-parameters between ball pads and the far-side power node where power enters the board. The board is fully loaded with bypass capacitors as it would be in real applications. The behavior of the s-parameters fits with the RLC equivalent circuit so board series inductance is known and cascades to the chip and package. To validate the measured value of system PDN impedance, a field solver is employed to generate models for the package and board PDN. Figure 5 shows the system PDN impedance curves from the chip side, the same perspective that the chip would see during actual operations. Not shown in the 10-MHz region is the board bypass behavior. Due to its low impedance, this is not a major concern now as compared to the impedance pole at 100 MHz.

Figure 5. System PDN Impedance as Measured and Modeled Note to Figure 5:

1. The red curve is from the field solver model and the blue curve is from the measurement extraction.

The salient feature on the system PDN impedance curve is the impedance pole generated by the parallel resonance of on-chip bypass capacitance and the combined series inductance of package and board PDN. A good correlation is achieved between model and measurement, and both yield the same resonance frequency. The resonance

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frequency, fc, is read at approximately 180 MHz. The implication of the impedance pole is that the supply voltage will experience the most sag when either transient current switches at this frequency or harmonics of a lower data rate fall at this frequency. The former will directly affect VCCIO sag and the latter will produce oscillations on the power rail at a harmonic frequency corresponding to fc. The second feature is DC resistance, which is the interception point of y-axis at near zero frequency. The DC resistance contributes to the fixed voltage drop, ∆V, at the static state of logic high, because in this state current is flowing steadily from the PDN to the SSTL I/O termination. In order to understand the relationship between the PDN impedance pole and SSN noise, one needs to look at the issue in terms of a multiplication operation of the switching current spectrum and the frequency domain PDN impedance. Furthermore, although frequency domain PDN impedance analysis can explain to the first degree of understanding the impact of the impedance pole to SSN, crosstalk mechanism, one of the dominant contributors to SSN, has not been addressed. This requires noise spectrum analysis, especially because the noise spectrum is sampled on the quiet pin voltage at the receiver end, in which both power rail degradation as well as crosstalk are embedded. Lastly, spectrum analysis can verify the on-chip bypass capacitance value. In our previous work, we demonstrated how to extract on-chip decoupling capacitance values through combined chip-package measurement. The value is extracted indirectly by curve fitting measurement data with a chip-package PDN equivalent circuit. However, it is known that the on-chip decoupling function comes from a combination of mechanisms and may vary by the amount of supply voltage, number of switching buffers, data patterns, etc. Its value under the dynamic operation can be derived directly in the spectrum domain, as shown in the following section. Both numbers from the static and dynamic operations will then be compared. [2] SSN Noise in Spectrum Domain In the PDN impedance study, a single frequency current source acts as stimulus to the chip-package-board PDN network and continuously sweeps from DC to a certain high frequency. An alternative stimulus source is the discrete frequency pulse train that extends from DC to high frequency range. This is a common technique, often referred as Fourier Analyzer in the RF and microwave field. Its spectrum I(f) is the Fourier transform of time-domain signal i(t) and can be expressed as ∑I(f-n∆f). The relationship between the current pulse spectrum, PDN impedance Z(f), and voltage at PDN node V(f) is as follows:

∑V(f -n∆f ) = ∑I(f-n∆f) · Z(f) Equation 1

where n = 0 to ∞ and ∆f is the spacing between adjacent frequency pulses.

From the equation, it is obvious that an ideal PDN with only DC resistance will zero out all current frequency contents except DC current such that voltage at PDN node is a straight DC voltage. However, a non-ideal PDN carries a frequency dependent impedance, as depicted in Figure 5, so that the voltage at the PDN node will contain several frequency contents. Figure 6 (A) shows the circuit diagram of the current frequency pulse source I(f) and the PDN network. A direct implementation of this scheme is by means of the PMOS buffer driven by input data with repetitive patterns. Figure 6 (B) illustrates the equivalent configuration with CMOS buffers.

Figure 6. “Fourier Analyzer” for System Response Measurement (A) and its Implementation via CMOS Devices in FPGA System (B) In Figure 6 (B), the PMOS behaves as a switching current source controlled by the input signal level. The switching current is provided from an on-chip decoupling capacitor for high-frequency current spectrum components, an on-package decoupling capacitor for mid-frequency components, and by the PCB decoupling capacitor for low-frequency components. A closed loop for the transient current is formed by the PDN ground net and the I/O transmission line return path. The latter becomes apparent if displacement current is taken into account. The discrete current spectrum ∑I(f-n∆f) may take different forms depending on the time-domain data pattern. In the CMOS operation, the repetitive input signal will generate repetitive current toggling by means of the switch function of CMOS. From Fourier

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transform theory, a repetitive, time-domain, square-wave current pulse train has the spectrum of discrete frequency components modulated by the sin(x)/x, or sinc, function. Figure 7 shows an example of the square-wave pulse train spectrum and the features associated with the time-domain signal.

Figure 7. Example of Square-Wave Pulse Train Spectrum and Features Associated With Time-Domain Signal The top graph of Figure 7 shows a time-domain square-wave pulse train with a rise time of Tr (inset graph) and period of T. In the bottom graph, the spectrum of square-wave pulse train shows distinct sinc function lobes and odd harmonic contents, which are a spectral characteristic of square-wave pulses with 50 percent duty cycle. The “break” frequency, often referred as bandwidth, is 0.35/Tr. In log-log scale, frequency contents roll off at 20 dB/decade before the break frequency and 40 dB/decade after.

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Now take a moment to review memory interface applications using a common standard, SSTL18 Class II. Its system configuration has already been shown in Figure 2. SSTL is often studied for SSN immunity because it has the lowest supply voltage requirement, making it more vulnerable to PDN noises. When driven by a repetitive input signal, SSTL-configured I/O buffers draw current from the PDN in the form of a toggling square-wave. The voltage variance at the buffer power node will become the product of toggling current spectrum and system PDN impedance, as shown in Equation 1. In other words, the voltage spectrum is a modulated (multiplied) current spectrum by the PDN impedance curve, so that the impedance resonance peak at fc is expected to be visible. To demonstrate the theory, a series of spectrum measurements are performed in the lab. The measurement strategy is to make use of the FFT math function of a real-time sampling oscilloscope and to convert time-domain noise into spectral contents. An adequate sampling rate and point are selected to guarantee no aliasing occurs in the FFT conversion. Another technique used is averaging, if the waveform is repetitive. This way, a great dynamic range can be achieved for the captured spectrum. Figure 8 shows a spectrum for the voltage captured on the quiet pin at the far end, along with its time-domain waveform. The conditions are 60 I/Os simultaneously toggling, each with about 300-ps rise time. It should be noted that function of the quiet pin is as a voltage probe into chip bump, where the lab probe is not accessible. The quiet pin is pulled high to the power rail to effectively tap out noise behavior of the voltage at bump. Furthermore, the high-bandwidth transmission line nature of the quiet pin net can transmit noise, often wide bandwidth, truthfully to the far-end measurement location. By inspecting the measurement results in Figure 8, it can be seen that the quiet pin voltage spectrum is a modulated current spectrum. While the modulated spectrum retains certain original current spectral features such as dominant odd harmonics, the two peaks are new and very visible, with peak A at about 165-180 MHz and peak B at 900 Mhz-1 GHz. Peak A is of particular interest to us because its peak frequency matches PDN impedance resonance frequency, fc. This phenomenon confirms early expectations about the modulation nature between current spectrum and PDN impedance, as well as the location of the impedance pole. It is the resonance peak A appearing at fc in the spectrum that proves on-chip decoupling capacitance in dynamic operation has similar value to that measured and extracted in static mode by VNA. The peaking in spectrum often indicates higher spectral power around the peaking frequencies than other regions. The high spectral power manifests itself in time domain as evident oscillations ringing at period of one over peaking frequency. With a 165-180-MHz peaking frequency, one would expect to see 5.5-6 ns oscillations in a time domain waveform, which is the exact case (∆T) in Figure 3. In SSN terms, supply voltage suffers the most dramatic sag at frequencies where the harmonic of current spectrum lines up with peak impedance.

Figure 8. Spectrum of Voltage Captured on Quiet Pin at Far End, Along With its Time-Domain Waveform However, it is slower than the 20 dB/decade roll-off and the second peak B around 1 GHz implies other fast mechanisms in play. It has been confirmed in simulation study[1] that the fast mechanism is crosstalk coupled onto the quiet pin in the package-PCN breakout region. For now, the explanation is given. Figure 1 illustrates how mutual coupling causes crosstalk from toggling the signal transmission line to the quiet pin transmission line. The coupling is governed by Δv’ = ∑Miq di/dt, where Miq is mutual inductance representing coupling effectiveness between individual toggling I/O and the quiet pin.

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Since i(t) flowing in the toggling aggressor pin is in the square-wave form having the same periodic nature as the switching current through CMOS device, its derivative would be a delta function with short pulses at the rising and falling edges only. The coupled voltage is scaled short pulses by factor, Miq. The total coupled noise on the quiet pin is a summation of coupling voltage from each toggling I/O to quiet pin with a coefficient governed by individual Miq. This coupled voltage behaves as a noise spikes additive to the voltage waveform on the quiet pin in the time domain as well as in the spectrum domain. With Fourier theory, the short pulse train in time produces a frequency pulse train modulated by an envelope with bandwidth inversely proportional to the time pulse width, which is by nature a derivative faster than original i(t) rise time. As a result, the pulse spectrum will have a flatter envelope than a square-wave does and adding on the quiet pin makes the combined spectrum rolling off slower than a square-wave spectrum does. In addition, since crosstalk voltage is proportional to the derivative of the current, its edge rate is even higher than Tr. Thus, the fast crosstalk voltage is inevitably reflected by the load capacitor (an impedance discontinuity) and induces ringing at a period equal to the round-trip time between the coupling point, ball, and the discontinuity point, load capacitor. The consequence of reflection is a spectrum peak (B) established and centered at 1 GHz that corresponds to a 1-ns ringing period. This result correlates well to time-domain fast oscillations at a period of 950 ps (∆t), immediately following the down edge of the initial voltage sag. In this test board design, the transmission line between ball and load is 3 inches, which gives a 500-ps one-way delay or 1-ns round trip time.

Figure 9. Ground Bounce Spectrum Measured in Lab as Quiet Pin Pulled Low by FPGA Program From perspective of ground bounce, crosstalk and its reflection can be verified. When ground bounce occurs, the PMOS is turned off and detaches power net from the event.

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The loop is made of NMOS device, I/O transmission line, return path, and load (see Figure 1). The dominant ground bounce is caused by pure crosstalk in the breakout regions, a claim that can be justified by the nearly equal magnitude and shape of two pulses along the rising and falling edge in Figure 3. This is typical to far-end crosstalk. By examining the ground bounce spectrum measured in the lab, as shown in Figure 9, the flat top from 10 MHz to 300 MHz and peak B are both evident. There is no apparent peak A, indicating that the power net is not a major part of ground bounces. Considering that the same mechanism works on the quiet pin when it is pulled high (crosstalk does not distinguish victim pin high or low), the spectrum similar to ground bounce is added to the original spectrum on the quiet pin that has only a PDN impedance peak embedded prior to coupling. The common features between ground bounce and sag spectrum remain flat roll-off and peak B, as shown in Figure 8 and Figure 9. To strengthen the validity of our analysis about crosstalk effect in SSN, a FPGA device with a similar PDN structure but with improved breakout and crosstalk design is characterized using the same bench setup. Figure 10 shows the new spectrum in which peak B drops by 20 dB, or 100x in voltage magnitude at its center frequency, while peak A remains roughly the same. Also interesting to notice is the roll-off start of 20 dB/decade, at least for the fundamental data rate and the first two dominant harmonics. Because the bandwidth enhancement feature from crosstalk is practically removed from

the picture. Figure 10. Voltage Sag Spectrum for an FPGA Device With Improved Crosstalk Coupling but Similar PDN To summarize, crosstalk is an additional embedment of noise on the quiet pin other than voltage oscillation generated by PDN impedance peaking. These are caused by two distinct mechanisms and impose on the quiet pin in different times and locations, yet both transmit to the far-end and are captured.

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V. SSN Modeling and Simulation In this section, a practical SSN modeling and system simulation method is employed to verify the findings from an experiment. Recently, we have proposed a simple, yet practical, strategy, namely the structural method, which interprets SSN in terms of its dominant contributing factors in the chip, package, and PCB board [1]. It is much different from the conventional “black-box” behavior modeling method. Figure 11 illustrates this methodology.

Figure 11. Illustration of “Structural” SSN Modeling Methodology Based on the structural method, all SSN contributions are categorized into vertical and horizontal structures, where vertical structures consist of bumps, PTH and micro vias, balls, and PCB breakout vias, and horizontal structures consist of I/O traces and board power planes. The essence of this method is to break down individual contributors in two directions and then model each separately. Horizontal structures are modeled as a transmission line and vertical structures modeled in a coupled RLC matrix. Great care is taken to assure RLC segments meet the bandwidth requirement. The system simulation will be performed on a chain of linked models, from chip buffer to load on board to PCB power supplies. As compared to black box behavior models, this method has the advantages of fast turn-around time (less than a hour), modular blocks for insight into SSN bottlenecks, capability of assigning different victim pins spatially located across the pinout map by users, configurability for appending board models, as well as good accuracy for dominant SSN mechanisms. The assumption made is that the vertical structures tend to generate dominant SSN noise with technical and economical constraints. This has been proved the case in recent studies and industry seminars.

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Figure 12 shows simulated voltage sag using the lab bench setup condition, as compared to early measurement data.

Figure 12. Simulated Voltage Sag and Measured Sag Data Using the Same Bench Setup and Conditions. Note to Figure 12:

1. Top trace: measurement. Bottom trace: simulated The characteristics of sag waveform, ∆V, ∆T, ∆t, and τ sag, correlate reasonably well between simulated and measured data. Moreover, the simulation allows us to separate each SSN mechanism and to find the root cause, which is often difficult to untangle in the real world. Figure 13 shows three voltage curves, all representing voltage sag waveform at the far-end load. The first (top) is a fast-changing curve, simulated with an ideal PDN yet mutually coupled breakout, so the curve is the sole effect of crosstalk. The second curve is a slow varying oscillation, simulated with ideal breakout but with a frequency

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Figure 13. Simulated Contribution From PDN Only, Crosstalk Only and Combined PDN and Crosstalk In the spectrum domain, the correlation is also accomplished between theory and measurement. Figure 14 shows the simulated spectrum on quiet pin at the far-end load.

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Figure 14. Simulated Spectrum for Voltage Sag on a Quiet Pin Using the Same Experiment Setup as in Figure 8 To demonstrate the influence of the PDN impedance pole, it is overlaid on top of the sag spectrum as peak A, which matches the location of resonance frequency, fc, around 180 MHz, and is especially evident from the envelope formed by the skirt of spectral components. Features such as peak B and the slower-than-20-dB/decade roll-off are clearly seen from the simulated sag spectrum as well. Additional simulation also reveals that peak B moves to a higher frequency when the transmission line length between ball breakout and load is shortened. This confirms the nature of peak B that corresponds to a reflection of fast changing crosstalk. More simulation results can be found in Reference [1]. Since the simulation link is built according to our understanding of SSN phenomena in FPGA devices and systems, a good match of simulation to experiment demonstrates that our postulation about its cause mechanism has a sound basis. VI. Conclusion A systematic study is performed on SSN phenomenon in FPGA devices and systems from the perspective of time, frequency, and noise spectrum. Cross-correlation in three domains confirms the two dominant cause mechanisms in action. The first is frequency dependent PDN impedance, specifically impedance resonance caused by on-chip bypass capacitance and system PDN series inductance. The second is crosstalk from the package-PCB breakout region. Each mechanism shows its manifestation in a time-domain waveform. The frequency location match between the PDN impedance pole and resonance peak A in the spectrum demonstrates the fact that the on-chip bypass capacitance value in a dynamic operation has a similar value as that in the static mode extracted with VNA, making VNA measurement a valid method for on-chip decoupling characterization. A simple and practical SSN simulation method validates our postulations made on explanations to measurement data. It confirms that crosstalk is an embedment of noise on the quiet pin in addition to voltage oscillation generated by the PDN impedance peaking. Voltage sag is caused by these two distinct mechanisms imposing on quiet pin in different times and locations, whereas ground bounce arises mainly from crosstalk.

Acknowledgement The author would like to thank Anil Pannikkat, Kok Siang Ng, Hong Nien Foong, and Yee Huan Yew for great modeling support; Vadim Heyfitch, Khalid Ansari, CK Sung, Bonnie Wang, Jeff Tyhach, and Jon Long for insightful discussions; John Xie for his encouragement to this study; and Tarun Verma for management support and vision in this field. Reference [1]. Hong Shi, “Simultaneous Switching Noise in FPGA and Structure ASIC Devices, Methodology for Analysis, Modeling, and Validation”, Accepted by ECTC 2006, May 2006, San Diego, CA.

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