Simulation with Verilog-XL

Verilog-XL is a great tool to perform digital logic design. It lets you perform logic design at the functional level. This enables a designer to test his logic without going into gory details of the transistor level operations. More details about this tool and its syntax can be found by using the openbk command at the prompt. This section will enable you to create a verilog file for your design (an example considered here is that of an inverter). You will also simulate this inverter using Cadence.

To create verilog file, click on the File -> New -> Cell view in the Library Manager Window. A pop-up window will appear.

Type in functional on the View, choose Type and Application as shown above. And then, click on OK button. After this, you will functional in View of Library Manager Window.

To edit verilog file, open functional view. An verilog.v file will pop-up as shown below.

This is an example for inverter.

Save the functional view and close it. Cadence will tell you in the CIW whether the functional view is successfully parsed (no syntax errors) or not.

To open Verilog-XL, with the schematic window of the cell you want to simulate open, select Launch --> Simulation --> Verilog-XL

A pop up window will appear.

Note that View name must be functional because you are going to do verilog simulation using functional view, not schematic.

After click OK, you will see new window as shown below.

Go to Setup -> Record signals in Verilog-XL Integration window.

Choose all items like the figure above. And then click OK.

To simulate verilog file, you need a stimulus file to assign input signal pulse.

Go to Stimulus-> Verilog

Stimulus Options window will pop up.

To edit this stimulus file, choose Mode as Edit and click OK.

You will see an editing window. From this window, you are able to describe input signal pulses you want. Note that time unit is n sec. It means that #25 is corresponding to 25n sec.

Save it and quit.

Next, click on the left button in the list of buttons provided in the Verilog-XL Integration Control Window as shown in figure below, select Simulation -> Start Interactive.

If there are no errors, you will see a figure below.

Click on the Continue icon (second top icon in the second column) in the Verilog-XL Integration Control window or select Simulation -> Continue.

Upon completion, your Verilog-XL Integration Control Window should look like this.

Click on the View Waveforms Icon( >>) in the window. This will open up SimVision which shall look like the window below.

Select File -> OpenDatabase , a pop-up window of open database as shown below, go to directory 'inv.run1/RunObject.0/ShmDir/shm.db/" and highlight 'shm.trn' and press 'Open' button to open it.

A window as shown in the picture below will appear.

Click on the 'test' and you'll see two signals, which are 'inp' and 'out', in the bottom panel.

Clicking on each signal, you should be able to plot the signals.