simulation user guide (ug072) - achronix contains the post-route (or final) simulation project area...

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Simulation User Guide (UG072)

Achronix FPGAs

http://www.achronix.com


2 www.achronix.com Achronix FPGAs

Copyrights, Trademarks and DisclaimersCopyright © 2018 Achronix Semiconductor Corporation. All rights reserved. Achronix, Speedcore, Speedster, and ACE are trademarks of Achronix Semiconductor Corporation in the U.S. and/or other countries All other trademarks are the property of their respective owners. All specifications subject to change without notice.

NOTICE of DISCLAIMER: The information given in this document is believed to be accurate and reliable. However, Achronix Semiconductor Corporation does not give any representations or warranties as to the completeness or accuracy of such information and shall have no liability for the use of the information contained herein. Achronix Semiconductor Corporation reserves the right to make changes to this document and the information contained herein at any time and without notice. All Achronix trademarks, registered trademarks, disclaimers and patents are listed at http://www.achronix.com/legal.

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Table of Contents

Chapter - 1: Simulation Software Tool Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Chapter - 2: Simulation Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Chapter - 3: General Project Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

User Design Project Directory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

ACE Installation Library Directory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

ACE Extension I/O Ring Library Directory Structure (Speedcore Only) . . . . . . . . . . . . . . . . 11

Chapter - 4: General RTL Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Chapter - 5: General Gate-Level Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . 13Chapter - 6: General Post-Route Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . 14Chapter - 7: Example Design Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Chapter - 8: Synopsys VCS Simulator Example . . . . . . . . . . . . . . . . . . . . . . . . . . 19

RTL Simulation in VCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Step 1 – Run the VCS Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Step 2 – Start the Simulation GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Step 3 – Open the Simulation Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Step 4 – Reset the Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Step 5 – Add Signals to the Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Step 6 – View the Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Gate-Level Simulation in VCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Step 1 – Create the Synthesis Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Step 2 – Synthesize the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Step 3 – Run the VCS Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Post-Route Simulation in VCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Step 1 – Create the ACE Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Step 2 – Run Place and Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Step 3 – Run the VCS Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Chapter - 9: Cadence Incisive Simulator Example . . . . . . . . . . . . . . . . . . . . . . . . 26RTL Simulation in Incisive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Step 1 – Invoke the Incisive Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26


Step 3 – Run the Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29




Step 3 – Run the Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Step 4 – View the Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Step 5 – View Console Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Gate-Level Simulation in Incisive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Step 1 – Create the Synthesis Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32


Step 3 – Run Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Step 4 – View Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Post-Route Simulation in Incisive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Step 1 – Create the ACE Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33


Step 3 – Run Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Step 4 – View Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Chapter - 10: Mentor Questa Sim Simulator Example . . . . . . . . . . . . . . . . . . . . . . 35RTL Simulation in Questa Sim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Step 1 - Create the Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Step 2 - Initialize the Work Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Step 3 - Create the File List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Step 4 - Compile the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Step 5 – Prepare the Simulation Run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Step 6 – Set up the Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37



Gate-Level Simulation in Questa Sim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Step 1 – Create the Synthesis Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41


Step 3 – Set up the Simulation Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Step 4 – Initialize the Work Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Step 5 – Create the File List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Step 6 – Compile the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42


Post-Route Simulation in Questa Sim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Step 1 – Create the ACE Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42


Step 3 – Set up the Simulation Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Step 4 – Initialize the Work Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Step 5 – Create the File List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Step 6 – Compile the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43




Step 6 – Compile the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43


Chapter - 11: Aldec Riviera Simulator Example . . . . . . . . . . . . . . . . . . . . . . . . . . . 45RTL Simulation in Riviera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Step 1 – Create Simulation Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Step 2 – Create a .do File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45



Step 5 – Open the Workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Step 6 – Initialize the Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47



Gate-Level Simulation in Riviera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Step 1 – Create the Synthesis Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50


Step 3 – Create a Workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50


Step 5 – View the Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Post Route Simulation in Riviera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Step 1 – Create the ACE Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51


Step 3 – Create the Workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51


Step 5 – View the Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53




Chapter - 1: Simulation Software Tool FlowThe Achronix tool suite includes synthesis and place-and-route software that maps RTL designs (VHDL or Verilog) into Achronix devices. In addition to synthesis and place-and-route functions, the Achronix software tools flow also supports simulation at several flow steps (RTL, Synthesized Netlist, and Post Place-And-Routed Netlist), as shown in the figure below.

Functional simulation can be done at the following stages:

Functional RTL level (referred to as RTL simulation)

Gate-level, post-synthesis netlist (referred to as gate-level simulation)

Gate-level, post-place-and-route netlist (referred to as post-route simulation:

The following diagram shows the three stages of simulation in the context of the Achronix software tool flow.




Figure 1: Simulation Flow




Chapter - 2: Simulation LibrariesThis guide covers simulation for all Achronix devices. It is incumbent on the user to select the correct technology library. The text in this user guide contains references to . The user should simply replace this <technology>with the abbreviated version of the technology name as specified in the table below, e.g., . 22i

Table 1: Achronix Simulation Libraries

Technology Abbreviation Simulation Model File Name Device Families

Speedster22i 22i 22i_simmodels.v Speedster FPGAs

Speedster16t 16t 16t_simmodels.v Speedcore eFPGAs




Chapter - 3: General Project Setup

User Design Project Directory StructureThe following project directory structure is used in this example:

Directory Description

<project_dir> root directory for the user design project

/src /src

/rtl Contains source RTL for the user design

/mem_init_files Contains memory initialization files for BRAMs or LRAMs

/tb Contains the simulation testbench for the user design

/syn Contains the synthesis project area and output

/ace Contains the ACE project area and output

For Mentor Questasim

/questasim-rtl Contains the RTL simulation project area and output

/questasim-gate Contains the gate-level simulation project area and output

/questasim-final Contains the post-route (or final) simulation project area and output

For Aldec Riviera

/riviera-rtl Contains the RTL simulation project area and output

/riviera-gate Contains the gate-level simulation project area and output

/riviera-final Contains the post-route (or final) simulation project area and output

For Cadence Incisive

/incisive-rtl Contains the RTL simulation project area and output

/incisive-gate Contains the gate-level simulation project area and output

/incisive-final Contains the post-route (or final) simulation project area and output





For Synopsis VCS

/vcs-rtl Contains the RTL simulation project area and output

/vcs-gate Contains the gate-level simulation project area and output

/vcs-final Contains the post-route (or final) simulation project area and output

ACE Installation Library Directory StructureFiles used in the ACE installation are located under the ACE install directory as follows:


<ace_install_dir> Directory path to where ACE is installed.

/libraries Root directory for simulation and other libraries provided by Achronix. This is the top-level library include directory (+incdir+) for Achronix device libraries.

/device_models Contains the technology-specific top-level Achronix device library include files for simulation and synthesis.

ACE Extension I/O Ring Library Directory Structure (Speedcore Only)If the user design instantiates ASIC I/O ring logic outside the Speedcore instance, files from the ACE extensions directory must be included from the file structure below:


<ace_ext_dir> Directory path to the ACE extensions directory being used (should match the $ACE_EXT_DIR environment variable setting).

/libraries Root directory for simulation and other libraries for the ASIC I/O ring provided by the ASIC integrator. This is the top-level library include directory (+incdir+) for ASIC I/O ring libraries.

/sim Contains the technology-specific top-level ASIC I/O ring library include file for simulation.




1.

2.

3.

a.

b.

c.

d.

e.

4.

Chapter - 4: General RTL Simulation FlowTo perform RTL simulation:

The user must first create a directory under .<sim_tool>-rtl <project_dir>/src/

Then change directories (cd) to the new directory (make it the <project_dir>/src/<sim_tool>-rtlcurrent working directory) to launch subsequent simulator commands from. This step is critical for the simulator to find relative paths to mem_init_file parameters set to "../mem_init_files

"./<mem_init_file>.txt

Create the simulation project files and add the source files and library paths. The end user must add the following to the simulator project:

The top-level Achronix technology-specific simulation library include directory path (incdir): <ace_install_dir>/libraries

The top-level Achronix technology-specific simulation library include file, found in <ace_install_dir>/libraries/device_models/<technology>_simmodels.v

(Speedcore only) Optionally, the top-level ASIC I/O ring technology-specific simulation library include file, found in <ace_ext_dir>/libraries/sim/<ioring_library_file>.

The behavioral RTL (Verilog or VHDL) source files for the user design

The top-level simulation testbench (Verilog or VHDL) files

Run the simulation and observe the output waveform.




1.

2.

3.

4.

a.

b.

c.

d.

e.

5.

Chapter - 5: General Gate-Level Simulation FlowTo perform gate-level simulation:

The end user must first create a synthesis project in the directory for <project_dir>/src/syn/Synplify Pro to compile and synthesize the source behavioral RTL files to map to Achronix technology. The output of the synthesis tool (Synplify Pro) is a mapped gate-level Verilog netlist in the format that the ACE tool accepts as input for the back-end place-and-route flow. Synplify Pro outputs the synthesized gate-level netlist with the extension.*.vm

The user must first create a directory under .<sim_tool>-gate <project_dir>/src/

Then change directories (cd) to the new directory (make it <project_dir>/src/<sim_tool>-gatethe current working directory) to launch subsequent simulator commands from. This step is critical for the simulator to find relative paths to mem_init_file parameters set to "../mem_init_files


Create the simulation project files and add the source files and library paths. The end user must add the following to the simulator project:



(Speedcore only) Optionally, the top-level ASIC I/O ring technology-specific simulation library include file, found in <ace_ext_dir>/libraries/sim/<ioring_library_file>.v

The synthesized gate-level Verilog netlist file ( ) for the user design*.vm


Run the simulation and observe the output waveform




1.

2.

3.

4.

a.

b.

c.

d.

e.

5.

Chapter - 6: General Post-Route Simulation FlowTo perform post-route simulation:

The end user must first create a project in the directory for ACE to place <project_dir>/src/ace/and route the source synthesized gate-level Verilog netlist file ( file output by Synplify Pro) for the *.vmuser design. The user design must be run through the place-and-route flow in the ACE tool, and the

flow step must be run to output the post-route gate-level netlist from Generate Final Simulation NetlistACE. The post-route gate-level netlist represents the user design logic after all transformations and optimizations made by the tools flow prior to bitstream generation. ACE outputs the post-route gate-level netlist into the following location: <project_dir>/src/ace/<active_impl_dir>/output

. This file is encrypted using industry-standard Verilog encryption techniques which /<design>_final.vare supported by all simulators in the Achronix software tool flow.

The user must first create a directory under .<sim_tool>-final <project_dir>/src/

Then change directories (cd) to the new directory (make it <project_dir>/src/<sim_tool>-finalthe current working directory) to launch subsequent simulator commands from. This step is critical for the simulator to find relative paths to mem_init_file parameters set to "../mem_init_files


Create the simulation project files and add the source files and library paths The end user must add the following to the simulator project:



(Speedcore only) Optionally, the top-level ASIC I/O ring technology-specific simulation library include file, found in <ace_ext_dir>/libraries/sim/<ioring_library_file>.v

The encrypted post-route gate-level Verilog netlist file ( ) for the user design.*_final.v


Run the simulation and observe the output waveform.




Chapter - 7: Example Design DescriptionThe example design used in various simulation flows described in this user guide instantiates a true-dual port RAM (BRAMTDP) with porta write/read width and portb write/read width being 20 bits. The data is read from a file which is specified through the mem_init_file parameter and the data output is observed on rom_file.txtportb.

bram_example.v

module bram_example

(

input clk,

input rst_latch,

input rst_reg,

input outce,

input rden,

input wren,

input [1:0] we,

input [13:0] rdaddr,

input [13:0] wraddr,

input [19:0] din,

output reg [19:0] dout

);

reg rst_latch_reg = 'h0;

reg rst_reg_reg = 'h0;

reg outce_reg = 'h0;

reg rden_reg = 'h0;

reg wren_reg = 'h0;

reg [1:0] we_reg = 'h0;

reg [13:0] rdaddr_reg = 'h0;

reg [13:0] wraddr_reg = 'h0;

reg [19:0] din_reg = 'h0;

wire [19:0] dout_int;

always @(posedge clk)

begin

rst_latch_reg <= rst_latch;

rst_reg_reg <= rst_reg;

outce_reg <= outce;

rden_reg <= rden;

wren_reg <= wren;

we_reg <= we;

rdaddr_reg <= rdaddr;

wraddr_reg <= wraddr;

din_reg <= din;

dout <= dout_int;

end

BRAMTDP

#(.porta_write_width(20),

.porta_read_width(20),

.portb_write_width(20),




.portb_read_width(20),

.initd_00(256'hFFFFEEEEDDDDCCCCBBBBAAAA9999888877776666555544443333222211110000),

.initd_01(256'h0),

.initd_02(256'h0),

.initd_03(256'h0),

.initd_04(256'h0),

.initd_05(256'h0),

.initd_06(256'h0),

.initd_07(256'h0),

.initd_08(256'h0),

.initd_09(256'h0),

.initd_10(256'h0),

.initd_11(256'h0),

.initd_12(256'h0),

.initd_13(256'h0),

.initd_14(256'h0),

.initd_15(256'h0),

.initd_16(256'h0),

.initd_17(256'h0),

.initd_18(256'h0),

.initd_19(256'h0),

.initd_20(256'h0),

.initd_21(256'h0),

.initd_22(256'h0),

.initd_23(256'h0),

.initd_24(256'h0),

.initd_25(256'h0),

.initd_26(256'h0),

.initd_27(256'h0),

.initd_28(256'h0),

.initd_29(256'h0),

.initd_30(256'h0),

.initd_31(256'h0),

.initd_32(256'h0),

.initd_33(256'h0),

.initd_34(256'h0),

.initd_35(256'h0),

.initd_36(256'h0),

.initd_37(256'h0),

.initd_38(256'h0),

.initd_39(256'h0),

.initd_40(256'h0),

.initd_41(256'h0),

.initd_42(256'h0),

.initd_43(256'h0),

.initd_44(256'h0),

.initd_45(256'h0),

.initd_46(256'h0),

.initd_47(256'h0),

.initd_48(256'h0),

.initd_49(256'h0),

.initd_50(256'h0),

.initd_51(256'h0),




.initd_52(256'h0),

.initd_53(256'h0),

.initd_54(256'h0),

.initd_55(256'h0),

.initd_56(256'h0),

.initd_57(256'h0),

.initd_58(256'h0),

.initd_59(256'h0),

.initd_60(256'h0),

.initd_61(256'h0),

.initd_62(256'h0),

.initd_63(256'h0),

.initp_0(256'h0E4),

.initp_1(256'h0),

.initp_2(256'h0),

.initp_3(256'h0),

.initp_4(256'h0),

.initp_5(256'h0),

.initp_6(256'h0),

.initp_7(256'h0),

.initpx_0(256'h0),

.initpx_1(256'h0),

.initpx_2(256'h0),

.initpx_3(256'h0),

.initpx_4(256'h0),

.initpx_5(256'h0),

.initpx_6(256'h0),

.initpx_7(256'h0),

ìfdef ALDEC

.mem_init_file("rom_file.txt"),

èlse

.mem_init_file("../mem_init_files/rom_file.txt")) //rom_file.txt has to be in the

directory relative to where the simulation tool is invoked for all

//simulators described in this

document except for Aldec simulator

èndif

X_BRAMTDP

(.clka(1'b0),

.dina(16'h0),

.dinpa(2'b0),

.dinpxa(2'b0),

.addra(14'h0),

.wea(2'b0),

.pea(1'b0),

.rstrega(1'b0),

.rstlatcha(1'b0),

.outregcea(1'b0),

.clkb(clk),

.dinb(16'h0),

.dinpb(2'h0),

.dinpxb(2'h0),

.addrb({rdaddr_reg[9:0], 4'h0}),




.web(2'b0),

.peb(rden_reg),

.rstregb(rst_reg_reg),

.rstlatchb(rst_latch_reg),

.outregceb(outce_reg),

.douta(),

.doutpa(),

.doutpxa(),

.doutb({dout_int[18:15],dout_int[13:10],dout_int[8:5],dout_int[3:0]}),

.doutpb({dout_int[14],dout_int[4]}),

.doutpxb({dout_int[19],dout_int[9]}));

endmodule

Note

The has to be present in the mem_init_files directory, relative to where the simulation rom_file.txttool is in invoked for all simulators except Aldec Rivera. Otherwise the simulators will not be able to find the file and will error out. For Aldec Riviera, refer to the steps described in Aldec Simulator .txtExample regarding rom_file.txt.




Chapter - 8: Synopsys VCS Simulator Example

RTL Simulation in VCSIn order to run the RTL simulation using the VCS tool, the following steps have to be followed:

Step 1 – Run the VCS SimulatorRun the simulator using the command, including the libraries path, path to , vcs <technology>_simmodels.vtop-level RTL file and testbench as shown below:

vcs +vcs+lic+wait -lca -debug_pp +incdir+<ace_install_dir>/libraries/ <ace_install_dir>

/libraries/device_models/<technology>_simmodels.v <project_dir>/src/rtl/bram_example.v

<project_dir>/src/tb/tb_bram_example.v -sverilog -R -l vcs.log

Where is one of the abbreviated options from the table in the <technology> Simulation Libraries (see page 9)section.

Table 2: Command Options

Options Required Description

-lca Yes IEEE encryption flow in VCS requires this option

-debug_pp No

Creates a VPD file (when used with the VCS system task $vcdpluson) and enables DVE for post-processing a design. Using-debug-pp can save compilation time by eliminating the overhead of compiling with -debug and -debug_all.

-sverilog Yes Supports System Verilog features.

-R NoRun the executable file immediately after VCS links together the executable file. This option is required so that .vpd file is generated which is used for analyzing waveform.

-l NoLog file name can be specified with this option where VCS records compilation messages. Runtime messages are also included in the log file if -R option is used along with -l.

+vcs+lic+wait No Tells VCS to wait for network license if none is available.

+define+CMEM_READBACK No

This option is to be used only when reading back configuration memory (CMEM) contents during WGL simulations. To reduce simulation time for CMEM readback, use the command line option: -Xalex=0x10000000




Step 2 – Start the Simulation GUIAfter successful completion of compilation and simulation above, a GUI called Discovery Verification Environment (DVE) can be used to post-process a design. In this example is tb_bram_example.vpdgenerated after completion of Step 1. DVE can be opened using the following command:

dve &

Figure 2: DVE Main Window

Step 3 – Open the Simulation DatabaseOpen the database file file:tb_bram_example.vpd




Figure 3: Opening the Simulation Database

Step 4 – Reset the LayoutClick on the Hier tab at the bottom left of the window and reset layout by selecting Window → Load Layout →

:Reset Layout




Figure 4: Resetting the Layout

Step 5 – Add Signals to the WaveformSelect the required signals from the DUT and add them to the waveform by right-clicking and selecting Add to

:Waves → New Wave View




Figure 5: Adding Signals to the Waveform

Step 6 – View the Simulation ResultsWaveforms can be viewed and analyzed as shown below:




Figure 6: Viewing the Waveforms

Gate-Level Simulation in VCSFor gate-level simulation, a synthesized netlist has to first be generated using Synplify Pro before performing the simulation..

Step 1 – Create the Synthesis ProjectCreate a new project in Synplify under , include <project_dir>/src/syn <ace_install_dir>/libraries

followed by the RTL design files and constraint files./device_models/<technology>_synplify.v


Step 2 – Synthesize the DesignSynthesize the design using Synplify Pro. Synplify Pro generates a gate-level netlist with extension, for the .vmexample design, the file is generated.<project_dir>/src/syn/rev_acx/bram_example.vm

Step 3 – Run the VCS SimulatorTo run the gate-level simulation, use the same command as described in RTL Simulation in VCS (see page 19)above except that the gate-level simulation uses the mapped netlist instead of source RTL bram_example.vmfiles.





/libraries/device_models/<technology>_simmodels.v <project_dir>/src/syn/rev_2

/bram_example.vm <project_dir>/src/tb/tb_bram_example.v -sverilog -R -l vcs.log


Complete the process by following Steps 2 to the end of .RTL Simulation in VCS (see page 19)

Post-Route Simulation in VCSFor post-route simulation, the synthesized gate-level neltist must first be run through place and route using ACE.

Step 1 – Create the ACE ProjectCreate a new project in ACE under . Add the gate-level netlist <project_dir>/src/ace bram_example.vmgenerated by Synplify plus the constraint files.

Step 2 – Run Place and RouteRun the place and route flow, including the 'Generate Final Simulation Netlist' step to obtain a post-route netlist. In this example, the netlist would be generated under <project_dir>/src/ace/impl_1/output

./bram_example_final.v

Step 3 – Run the VCS SimulatorRun the post-route simulation using the same command as used in RTL and gate-level simulation using the final netlist:


/libraries/device_models/<technology>_simmodels.v <project_dir>/src/ace/impl_1/output

/bram_example_final.v <project_dir>/src/tb/tb_bram_example.v -sverilog -R -l vcs.log


Complete the process by following Steps 2 to the end of .RTL Simulation in VCS (see page 19)

Note

In post-route simulations, the user design netlist output from ACE is encrypted. Therefore, only signals from the testbench are observable. The post-route simulation results should functionally match exactly with the gate-level simulation results. However, if an issue is seen in post-route simulation, run a gate-level simulation to debug the issue.




Chapter - 9: Cadence Incisive Simulator Example

RTL Simulation in IncisiveIn order to run the RTL simulation using the Cadence Incisive tool, follow the steps below:

Step 1 – Invoke the Incisive ToolInvoke the Cadence tool by specifying the path where the tool is installed using the command and include irunthe libraries path, path to , top-level RTL file, and testbench as shown below:<technology>_simmodels.v

irun -access +rwc +incdir+<ace_install_dir>/libraries/ /<ace_install_dir>/libraries

/device_models/<technology>_simmodels.v <project_dir>/src/rtl/bram_example.v <project_dir>

/src/tb/tb_bram_example.v -gui -sv


Table 3: Command Options

Options Required Description

-access +rwc Yes Turn on read, write and/or connectivity access

-gui No Invoke the GUI

-sv Yes Supports System Verilog constructs

+define+CMEM_READBACK No

This option is to be used only when reading back configuration memory (CMEM) contents during WGL simulations.

Note

Simulating CMEM readback function takes on the order of hours to complete with the Incisive simulator.

When the compilation and elaboration of the design completes successfully, the following message is displayed at the end of created in the same directory where the tool is run. Also the graphical debug irun.logmenvironment, the SimVision GUI, is launched as shown in Step 2.

Building instance specific data structures.

Loading native compiled code: .................... Done

Design hierarchy summary:

Instances Unique

Modules: 731 221

Resolved nets: 3 1

Registers: 4404 552




Scalar wires: 8630 -

Expanded wires: 1537 45

Vectored wires: 1181 -

Named events: 48 4

Always blocks: 2758 249

Initial blocks: 328 79

Cont. assignments: 2542 1202

Pseudo assignments: 675 368

Simulation timescale: 1ps

Writing initial simulation snapshot:

ncsim: *W,DSEM2009: This SystemVerilog design is simulated as per IEEE 1800-2009

SystemVerilog simulation semantics.

Use -disable_sem2009 option for turning off SV 2009 simulation semantics.

Step 2 – Add Signals to the WaveformFrom the Design Browser pane in the SimVision main window, scroll down to and select the testbench, tb_bram_example.

Figure 7: SimVision Main Window

From the Objects view, select the DUT and all of the required signals. Right-click, select Send to Waveform to add the signals.Window





The Waveform window will open as shown below.




Figure 9: Incisive Waveform Window

Step 3 – Run the SimulationRun simulation by selecting .Simulation → Run




Figure 10: Running Simulation

Step 4 – View the WaveformSelect View Tab and Zoom Full X. The waveform will be displayed as shown below.




Figure 11: SimVision Waveform Window

Step 5 – View Console MessagesThe console window displays messages from the testbench. It indicates that the test passed successfully and the simulation finish time.

Figure 12: SimVision Console Window




Gate-Level Simulation in IncisiveFor gate-level simulation, a synthesized netlist has to first be generated using Synplify Pro before performing the simulation..





Rename the gate-level netlist extension from to so that the cadence simulator understands that it is a .vm .vVerilog file. Otherwise, the cadence simulator tool will error out. The example netlist is renamed to

.bram_example_gate.v

Step 3 – Run SimulationTo run the gate-level simulation, use the same command as described in the RTL Simulation in Incisive (see

section, except that the gate-level simulation uses the mapped netlist file page 26) bram_example_gate.vinstead of source RTL files.

irun -access +rwc +incdir+<ace_install_dir>/libraries/ <ace_install_dir>/libraries

/device_models/<technology>_simmodels.v <project_dir>/src/syn/rev_acx/bram_example_gate.v

<project_dir>/src/tb/tb_bram_example.v -gui -sv


Step 4 – View Simulation ResultsFollow the same steps described in (Steps 2 to 5) for loading the RTL Simulation in Incisive (see page 26)waveform and viewing the results. When the DUT is selected, the gate-level netlist signals appear as shown below.





Post-Route Simulation in IncisiveFor post-route simulation, the synthesized gate-level neltist must first be run through place and route using ACE.




Step 3 – Run SimulationRun the post-route simulation using the same command as was used in RTL and gate-level simulation.

irun -access +rwc +incdir+<ace_install_dir>/libraries/ <ace_install_dir>/libraries

/device_models/<technology>_simmodels.v <project_dir>/src/ace/impl_1/output

/bram_example_final.v <project_dir>/src/tb/tb_bram_example.v -gui -sv





Step 4 – View Simulation ResultsIn post-route simulation, when DUT is selected, no signals are displayed since the post-route netlsit file is encrypted. Instead, select the signals under tb_bram_example and follow the same steps described in RTL

(Steps 2 to 5) for loading the waveform and viewing the results.Simulation in Incisive (see page 26)





Chapter - 10: Mentor Questa Sim Simulator Example

RTL Simulation in Questa SimStep 1 - Create the ProjectCreate the Questa Sim RTL simulation project directory under , then <project_dir>/src/questasim-rtlchange directories (cd) to make it the current working directory to launch all simulator tools from.

Step 2 - Initialize the Work LibraryInitialize the simulator work library using the following Questa Sim command:

vlib <project_dir>/src/questasim-rtl/work

Step 3 - Create the File ListCreate a file to configure the project defines, include directories, and source files. If using VHDL, filelist.fthe file should appear similar to the following example:

Warning!

VHDL simulation is only supported at the RTL simulation level. Achronix does not provide the VHDL wrapper libraries for the Verilog library primitives. Behavioral VHDL is recommended. For Achronix IP, such as BRAM or DSP blocks, the ACE GUI provides IP configuration tools which can generate a VHDL wrapper on top of the configured Verilog primitive wrapper.

Example vhdl_filelist.f

+define+ACX_ARCH_SPEEDSTER<technology>

+define+SIMSTEP_rtl

+incdir+<project_dir>/src/tb

+incdir+<project_dir>/src/rtl

+incdir+<ace_install>/libraries

+incdir+<ace_ext_dir>/libraries

<ace_install>/libraries/device_models/<technology>_simmodels.v

<project_dir>/src/rtl/bram_example.vhd

<project_dir>/src/tb/tb_bram_example.vhd


If using Verilog, the file should appear similar to the following example:filelist.f

Example verilog_filelist.f


+define+SIMSTEP_rtl









<project_dir>/src/rtl/bram_example.v

<project_dir>/src/tb/tb_bram_example.v

+libext+.v


Step 4 - Compile the DesignBefore the design can be simulated, it must be compiled. If using VHDL, use the following command to compile the design:

vcom -work <project_dir>/src/questasim-rtl/work -f <project_dir>/src/questasim-rtl

/vhdl_filelist.f

If using Verilog, use the following command to compile the design:

vlog -sv -work <project_dir>/src/questasim-rtl/work -mfcu -f <project_dir>/src/questasim-

rtl/verilog_filelist.f

Table 4: Important Command-Line Options

Option Description

-mfcu Multi-file compilation unit, all files in command line make up a compilation unit.

-sv Enable SystemVerilog features and keywords

Step 5 – Prepare the Simulation RunOpen the simulator and load the compiled design using the following command:

vsim -novopt -lib <project_dir>/src/questasim-rtl/work -gui

In the simulator GUI, select to prepare the simulation:Simulate → Start Simulation...




Figure 15: Questa Sim GUI

Step 6 – Set up the WaveformIn the Start Simulation dialog, select the testbench file to run, and click :tb_bram_example.v OK




Figure 16: Start Simulation Dialog Box

Select the signals to monitor and add them to the waveform by selecting DUT, selecting the desired signals, and then right-clicking and selecting .Add Wave




Figure 17: Selecting Signals to Observe

Step 7 – Run the SimulationFrom the simulator GUI, select to start the simulation:Simulate → Run → Run -All




Figure 18: Starting the Simulation Run

Step 8 – View the WaveformSimulation results are written to the waveform viewer for review:




Figure 19: Questa Sim Waveform Viewer

Gate-Level Simulation in Questa SimFor gate-level simulation, a synthesized netlist has to first be generated using Synplify Pro before performing the simulation..





Step 3 – Set up the Simulation ProjectCreate a Questa Sim gate-level simulation project directory under , <project_dir>/src/questasim-gatethen enter this directory to make it the current working directory to launch all simulator tools from.




Step 4 – Initialize the Work LibraryInitialize the simulator work library using the following Questa Sim command:

vlib <project_dir>/src/questasim-gate/work

Step 5 – Create the File ListCreate a file to configure the project defines, include directories, and source files:filelist.f



+define+SIMSTEP_gate






<project_dir>/src/syn/rev_acx/bram_example.vm


+libext+.v


Step 6 – Compile the DesignCompile the design for simulation using the following command:

vlog -sv -work <project_dir>/src/questasim-gate/work -mfcu -f <project_dir>/src/questasim-

gate/verilog_filelist.f


vsim -novopt -lib <project_dir>/src/questasim-gate/work -gui

Complete the process by following Steps 6 to the end of above.RTL Simulation in Questa Sim (see page 35)

Post-Route Simulation in Questa SimFor post-route simulation, the synthesized gate-level neltist must first be run through place and route using ACE.


Step 2 – Run Place and Route






Step 3 – Set up the Simulation ProjectCreate the Questa Sim post-route simulation project directory under <project_dir>/src/questasim-final, then enter this directory to make it the current working directory to launch all simulator tools from.

Step 4 – Initialize the Work LibraryInitialize the simulator work library using the following Questa Sim command:

vlib <project_dir>/src/questasim-final/work

Step 5 – Create the File ListCreate a file to configure the project defines, include directories, and source files:filelist.f



+define+SIMSTEP_final






<project_dir>/src/ace/impl_1/output/bram_example_final.v


+libext+.v


Step 6 – Compile the DesignCompile the design for simulation using the following command:

vlog -sv -work <project_dir>/src/questasim-gate/work -mfcu -f <project_dir>/src/questasim-

final/verilog_filelist.f


vsim -novopt -lib <project_dir>/src/questasim-final/work -gui

Complete the process by following Steps 6 to the end of above.RTL Simulation in Questa Sim (see page 35)




Note

In post-route simulations, the user design netlist output from ACE is encrypted. Therefore, only signals from the testbench are observable. The post-route simulation results should functionally match exactly with the gate-level simulation results. However, if an issue is seen in post-route simulation, run a gate-level simulation to debug the issue.




Chapter - 11: Aldec Riviera Simulator Example

RTL Simulation in RivieraStep 1 – Create Simulation DirectoryCreate a RivieraSim RTL simulation project directory under , then change directories <project_dir>/src/(cd) to make as the current working directory to launch Riviera from.<project_dir>/src

Step 2 – Create a .do FileCreate the file . The following commands are used in the file to riviera_script.do riviera_script.docompile and simulate the design.

#Creates a workspace called riviera_rtl_workspace in current directory. It automatically

changes directory to ./riviera_rtl_workspace

workspace.create riviera_rtl_workspace ./

#Creates a design called bram_example

workspace.design.create bram_example ./

#Save workspace

workspace.save

#Copy the rom_file.txt to riviera_rtl_workspace directory

cp ../rtl/rom_file.txt .

#Add the design RTL

design.file.add ../rtl/bram_example.v

design.file.add ../tb/tb_bram_example.v

design.file.add /<ace_install_path>/libraries/device_models/<technology>_simmodels.v

#Compile design

#design.compile test

alog -work testbram -incdir {/<ace_install_path>/libraries/} -msg 5 -dbg -protect 0 -

quiet {/<project_dir>/src/rtl/bram_example.v} {/<project_dir>/src/tb/tb_bram_example.v} {

/<ace_install_path>/libraries/device_models/<technology>_simmodels.v}

#Initialize design

#design.simulation.initialize tb_bram_example

asim -lib testbram -dbg -t 0 -dataset {/<project_dir>/src/results/testbram} -datasetname

{sim} tb_bram_example

#Run

run -all

#Saves workspace

workspace.close -save




quit


Step 3 – Run the SimulationRun the script to compile and simulate the design using the following command. The riviera_script.doresults are then copied to the file.sim.log

/<riviera_install_path>/riviera-pro-2014.06-x86_64/bin/vsimsa -do ./riviera_script.do >

sim.log

Once simulation is complete, the displays the following message:sim.log

Step 4 – View the WaveformIn Riviera, in order to view the waveform, simulation has to be rerun. Change the directory to

. Invoke the Riviera GUI from this directory using the following command./riviera_rtl_workspace

/<riviera_install_path>/riviera-pro-2014.06-x86_64/bin/riviera &

Step 5 – Open the WorkspaceAfter the Riviera GUI starts up, open the workspace file by selecting riviera_rtl_workspace.rwsp File →

.Open → Workspace




Figure 20: Riviera Workspace

Copy the file to the previously created design directory .rom_file.txt /bram_example

Note

Copying the to design directory bram_example is important; otherwise, when re-rom_file.txtrunning simulation for viewing waveform, the will not be found.rom_file.txt

Step 6 – Initialize the SimulationInitialize simulation as shown below by right-clicking on the file in the Libraries pane and tb_bram_example.vselecting .Initialize Simulation




Figure 21: Initializing Simulation

Step 7 – Add Signals to the WaveformAdd signals to the waveform by right-clicking the DUT in the Hierarchy pane and selecting Add to → Waveform..




Figure 22: Adding the Waveform

Step 8 – View the WaveformClick the and button to view the waveform.Restart Run -all

Figure 23: Viewing the Waveform




Gate-Level Simulation in RivieraFor gate-level simulation, a synthesized netlist has to first be generated using Synplify Pro before performing the simulation..





Step 3 – Create a WorkspaceTo run the gate-level simulation, create a workspace and run the script as described in RTL Simulation in Riviera

except that the gate-level simulation uses the mapped netlist(see page 45)

#Creates a workspace called riviera_gate_workspace in current directory. It automatically

changes directory to ./riviera_rtl_workspace

workspace.create riviera_gate_workspace ./



workspace.save

#Copy the in/exp files


#Add the gate netlist

design.file.add ../syn/rev_2/bram_example.vm



#Compile design





#Initialize design




#Run

run -all




#Saves workspace


quit


Step 4 – Run the SimulationFollow Step 3 of to run simulation.RTL Simulation in Riviera (see page 45)

Step 5 – View the ResultsFollow Steps 4 to the end of to view the waveform.RTL Simulation in Riviera (see page 45)

Post Route Simulation in RivieraFor post-route simulation, the synthesized gate-level neltist must first be run through place and route using ACE.




Step 3 – Create the WorkspaceRun the post-route simulation by creating a workspace called final and run the script as described in the RTL

section except that the post-route simulation uses the final netlist.Simulation in Riviera (see page 45)

#Creates a workspace called riviera_final_workspace in current directory. It

automatically changes directory to ./riviera_rtl_workspace

workspace.create riviera_final_workspace ./



workspace.save

#Copy the in/exp files

cp ../tb/testvectors.in .

cp ../tb/testvectors.exp .


#Add the final netlist

design.file.add ../ace/impl_1/output/bram_example_final.v






#Compile design





#Initialize design




#Run

run -all

#Saves workspace


quit


Step 4 – Run the SimulationFollow Step 3 of to run simulation.RTL Simulation in Riviera (see page 45)

Step 5 – View the ResultsFollow Steps 4 to the end of to view the waveform.RTL Simulation in Riviera (see page 45)




Revision History

Version Date Description

1.0 August 28, 2016 Initial release.

1.1 October 31, 2016 Updated document template to reflect confidentiality.

1.2 November 13, 2016 Renamed and re-formatted the document to make it technology agnostic.

1.3 March 27, 2018 Added command option for configuration memory readback during WGL simulation for VCS and IES simulators


simulation user guide (ug072) - achronix contains the post-route (or final) simulation project area...

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