siigx hssi model spice user guide

8/10/2019 SIIGX HSSI Model Spice User Guide

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Stratix-II GX HSSIEncrypted Spice Model

User Guide

Copyright 2007 Altera Corp.

ALTERA Corporation Confidential 1


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1. Introduction:This document is the spice model user guide for the High Speed Serial Interface HSSI! Transmitter and Recei"er forStrati# II $% product famil&. The information in this document ena'les the user to configure the spice models to his(herre)uirement. It contains * different spice templates for T%+ R% and T%,R% com'ined.

The document -ill discuss the naming con"ention for the spice models+ file la&out and organiation+ control nodes for the

transmitter and recei"er along -ith the procedure for using the "arious settings. /lease go o"er the document 'efore runningthe simulations.

2. Directory Structure: igure 1 sho-s the director& structure of the Strati# II $% spice model it.

SIIGX_IO |_______inc | |

|_______ tx |

||_______ rx

|||_______ tx_rx

Figure 1. irector& structure of Strati# II $% HSSI spice modeling it

The content of each director& is as follo-s3

inc3 This director& contains the encr&pted spice netlists for the I(4 structures+ the encr&pted transistor process model li'raries+control setting files+ data input files and script to generate data input patterns. Here is the detailed description of files under ..(inc(director&.

- 5etlist3i. t#.cir3 Encr&pted T% dri"er netlist

ii. r#.cir3 Encr&pted R% recei"er netlistiii. rx_run_w_tx_only.cir3 Reduced R% recei"er netlist -hen running -ith Altera T% a fe- shared su'cts are

taen out to a"oid duplicated su'cts get to redefined t-ice!.

- /rocess Corner3i. 2sg#6tt.inc 3 Encr&pted process model for t&pical(t&pical corner

ii. 2sg#6ff.inc 3 Encr&pted process model for fast(fast corneriii. 2sg#6ss.inc 3 Encr&pted process model for slo-(slo- corner

- ata inputi. t#6data6input3 T% input data file

ii. r#6data6input3 R% input data file -hen running signal generator T7lineR%!

iii. signal6generator.inc3 Signal generator source

- Scripts3i. tx_ingen3 generates the spice input data file for T%. T&pe 8t#6ingen9 in .(inc( director& for instruction. The

scripts can onl& 'e used under :5I% platform.ii. de6gen ; do6gen3 su'7scripts of t#6ingen.

iii. rx_ingen3 generates the spice input data file for R%.i". rgen3 su'7script of r#6ingen". pr's


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Release 0.2Note3 Change the permission for a'o"e scripts to 8e#ecuta'le9 '& t&ping the follo-ing line in :ni#(Linu# -indo-under.(inc( director&: chmod a+x *gen*.

- Control setting files3i. t#6setting.inc3 li'rar& file to control all T% settings

ii. r#6setting.inc3 li'rar& file to control all R% settings.

- Spice output file 3i. t#6pro'e.inc3 pro'ing nodes of T% 'locs

ii. r#6pro'e.inc3 pro'ing nodes of R% 'loc

tx3 this director& contains the sample spice template using the transmitter model.- t#6nearend.spi3 spice template using the transmitter'loc

r#3 this director& contains the sample spice template using the recei"er model.- Siggen6'p6r#.spi3 spice template using the recei"er 'loc

tx_r#3 this director& contains the sample spice template using 'oth the transmitter and recei"er model.- t#6'p6r#.spi:spice template for 8T%>acplane T7line!R%9 simulation

3. Transmitter Driver Mode:igure 2 is the T% dri"er 'loc diagram. The left side are the T% input signals ?I! and the control nodes for pre7emphasissettings+ sle- rate settings+ termination resistor settings+ and common mode "oltage settings. The top has the po-er pins andthe 'ottom has the ground pins. The right has the near7end output pins T%/65EAR(T%565EAR!. See the pin descriptionfor more details.

VID

X_!"#_#$_%&'(0)

X_!"#_#$_2&2(0)

X_!"#_#$_!&2(0)

X_SIGI*V_2

X_SIGI*V_!"#

X_"_S+#,

X_#"$_S#+&%(0)

X_-0&.(0)

X!_*#A"

X*_*#A"

VCCX

VCC/X

VSSX

X_VOD_S#+&2(0)

X

Drier

X_V&%(0)

X_C+1X_C+13

Figure 23 A simplified T% dri"er

- !in descri"tion3

i. T% data input ; Clocsa. ?I3 T% input signals. ?I is a short representation of @ differential input signals 2 pairs!. These 2

pairs are3 T%6E(T%6E>3 ifferential pair of T% e"en data inputs T%64(T%64>3 ifferential pair of T% odd data inputs.

ALTERA Corporation Confidential *


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Release 0.25ote3 The odd(e"en data input is running at half the real data rate. The& are com'ined and serialiedinto a single serial data inside the T% 'loc. The& are taen care in the tx_data_inputfile -hich can'e automaticall& generated using the tx_ingenscript!.

or e#ample3T%6E3 0 0 0 0 0 1 1 0 0 1 1 1 1 0 1 0 0 0 1 0 1 0T%643 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1 0 1 1 1 1T%6CL 10101010101010101010101010101010101010101010T%6CL> 01010101010101010101010101010101010101010101

66666666666666666666666666666666666666666666?I Serial Input data!3 01010001011111010110111010011101010011011101

The 'it patten of the serial input data input to T% dri"er! is the same as the serial output data at

T%/65EAR pin.'. T%6CL(T%6CL>3 ifferential pair of Clocs to capture the a'o"e e"en(odd data and shift into the

T% dri"er. T%6CL samples T%6E ; T%6CL> samples T%64 to produce ?I.

ii. 4utput "oltage control3a. T%6?46SELB2303 le"el control for differential output "oltage ?4! through current control at the

outputTa#e13 ?4settings

T$_%&D_S'()2:*+ &ut"ut ,urrent s"ice Setting

000 2mA "od62ma

001 @mA "od6@ma

010 DmA "od6Dma

011 mA "od6ma

100 10mA "od610ma101 12mA "od612ma

110 1@mA "od61@ma

iii. /re7emphasis3a. T%6/RE6EF61TB*303 le"el control for the pre7emphasis 1sttap.

Ta#e23 irst tap pre7emphasis settings

T$_!'_'M_1T)3:*+ 1stTa" !re-em (eve s"ice Setting

0000 isa'le the pre7emphasis 1sttap t#61tap0

0001 1 t#61tap1

0010 2 t#61tap2

0011 * t#61tap*

0100 @ t#61tap@

0101 G t#61tapG0110 D t#61tapD

0111 < t#61tap T%6E, T%6E> T%64 T%64> T%6/RE6EF61T* T%6/RE6EF61T2 T%6/RE6EF61T1 T%6/RE6EF61T0, T%6/RE6EF62T2 T%6/RE6EF62T1 T%6/RE6EF62T0 T%6/RE6EF6/T2 T%6/RE6EF6/T1, T%6/RE6EF6/T0 T%6R6SLEN T%6SI$I5?62T T%6SI$I5?6/RE T%6TERF6SEL1 T%6TERF6SEL0, T%6?46SEL2 T%6?46SEL1 T%6?46SEL0 T%6?TT1 T%6?TT0 ?CCHT% ?CCT% ?SS% T$_T&!5 s61u

Note: 7s61u8 s"eci9ies a device "arameters inside te T$_T&! su#c;t are scaed


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"ii. Clocs3"t#6cl t#6cl 0 pulse0 p-r) P1(tdrate7trf#(2P trf# trf# P1(tdrate7trf#P P2(tdrateP!Et#6cl' t#6cl' 0 ?4LP "t#6cl!7p-r)!O71! !P

"iii. /re7emphasis setup3.li' K..(inc(t#7setting.inc t#6prtap0 M isa'le the pre7tap pre7emphasis. See ta'le @ for more settings..li' K..(inc(t#6setting.inc t#61tap0 M isa'le the 1sttap pre7emphasis. See ta'le 2 for more settings..li' K..(inc(t#6setting.inc t#62tap0 M isa'le the 2ndtap pre7emphasis. See ta'le * for more settings.

i#. Termination resistor3.li' K..(inc(t#6setting.inc r1006tt M 100Q internal termination resistor. See ta'le D for more settings.

#. Common mode "oltage source3.li' K..(inc(t#6setting.inc "cm60pD M Common mode "oltage. ?cm0.D". See ta'le < for more settings.

#i. 4utput "oltage opening control3.li' K..(inc(t#6setting.inc "od6ma M ifferential output "oltage ?4! control. 4utput current ma.

M See ta'le 1 for more settings.

#ii. /re7emphasis sign in"ersion control3?sigin"6pre t#6sigin"6pre "ss# 0 M /re7tap polarit& control. /ositi"e 0+ negati"e p-r).

?sigin"62t t#6sigin"62t "ss# 0 M /re7tap polarit& control. /ositi"e 0+ negati"e p-r).

#iii. E#ternal termination for R% representation3Re#t t#p6near t#n6near 100 M Set the e#ternal matching resistor to 100 ohms.

#i". E&e diagram generation ; pro'ing nodes3E&e "e&e 0 ?4L1e0OTIFE7dpercOintTIFE(dperc!!Re&e "e&e 0 10..inc K..(inc(t#6pro'e.inc M /ro'e interested nodes of T%.

#". Simulation transient3.tran 0.01ns P'it6numOper#,2ns,D0nsP startD0nsIt taes a -hile for all the nodes to 'ecome sta'ilied. Thus to o'tain a correct "alue+ the start time to

record the -a"eforms should 'e at a time -hen all the nodes are sta'le. Thats -h& the a'o"e D0ns ischosen for a good e&e diagram.

. $ eceiver:

>elo- igure *! is the R% dri"er 'loc diagram. The left has t-o T% input signals R%6I5/(R%6I55! and the rest areRAF 'its to control the e)ualier+ the dc gain+ the common mode "oltage+ and the termination resistor. The top has the



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Release 0.2po-er pins and the 'ottom has the ground pins. The right has R% output pins R%/(R%5! to the CR. See the pindescription for more detail of e"er& pin.

"X_I*!

"X_# 89ee ta:le 7;

"X_"3I_DC&%(0)

"X_V&2(0)

"X_#"$&%(0)

"X!

"X*

VCC"X

VSSX

"X_I**

"X

Drier

"X_3-0&(0)

Figure 33 A simple R% dri"er

- !in descri"tion3

i. R% data inputa. R%6I5/3 positi"e R% data input.'. R%6I553 negati"e R% data input

ii. E)ualier gain3a. R%6E3 ta'le sho-s 1D a"aila'le e)ualier settings for R% dri"er

Ta#e=3 E)ualier settings

0ain eve '>uai?er 0ain s"ice Setting

>&pass 0d>! >&pass E6>/

Lo- $ain*7!

Lo- 0 E6L0

Lo- 1 E6L1

Lo- 2 E6L2

Lo- * E6L*

Lo- @ E6L@

Fed $ain712d>!

Fed 0 E6F0

Fed 1 E6F1

Fed 2 E6F2

Fed * E6F*

Fed @ E6F@

High $ain1271Dd>!

High 0 E6H0High 1 E6H1

High 2 E6H2

High * E6H*

High @ E6H@

iii. C gain le"el3

R%6R>IT6CB1303 /rogramma'le C gain setting for the e)ualier.

Ta#e @3 E)ualier C gain settings



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$_AIT_D,)1:*+ D, gain eve s"ice Setting

00 0 d> dc6gain0

01 * d> dc6gain1

10 * d> dc6gain2

11 D d> dc6gain*

i". Common mode "oltage control3R%6?TTB2303 Common mode "oltage le"el control for R%. Support onl& * le"el settings3 tri7state+ 0."+

and 1.2". Ta#e 1*3 Common mode "oltage le"el settings

$_%TT)2:*+ %otage eve s"ice Setting

110 Tri7state ?cm6tri

010 0." ?cm60p

011 1.2" ?cm61p2

". Internal termination resistor3R%6TERFB1303 controlled signal for R% differential input termination resistorThe internal termination resistance "alues "ar& depending on the process corner and temperature.

Ta#e 113 Internal Termination Resistance settings

$_T'M)1:*+ Termination esistance s"ice Setting

00 1G0 4hms efault!r1G06ttr1G06ffr1G06ss

01 120 4hmsr1206ttr1206ffr1206ss

10 100 4hmsr1006ttr1006ffr1006ss

11 E#ternal Resistor open drain! re#t

R%6>G0B@303 are internal controlled signals for termination resistance "alues. The user needs not to -orr&a'out these nodes. The a'o"e hspice settings ta'le 11! -ill tae care of them.

"i. /o-er and $round3?CCR%3 1.2" po-er suppl& for R% dri"er?SS%3 Common ground

"ii. R% data output to the CR3R%/3 /ositi"e differential output pinR%53 5egati"e differential output pin

- S"ice tem"ates descri"tion:To test the R% dri"er+ the user can use an ideal dri"er or a real dri"er to dri"e the R% recei"er directl& or through a'acplane. The R% spice template is 'uilt for figure @ -hich is an ideal dri"er dri"ing a 'acplane+ an AC cap+ anda real Altera R% recei"er.



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Figure 3 A signal generator dri"es Altera R% recei"er through a 'acplane and an AC cap.

i. siggen_#"_rx.s"i3 R% spice template -hich can 'e modified depending on the application.

ii. 5etlist3.include K..(inc(r#.cir M $et the R% circuit netlist.

>elo- statement assigns all the pin names to the $_T&!su'7circuit instance.

$$_T&! R%6EA R%6E> R%6EC R%6E R%6E? R%6I5/ R%6I55 R%6R>IT6C1, R%6R>IT6C0 R%/ R%5 R%6>G0@ R%6>G0* R%6>G02 R%6>G01 R%6>G00 R%6TERF1, R%6TERF0 R%6?TT2 R%6?TT1 R%6?TT0 ?CCR% ?SS% $_T&!5 s61u

Note: 7s61u8 s"eci9ies a device "arameters inside te T$_T&! su#c;t are scaed


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Release 0.2accurate M 1 Sets timestep to gi"e 'etter TRA5 accurac&

See spice manuals for more options.

i". /rocess corner.inc K..(inc(2sg#6tt.inc M 8T&pical(T&pical9 corner

M or 8ast(ast9 corner+ change 82sg#6tt.inc9 to 82sg#6ff.inc9M or 8Slo-(Slo-9 corner+ change 82sg#6tt.inc9 to 82sg#6ss.inc9

". /o-er(ground3.param p-r)1.2" M Lo- "oltage po-er suppl&"ccr# "ccr# 0 p-r) M 1.2" po-er suppl&""ss# "ss# 0 0 M $round

"i. Temperature3.temp 2G M T&pical temperature

"ii. Input data pattern.param tdrateD.*acplane connection3OOO Loss Less T7line OOOO

T6lossless6p sg6p "ss# inpp "ss# 4G0 T0.0GnsT6lossless6n sg6n "ss# innn "ss# 4G0 T0.0Gns

or the 'acplane+ a loss less transmission line is used here. The customer can replace the T7line -ithhis(her 'acplane S7parameter '& replacing the T6lossless6p(6n -ith S1 as sho-n 'elo-!.8&our6'acplane.s@p9 is the s7parameter file name of the customer 'acplane.

OOO S7parameter >acplane OOOS1 sg6p inpp sg6n innn "ss# mname'p6name.model 'p6name s tstonefileP..(inc(your_backplane.s4p'

#. AC couple capacitance3Cacp inpp r#6inp 1mf M AC cap on r#6inp nodeCacp innn r#6inn 1mf M AC cap on r#6inn node5ote3 the capacitance "alue can 'e "aried depending on the customers application.

#i. E)ualier gain setting3.li' K..(inc(r#6setting.inc E6>/ M E)ualier gain setting. See ta'le for more settings.

#ii. E)ualier C gain setting3.li' K..(inc(r#6setting.inc dc6gain0 M E)ualier C gain setting. See ta'le for more settings.

#iii. Common mode "oltage source3.li' K..(inc(r#6setting.inc "cm60p M Common mode "oltage. ?cm0.". See ta'le 10 for more settings.

ALTERA Corporation Confidential 1@


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Release 0.2#i". Termination resistor3

.li' K..(inc(r#6setting.inc r1006tt M Internal termination resistor setting. See ta'le 11 for more settings.

#". E&e diagram generation ; pro'ing nodes3e&e "e&e 0 ?4L1e0OTIFE,GGe7!7dpercOintTIFE,GGe7!(dperc!!re&e "e&e 0 10..inc K..(inc(r#6pro'e.inc M /ro'e R% interested nodes for "ie-ing.

#"i. Simulation transient3.tran 0.01ns P'it6numOper#,2ns,D0nsP startD0nsIt taes a -hile for all nodes to 'ecome sta'ilied. Thus to o'tain a correct "alue+ the start time to recordthe -a"eforms should 'e at the time all nodes are sta'le. Thats -h& the a'o"e D0ns is chosen for a goode&e diagram. Some 'acplanes ma& re)uire longer or shorter sta'le times.

- 'B' mas; 9or te out"ut o9 te $:

The outputs R%/(R%5! are the input to the CR. To mae sure the CR cloc data reco"er&!-ors fine+ the e&e opening of the di99erentia output at R%/(R%5 pins must 'e larger than the EEmas.

X%#eye

/#eye

Xeye

A:oe '.2 G:p9(

X%_eye @ 0.- I

X2_eye @ 0.4 I

B_eye @ %4- ?V

3elo '.2 G:p9(

X%_eye @ 0.27- IX2_eye @ 0.00 I

B_eye @ %4- ?V

Figure /3 E&e mas for the differential output of the R%

/. T$

A! $:

This section sho-s the Altera T% dri"er that dri"es the Altera R% recei"er 'loc through a 'acplane and AC caps. igure Dsho-s a simplified diagram for the connection of these t-o 'locs. /lease refer to the T% and R% sections for the settings.

ALTERA Corporation Confidential 1G


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Figure 3 T% dri"es R% through a 'acplane and AC caps.

- !in descri"tion3/lease refer to the T% ri"er and R% recei"er sections for pin description and settings.

- S"ice tem"ates descri"tion:This section pro"ides the spice template to chec the lin of Altera 8T% >acplaneR%9. The current

'acplane is a lossless transmission line T7line!. The user can replace the T7line net-or -ith his(her 'acplanes7parameter

The spice file tx_bp_rx.spihas G sections as follo-3

i. /art 13 contains the process+ options+ and temperature.ii. /art 23 is Altera T% dri"er. This portion is "er& similar to the T% dri"er section.

iii. /art *3 contains the 'acplane. The loss less transmission line must 'e replaced -ith the customer 'acplane.

i". /art @3 is the Altera R% recei"er. This portion is "er& similar to the R% recei"er section. The onl& difference isrx.ciris replaced '& rx_run_w_tx_only.cirnetlist. The reason is r#.cir shares some su'cts -ith t#.cir. Thusr#6run6-6t#6onl&.cir is a reduced "ersion of r#.cir -here shared su'ct under r#.cir are remo"ed to a"oidconflict.

". /art G3 contains the simulation transient , the e&e diagram generation.

Note:1. /lease refer to the 8T% dri"er9 and 8R% recei"er9 sections for more information.

2. The "alue of the AC caps "aries depending to the customers application. If 'igger cap "alue is used+then it taes longer time for the T%/65EAR(T%565EAR to settle do-n longer simulation run

time is needed.

ALTERA Corporation Confidential 1D

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siigx hssi model spice user guide

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