signals and communication technology978-3-319-66565...this book is a result of our research work in...

Signals and Communication Technology

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Xinpeng Xing • Peng ZhuGeorges Gielen

Design of Power-EfficientHighly DigitalAnalog-to-Digital Convertersfor Next-Generation WirelessCommunication Systems

123

Xinpeng XingGraduate School at ShenzhenTsinghua UniversityShenzhenChina

Peng ZhuZhongguancun Dongsheng Technology ParkAnalog Devices, Inc.BeijingChina

Georges GielenDepartement Elektrotechniek,ESAT-MICAS

Katholieke Universiteit LeuvenLeuvenBelgium

ISSN 1860-4862 ISSN 1860-4870 (electronic)Signals and Communication TechnologyISBN 978-3-319-66564-1 ISBN 978-3-319-66565-8 (eBook)https://doi.org/10.1007/978-3-319-66565-8

Library of Congress Control Number: 2017950276

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To my wife Qin!

Preface

Mobile devices motivate the continuous development of the communicationindustry, meaning low-power designs are in great demand. Analog-to-digital con-verters (ADCs) build bridge between analog front-end and digital cores, and play amore important role in emerging transceiver architectures. On the other hand, due toCMOS technology scaling, the ADC design suffers from design issues such asdecreasing headroom voltage. Recently, one popular direction of ADC design isshifting more functions from the voltage and the analog domains to the time and thedigital domains, by using a voltage-controlled oscillator (VCO). The implementa-tion of circuits in the time domain immediately takes advantage again of thetechnology scaling with reduced gate delay.

This book is a result of our research work in ESAT-MICAS, K.U. Leuven, in thefield of highly digital ADC design. Recently, highly digital ADC has drawn moreand more interest from both academy and industry, and the increasing number ofpublication on this topic is an evidence. We believe this is a natural evolution whenIC designers are facing ongoing-scaling CMOS technologies. With this commoninterest, however, we cannot find systematic book on this topic but only papers andbook chapters as far as we know. It has been our motivation to present our work inhighly digital ADC as a book. This collection is mainly based on our own five chipdesigns in ESAT-MICAS, and also, some previous contributions by variousresearchers to this field are also included.

This book focuses on the systematic design of power-efficient highly digitalADC for future communication applications, with both architecture- andcircuit-level innovations. The first two designs are 40MHz-BW 12bit CT DR ADCsimplemented in 90nm CMOS, with quantizations done by highly digitalVCO-based quantizer. Various circuit-level techniques are applied for powerreduction, including the shaped switched capacitor digital-to-analog converter (SCDAC), the look-up-table (LUT)-based digital calibration, and the current-sharingfeedforward-compensated OTA. The third design is a 40MHz-BW two-stepopen-loop VCO-based ADC in 40nm CMOS. With hardware-economic structureand mostly digital building blocks, an excellent FoM of 42fJ/step is obtained.However, only first-order noise shaping is realized for the whole ADC, limiting its

vii

SNR performance. To go further, in our fourth design, a nonlinearity cancellation0–2 MASH DR ADC structure with innovative dual-input VCO-based quantizer isadopted. The optimized systematic parameters and the highly digital circuit blocksextend the FoM of the state-of-the-art high-bandwidth DR ADCs to 35fJ/step. Withsecond-order noise shaping, the ADC performance is improved, and one analogfront-end integrator is still needed, however. In the final design of this work, aVCO-based integrator is proposed to replace the power-hungry analog integrator inthe traditional DR ADC topology, realizing second-order DR ADC without anyanalog integrator. 74-dB SFDR and a FoM of 52fJ/step over a 40MHz bandwidthhave been achieved in the demonstration.

With the state-of-the-art power efficiencies, the presented highly digital ADCsare very suitable for the applications of next-generation wireless communicationstandards, including but not limited to 802.11n and LTE. Furthermore, the designmethodology and design innovations described in this book could also be applied toADCs for other applications.

Shenzhen, China Xinpeng XingBeijing, China Peng ZhuLeuven, Belgium Georges GielenMarch 2017

viii Preface

Acknowledgements

At the moment to archive our work, we could not forget the people, who con-tributed directly or indirectly to this book. First, we would like to thank editorOliver Jackson, Springer UK, for his careful and patient organization work duringthe whole publication procedure. We also would like to express our gratitude toanonymous reviewers for their valuable comments and suggestions for improve-ment. During our PhDs in K.U. Leuven, Prof. Jean Berlamont, Prof. MichielSteyaert, Prof. Marc Moonen, Prof. Wim Dehaene, Prof. Pieter Rombouts, Prof.Patrick Wollants, Prof. Guy Vandenbosch, all in K.U. Leuven, and Prof. MichaelPeter Kennedy, University College Cork, and Andrea Baschirotto, University ofMilano-Bicocca served kindly as the program committee members, many thanks tothem for their valuable feedback and communications on our work. We would liketo thank Danielle Vermetten, Ben Geeraerts, Chris Mertens, Frederik Daenen,Noella Gaethofs, and Michel De Cooman in MICAS-ESAT for their outstandingsecretariat and logistic works. Without their supports, we cannot accomplish thewhole chip design. We also would like to thank our ex-colleagues (also friends) YiKe and Peng Gao for the technical discussion in data converters and so on.

Besides, we would like to convey our thanks to the Funds for Scientific ResearchFlanders (FWO-V.), Belgium, and the European Union Seventh FrameworkProgramme for Research and Technology Development (EU-FP7) for the projectfinancial supports.

Finally, our most grateful thanks are for our families, for their invaluable love,support, and patience. Also many thanks to our colleagues and friends, for thewonderful time and memory in Leuven.

Shenzhen, China Xinpeng XangMarch 2017

ix

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Background and Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1.1 Communication Evolution. . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.2 CMOS Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.1.3 Wireless Receiver Architectures . . . . . . . . . . . . . . . . . . . . . 6

1.2 The Research Objective of the Book . . . . . . . . . . . . . . . . . . . . . . . 81.3 The Book Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2 A/D Converters and Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.2 ADC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.1 ADC Speed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.2.2 ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.2.3 ADC FoM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3 ADC Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.3.1 Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192.3.2 Two-Step ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212.3.3 Pipelined ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222.3.4 SAR ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232.3.5 Delta-Sigma ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242.3.6 ADC Architecture Summmary and Comparison . . . . . . . . . 26

2.4 Application of ADC in Communications . . . . . . . . . . . . . . . . . . . . 282.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3 Continuous-Time Delta-Sigma Modulators . . . . . . . . . . . . . . . . . . . . . 373.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373.2 DSM Basics: Oversampling and Noise-Shaping . . . . . . . . . . . . . . . 383.3 DSM Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

xi

3.3.1 Discrete-Time and Continuous-Time DSMs . . . . . . . . . . . . 413.3.2 1st-Order and Higher-Order DSMs . . . . . . . . . . . . . . . . . . . 443.3.3 Single-Loop and MASH DSMs . . . . . . . . . . . . . . . . . . . . . 453.3.4 The D R-0 and 0-D R MASH Structures . . . . . . . . . . . . . . 463.3.5 Single-Bit and Multi-bit DSMs . . . . . . . . . . . . . . . . . . . . . . 483.3.6 Feedforward, Feedback and Hybrid DSMs . . . . . . . . . . . . . 503.3.7 Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523.3.8 Feedin Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.4 CT DSM Nonidealities and Modeling . . . . . . . . . . . . . . . . . . . . . . 533.4.1 Loop Filter Nonidealities and Modeling . . . . . . . . . . . . . . . 543.4.2 DAC Nonidealities and Modelling . . . . . . . . . . . . . . . . . . . 593.4.3 Quantizer Nonidealities and Modeling . . . . . . . . . . . . . . . . 63

3.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4 VCO-Based ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674.2 VCO-Based Quantizers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4.2.1 Single-Phase Counting VCO-Based Quantizer . . . . . . . . . . 684.2.2 Multi-phase Counting VCO-Based Quantizer . . . . . . . . . . . 684.2.3 Frequency-Type VCO-Based Quantizer . . . . . . . . . . . . . . . 694.2.4 Phase-Type VCO-Based Quantizer . . . . . . . . . . . . . . . . . . . 72

4.3 Closed-Loop VCO-Based DSMs . . . . . . . . . . . . . . . . . . . . . . . . . . 724.3.1 DSM with Frequency-Type VCO-Based Quantizer . . . . . . . 734.3.2 DSM with Phase-Type VCO-Based Quantizer . . . . . . . . . . 744.3.3 DSM with Residual-Cancelling VCO-Based Quantizer . . . . 74

4.4 Open-Loop VCO-Based ADCs. . . . . . . . . . . . . . . . . . . . . . . . . . . . 764.4.1 VCO-Based ADC with Background Digital Calibration . . . 764.4.2 VCO-Based ADC with Counting and Foreground

Digital Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774.4.3 VCO-Based ADC with PWM Precoding. . . . . . . . . . . . . . . 78


5 CT DSM ADCs with VCO-Based Quantization . . . . . . . . . . . . . . . . . 835.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835.2 A 40 MHz-BW 12-Bit CT DSM with Digital Calibration and

Shaped SC DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845.2.1 Structure of the CT DSM . . . . . . . . . . . . . . . . . . . . . . . . . . 845.2.2 Delta-Sigma Modulator Building Blocks Design. . . . . . . . . 895.2.3 Measurement Setup and Experimental Results . . . . . . . . . . 95

5.3 A 40 MHz-BW 12-Bit CT DSM with Capacitive LocalFeedback and Current-Sharing OTA. . . . . . . . . . . . . . . . . . . . . . . . 975.3.1 System Design of the 40 MHz 12-Bit CT DSM . . . . . . . . . 99

xii Contents

5.3.2 Circuit Design of the DSM Building Blocks. . . . . . . . . . . . 1015.3.3 Measurement Results and Discussions . . . . . . . . . . . . . . . . 104


6 Two-Step Open-Loop VCO-Based ADC . . . . . . . . . . . . . . . . . . . . . . . 1096.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096.2 Architecture Design of Two-Step Open-Loop VCO-Based

ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1106.2.1 A Two-Step Open-Loop VCO-Based ADC

Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1106.2.2 Nonidealities of the Two-Step Open-Loop

VCO-Based ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136.3 Circuit Implementation of the Two-Step Open-Loop

VCO-Based ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166.3.1 VCO-Based Quantizer Design. . . . . . . . . . . . . . . . . . . . . . . 1176.3.2 DAC and Subtractor Design . . . . . . . . . . . . . . . . . . . . . . . . 119

6.4 Experimental Results and Discussions . . . . . . . . . . . . . . . . . . . . . . 1226.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

7 VCO-Based 0-DR MASH ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1277.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1277.2 Architecture Analysis of the 0-DR MASH VCO-Based ADC . . . . 128

7.2.1 0-DR MASH VCO-Based ADC . . . . . . . . . . . . . . . . . . . . . 1287.2.2 Nonlinearity-Cancellation Robustness Against PVT

Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1317.2.3 System Architecture of a 0–2 MASH VCO-Based

DR ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1327.2.4 Delay Matching Technique . . . . . . . . . . . . . . . . . . . . . . . . . 134

7.3 Circuit Implementation of the 0–2 MASH VCO-BasedDR ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1367.3.1 Three-Input Adder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1367.3.2 VCO-Based Quantizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1377.3.3 Integrator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1397.3.4 DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1417.3.5 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

7.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1437.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

8 Fully-VCO-Based High-Order DR ADC . . . . . . . . . . . . . . . . . . . . . . . 1538.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1538.2 Integrators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Contents xiii

8.2.1 Traditional Analog Integrator . . . . . . . . . . . . . . . . . . . . . . . 1538.2.2 VCO-Based Integrator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1558.2.3 Fully-VCO-Based DR ADC Structure . . . . . . . . . . . . . . . . . 157

8.3 Design Example: A Fully-VCO-Based 0-2 MASH VCO-BasedDR ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1588.3.1 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1588.3.2 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1608.3.3 Experimental Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163


9 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1739.1 Summary and Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1739.2 Suggestions for Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

xiv Contents

Abbreviations

2G Second Generation3G Third GenerationAAF Anti-Aliasing FilteringAC Alternating CurrentA/D Analog-to-DigitalADC Analog-to-Digital ConverterADSL Asymmetric Digital Subscriber LineAFE Analog Front-EndAGC Automatic Gain ControlAPWM Asynchronous Pulse-Width ModulatorASIC Application-Specific Integrated CircuitBB BaseBandBPF Band-Pass FilterBW BandwidthCF Crest FactorCM Common ModeCMFB Common-Mode FeedbackCMOS Complementary Metal Oxide SemiconductorCS Current-Steering or Current-SharingCT Continuous-TimeD/A Digital-to-AnalogDAC Digital-to-Analog ConverterDC Direct CurrentDCM Duty Cycle ModulationDEM Dynamic Element MatchingDFF Direct FeedforwardDNCF Digital Noise Cancellation FilterDNL Differential NonlinearityDR Dynamic RangeDSM Delta-Sigma Modulator

xv

DSP Digital Signal ProcessingDT Discrete-TimeDVD Digital Versatile DiscEDA Electronic Design AutomationELD Excess Loop DelayENOB Effective Number of BitERBW Effective Resolution BandwidthFET Field Effect TransistorFF FeedForward or Flip-FlopFIR Finite Impulse ResponseFM Fading MarginFoM Figure of MeritFS Full ScaleGBW Gain bandwidth productGP General PurposeGSM Global System for Mobile CommunicationsHSDPA High Speed Downlink Packet AccessIC Integrated CircuitsICO Current-Controlled OscillatorIF Intermediate FrequencyIIT Impulse Invariant TransformationIM2/3 2nd/3rd-order Intermodulation DistortionINL Integrated NonlinearityIPTV Internet Protocol TelevisionI/Q In-phase/QuadratureISI Inter-Symbol InterferenceISSCC International Solid-State Circuits ConferenceLFSR Linear Feedback Shift RegisterLHP Left Half PlaneLMS Least Mean SquareLNA Low-Noise AmplifierLO Local OscillatorLPF Low-Pass FilterLSB Least Significant BitLTE Long Term EvolutionLUT Look-Up TableLVDS Low-Voltage Differential SignallingMASH Multi-stAge noise SHapingMDAC Multiplying DACMIM Metal-Insulator-MetalMOS Metal-Oxide-SemiconductorMSB Most Significant BitNAND Negated AND

xvi Abbreviations

NF Noise FigureNFC Near Field CommunicationNM Noise MarginNMOS N-channel MOSTFETNRZ Non Return-to-ZeroNTF Noise Transfer FunctionOSR Oversampling RatioOTA Operational Transconductance AmplifierPA Power AmplifierPC Personal ComputerPCB Printed Circuit BoardPD Phase DetectorPLL Phase-Locked LoopPMOS P-channel MOSFETPM Phase MarginPSD Power Spectral DensityPSRR Power Supply Rejection RatioPVT Pcocess Voltage TemperaturePWM Pulse-Width ModulatorRF Radio FrequencyRMS Root-Mean-SquareROM Read-Only MemoryRSR Receivable Signal RangeRZ Return-to-ZeroSA Sense-AmplifierSAFF Sense-Amplifier Flip-FlopSAR Successive Approximation RegisterSAW Surface Acoustic WaveSC Switched-CapacitorSFDR Spurious-Free Dynamic RangeS/H Sample and HoldSiGe Silicon-GermaniumSNDR Signal-to-Noise-Distortion RatioSNR Signal-to-Noise RatioSoC System on ChipSP Standard PerformanceSQNR Signal-to-Quantization-Noise RatioSTF Signal Transfer FunctionTDMA Time Division Multiple AccessTHD Total Harmonic DistortionTSPC FF True-Single-Phase Clock Flip-FlopTV TelevisionVCO Voltage-Controlled Oscillator

Abbreviations xvii

VDSL Very-High-Bit-Rate Digital Subscriber LineV-F Voltage-FrequencyVGA Variable Gain AmplifierVGLNA Variable Gain Low-Noise AmplifierVTC Voltage-to-Time ConverterWLAN Wireless Local Area NetworkXOR Exclusive OR

xviii Abbreviations

List of Figures

Fig. 1.1 Data rate comparison between different wireline internetaccesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Fig. 1.2 Evolution of wireless communications [3]. . . . . . . . . . . . . . . . . . 3Fig. 1.3 Relative global shipments of four consumer electronics from

2012 to 2017 (estimated values for 2013 and 2017) [4] . . . . . . . 4Fig. 1.4 CMOS technology scaling over the last 45 years and prediction

for the next 4 years . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Fig. 1.5 Decreasing supply voltage and relatively constant threshold

voltage with CMOS scaling [7]. . . . . . . . . . . . . . . . . . . . . . . . . . 5Fig. 2.1 Generalized architecture, operation and waveforms of an ADC,

both with Nyquist sampling and oversampling . . . . . . . . . . . . . . 17Fig. 2.2 The linear model and input-output transfer function of the

quantizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Fig. 2.3 N-bit flash ADC architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Fig. 2.4 Block diagram of a (M þ N)-bit two-step ADC . . . . . . . . . . . . 22Fig. 2.5 Simplified architecture of pipelined ADC . . . . . . . . . . . . . . . . . . 23Fig. 2.6 Structure of SAR ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Fig. 2.7 Block diagram of DSM ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Fig. 2.8 Accuracy-bandwidth tradeoff of ADC architectures. . . . . . . . . . . 27Fig. 2.9 FoMs of different ADC architectures in ISSCC publications

[27] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Fig. 2.10 A receiver is partitioned into three basic parts. . . . . . . . . . . . . . . 28Fig. 2.11 Receiver AFE is a cascaded system . . . . . . . . . . . . . . . . . . . . . . 28Fig. 2.12 Accuracy relationship between the ADC and the AFE in a

telecom receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Fig. 3.1 Structure of a whole CT DSM ADC. The corresponding

illustrative signals and their spectral plots illustrate thestructure’s operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Fig. 3.2 A generalized DSM structure (top) and its linear model(bottom) for performance analysis . . . . . . . . . . . . . . . . . . . . . . . . 40

xix

Fig. 3.3 Structure of a DT DSM (top) and its CT counterpart(bottom). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Fig. 3.4 Popular circuit implementations of DT (left) and CT (right)integrators used in the DSM loop filter . . . . . . . . . . . . . . . . . . . . 42

Fig. 3.5 Different DAC current profiles used in CT DSMs: NRZ (left),RZ (middle) and SC (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Fig. 3.6 Performance of Nth-order 3-bit DSM with different OSRs . . . . . 44Fig. 3.7 The architecture of a discrete-time 2-2 MASH DSM,

the total noise shaping is 4th-order . . . . . . . . . . . . . . . . . . . . . . . 46Fig. 3.8 Block diagram of a D R-0 MASH structure . . . . . . . . . . . . . . . . 47Fig. 3.9 Block diagram of a modified DR-0 MASH structure. . . . . . . . . . 47Fig. 3.10 Block diagram of a 0-DR MASH structure . . . . . . . . . . . . . . . . . 48Fig. 3.11 Single-bit quantizer: the linear model, the input-output transfer

function and its highly nonlinear gain . . . . . . . . . . . . . . . . . . . . . 49Fig. 3.12 The concept of DEM: 3-bit DACs without (left) and with

(right) DEM are illustrated for comparison . . . . . . . . . . . . . . . . . 50Fig. 3.13 Different structures of generalized Nth-order DSMs:

feedforward (top), feedback (upper middle) and hybrid ones(lower middle and bottom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Fig. 3.14 Resonator in the loop filter for the generation of complexNTF zeroes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Fig. 3.15 Direct coupling paths from the DSM input to integratorsand quantizer for integrator output swing reduction . . . . . . . . . . 53

Fig. 3.16 An active-RC integrator with nonideal OTA and three inputvoltages in a CT DSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Fig. 3.17 An active-RC integrator with nonideal OTA and input parasiticcapacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Fig. 3.18 An accurate and convenient nonideal model of anactive-RC integrator in Matlab Simulink . . . . . . . . . . . . . . . . . . . 58

Fig. 3.19 Variable capacitor for RC time constant tuning in anactive-RC integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Fig. 3.20 Clock-jitter-induced noise in single-bit DACs: RZ (left),NRZ (middle) and SC (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Fig. 3.21 Clock-jitter-induced noise in multi-bit DACs: RZ (left),NRZ (middle) and SC (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Fig. 3.22 Inter-symbol inteference (ISI) of a NRZ DAC (right);the error is marked in darkgray. . . . . . . . . . . . . . . . . . . . . . . . . . 62

Fig. 3.23 The zero-order feedback path for ELD compensation infeedback-type DSMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Fig. 3.24 The ELD compensation scheme without extra analog adder:the zero-order feedback path is composed by a digitaldifferentiator and an analog integrator . . . . . . . . . . . . . . . . . . . . . 64

Fig. 4.1 Single-phase (left) and multi-phase (right) countingquantizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

xx List of Figures

Fig. 4.2 Structure, behavioral model and illustrative spectrum of thefrequency-type VCO-based quantizer . . . . . . . . . . . . . . . . . . . . . 70

Fig. 4.3 Structure of the phase-type VCO-based quantizer; theadditional digital frequency output is used for DSM ELDcompensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Fig. 4.4 Architecture of a 3rd-order CT DSM with frequency-typeVCO-based quantizer [4]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Fig. 4.5 Topology of a 4th-order CT DSM with phase-type VCO-basedquantizer [8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Fig. 4.6 Structure of a 2nd-order CT DSM with residual-cancellingVCO-based quantizer [10]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Fig. 4.7 Architecture of a 1st-order open-loop Delta-Sigma ADCwith VCO nonlinearity calibration (only one pathis shown here) [11] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Fig. 4.8 Concept of the VCO nonlinearity background digitalcalibration used in Fig. 4.7 [11] . . . . . . . . . . . . . . . . . . . . . . . . . 77

Fig. 4.9 Structure of an open-loop Delta-Sigma ADC with coarse andfine quantizations and VCO nonlinearity calibration [13] . . . . . . 78

Fig. 4.10 Concept of the foreground digital calibration used inFig. 4.9 [13] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Fig. 4.11 Architecture and illustrative signals of an open-loopVCO-based ADC with PWM precoding [15] . . . . . . . . . . . . . . . 79

Fig. 4.12 Implementation of an asynchronous PWM with hysteresissingle-bit quantizer [16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Fig. 5.1 Structure of the 40 MHz 12-bit CT DSM . . . . . . . . . . . . . . . . . . 85Fig. 5.2 CT DSM SNDR performance as a function of the scaled

OTA GBWs (normalized to 4, 2 and 2 GHz for loop filterintegrator one to three respectively) . . . . . . . . . . . . . . . . . . . . . . 86

Fig. 5.3 CT DSM SNDR performance as a function of the delayfor the three different feedback DACs. . . . . . . . . . . . . . . . . . . . . 87

Fig. 5.4 Block diagram of the digital calibration of the DAC. Thevalues in the look-up table are arbitrary values, for illustrativepurpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Fig. 5.5 Block diagram of the 4-stage full-feedforward compensatedoperational transconductance amplifier . . . . . . . . . . . . . . . . . . . . 90

Fig. 5.6 SNDR performance of the CT DSM as a function of therelative position of the poles and zeros in the doublets . . . . . . . . 91

Fig. 5.7 AC simulation result of (internal) gain of the operationaltranconductance amplifier used in the first integrator. . . . . . . . . . 92

Fig. 5.8 Circuit implementation of the shaped SC DAC (right) and itsdriving circuit (left) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Fig. 5.9 The output current pulse of the shaped SC DAC, comparedto the traditional pulse shape, as used in our design . . . . . . . . . . 93

Fig. 5.10 Schematic of the current-steering DAC cells . . . . . . . . . . . . . . . . 94

List of Figures xxi

Fig. 5.11 Die photo of the 40 MHz 12-bit CT DSM . . . . . . . . . . . . . . . . . 96Fig. 5.12 Measurement setup for the 40 MHz 12-bit CT DSM . . . . . . . . . 96Fig. 5.13 Measured spectra with (right) and without (left) digital

calibration for 938 kHz and 7.5 MHz input signals. . . . . . . . . . . 97Fig. 5.14 SNR/SNDR versus input amplitude for 938 kHz input

signals (left) and 7.5 MHz input signals (right). . . . . . . . . . . . . . 98Fig. 5.15 Output spectrum for a �10:5 dB two-tone test with 10

and 10.5 MHz frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98Fig. 5.16 Block diagram of the 40 MHz 12-bit CT DSM. . . . . . . . . . . . . . 99Fig. 5.17 Schematic of the current-sharing feedforward OTA. . . . . . . . . . . 103Fig. 5.18 AC simulation results of the current-sharing feedforward

OTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103Fig. 5.19 Die photo of the low-power 40 MHz 12-bit CT DSM . . . . . . . . 104Fig. 5.20 Measured spectra for a �3 dBFS 938 kHz (left) and a 7.5

MHz (right) single-tone measurement . . . . . . . . . . . . . . . . . . . . . 105Fig. 5.21 Measured SNR/SNDR versus input amplitude for a 938 kHz

input signal (left) and a 7.5 MHz input signal (right) . . . . . . . . . 105Fig. 5.22 Spectrum of two-tone measurement (�9:5 dBFS, 10 MHz

and 10.5 MHz input signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106Fig. 6.1 Proposed two-step open-loop VCO-based ADC architecture

and the VCO nonlinearity mitigation concept . . . . . . . . . . . . . . . 111Fig. 6.2 ADC SNDR performance as a function of the normalized

gain of the coarse ADC, fine ADC and DAC . . . . . . . . . . . . . . . 114Fig. 6.3 ADC SNDR performance as a function of the delays of the

coarse ADC and the DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115Fig. 6.4 ADC SNDR performance as a function of the standard

deviation of the current of the DAC cells. For comparison,both cases with and without DEM are showed . . . . . . . . . . . . . . 116

Fig. 6.5 ADC SNDR performance as a function of the clock jitter:around 15ps jitter can be tolerated for 10-bit accuracy . . . . . . . . 116

Fig. 6.6 Schematic of the 15-stage ring VCO in the quantizer(single-ended); the delay cell circuit is shown in the bluedashed box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Fig. 6.7 Large-signal simulation of a 5-bit frequency-type VCO-basedquantizer. Both the single-ended result (left) and thepseudo-differential result (right) are presented. . . . . . . . . . . . . . . 118

Fig. 6.8 Small-signal simulation of a 5-bit frequency-type VCO-basedquantizer; with around �20 dBFS input, the 3rd-orderdistortion is about �76 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Fig. 6.9 The simulated VCO phase noise; it is �113 dBc/Hz at an offsetfrequency of 10 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Fig. 6.10 Schematic of the current-steering DAC; the resistor connectedto the ADC input and the DAC output forms a passivesubtractor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

xxii List of Figures

Fig. 6.11 Noise simulation of the feedback current-steering DAC and thepassive subtractor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Fig. 6.12 Transistor-level simulation result of the two-step open-loopVCO-based ADC. Top left PSD plot of the coarse quantizeroutput; top right PSD plot of the fine quantizer output; bottomleft PSD plot of the overall ADC output . . . . . . . . . . . . . . . . . . . 121

Fig. 6.13 Die photo of the two-step open-loop VCO-based ADC. . . . . . . . 122Fig. 6.14 Measured results of the two-step 1st-order VCO-based DSM

with �1 dBFS 12 MHz sine input. Top left PSD plot of thecoarse quantizer output; top right PSD plot of the fine quantizeroutput; bottom left PSD plot of the overall ADC output . . . . . . . 123

Fig. 6.15 The measured ADC SNR/SNDR as a function of the analoginput power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Fig. 7.1 VCO-based quantizer in a single-loop DR modulator . . . . . . . . . 128Fig. 7.2 Block diagram of a 0-DR MASH VCO-based ADC . . . . . . . . . . 128Fig. 7.3 The nonlinearity-cancellation principle in a 0-DR MASH

VCO-based ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129Fig. 7.4 Equivalent signal model of the proposed 0-DR MASH

VCO-based ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130Fig. 7.5 SNDR of the 0–1 MASH and 0–2 MASH VCO-based ADCs

as a function of the stage-gain mismatch. . . . . . . . . . . . . . . . . . . 132Fig. 7.6 ADC SFDR performance as a function of the normalized

gain of the VCOs and DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . 132Fig. 7.7 The presented 0–2 MASH VCO-based DR ADC . . . . . . . . . . . . 133Fig. 7.8 SNDR performance as a function of the clock jitter . . . . . . . . . . 134Fig. 7.9 Block diagram of a simplified CT loop to approximately

represent the 2nd stage in a MASH ADC . . . . . . . . . . . . . . . . . . 134Fig. 7.10 Impulse invariance transformation of the 2nd stage in the

presented 0–2 MASH VCO-based ADC . . . . . . . . . . . . . . . . . . . 135Fig. 7.11 Topology of the dual-input VCO-based fine quantizer

(single-ended) to realize the three-input adder . . . . . . . . . . . . . . . 137Fig. 7.12 Schematic of the sense-amplifier-based flip-flop . . . . . . . . . . . . . 138Fig. 7.13 Simulated phase noise performance of the VCO . . . . . . . . . . . . . 138Fig. 7.14 Schematic of the integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139Fig. 7.15 Discretely tunable capacitor for the loop filter. . . . . . . . . . . . . . . 140Fig. 7.16 Schematic of the operational amplifier in the integrator . . . . . . . 141Fig. 7.17 Small-signal equivalent block diagram of the operational

amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141Fig. 7.18 ADC SNDR performance as a function of the standard

deviation of the current of the global and internalDAC cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Fig. 7.19 Block diagram of the Wallace tree encoder . . . . . . . . . . . . . . . . . 143Fig. 7.20 Schematic of the mirror adder implemented in the

unary-to-binary encoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

List of Figures xxiii

Fig. 7.21 Chip microphotograph of the 0–2 MASH DR ADCprototype . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Fig. 7.22 Measurement setup for the 0–2 MASH DR ADC prototype . . . . 146Fig. 7.23 Measured PSD results of the 0–2 MASH DR ADC chip

prototype with an 8-MHz input. Top first stage; middlesecond stage; bottom complete ADC output . . . . . . . . . . . . . . . . 147

Fig. 7.24 Measured PSD results of the 0–2 MASH DR ADC chipprototype with a 4-MHz input . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Fig. 7.25 Measured PSD results of the 0–2 MASH DR ADC chipprototype with a 1-MHz input . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Fig. 7.26 Measured SNDR versus the input amplitude for different inputfrequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Fig. 7.27 Output spectrum of the two-tone measurement(at 10 and 11 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Fig. 8.1 Traditional analog R-C and Gm-C integrator . . . . . . . . . . . . . . . . 154Fig. 8.2 Simplified diagram of a R-C integrator, in which the opamp

has a finite DC gain and a finite GBW . . . . . . . . . . . . . . . . . . . . 154Fig. 8.3 Equivalent model of an R-C integrator, in which the opamp

has a finite gain and GBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155Fig. 8.4 Frequency-domain transfer function of a VCO . . . . . . . . . . . . . . 156Fig. 8.5 Block diagram of a N-stage VCO-based 1st-order integrator. . . . 156Fig. 8.6 Block diagram of a single-loop DR ADC with a VCO-based

integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157Fig. 8.7 Block diagram of a 2nd-order VCO-based DR ADC

with a VCO-based integrator [2] . . . . . . . . . . . . . . . . . . . . . . . . . 158Fig. 8.8 Block diagram of the proposed 0-DR MASH ADC with

VCO-based integrators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158Fig. 8.9 Block diagram of the presented fully-VCO-based 0-2 MASH

DR ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159Fig. 8.10 Clock timing of the presented fully-VCO-based ADC. . . . . . . . . 159Fig. 8.11 Signal model of the presented fully-VCO-based 0-2 MASH

VCO-based ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159Fig. 8.12 Schematic of the pseudo-differential VCO-based integrator. . . . . 161Fig. 8.13 Simulated phase noise performance of the VCO used in the

integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161Fig. 8.14 Schematic of the SA-based buffer in the VCO-based

integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162Fig. 8.15 Schematic of the two-state phase detector . . . . . . . . . . . . . . . . . . 163Fig. 8.16 Transfer function of the two-state phase detector . . . . . . . . . . . . 163Fig. 8.17 Schematic of the source-switched DAC cells in the

VCO-based integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164Fig. 8.18 Chip microphotograph of the fully-VCO-based 0-2

MASH DR ADC prototype . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

xxiv List of Figures

Fig. 8.19 Measured PSD results of the fully-VCO-based 0-2MASH DR ADC chip prototype with an 8-MHz input . . . . . . . . 165

Fig. 8.20 Measured PSD results of the fully-VCO-based 0-2MASH DR ADC chip prototype with a 4-MHz input . . . . . . . . . 165

Fig. 8.21 Measured PSD results of the fully-VCO-based 0-2MASH DR ADC chip prototype with a 2-MHz input . . . . . . . . . 166

Fig. 8.22 Measured ADC SNDR versus input amplitude . . . . . . . . . . . . . . 166Fig. 8.23 Output spectrum of the two-tone measurement

(at 10 and 11 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167Fig. 8.24 Digital correction setup of the fully-VCO-based 0-2 MASH

DR ADC chip prototype . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168Fig. 8.25 Digitally corrected PSD results of the fully-VCO-based 0-2

MASH DR ADC chip prototype . . . . . . . . . . . . . . . . . . . . . . . . . 168Fig. 8.26 Comparison of the SNDR and the bandwidth of the presented

work with the state-of-the-art DSM ADC designs(BW � 8MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Fig. 8.27 Comparison of the FoM and the bandwidth of the presentedwork with the state-of-the-art DSM ADC designs(BW � 8MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Fig. 9.1 Block diagram of the digital calibration for the two-stepopen-loop VCO-based ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Fig. 9.2 Topology comparison between the traditional MASH ADCand the presented VCO-based MASH ADC . . . . . . . . . . . . . . . . 176

Fig. 9.3 Improved 1–1 MASH structure for VCO-based ADC . . . . . . . . . 176Fig. 9.4 Block diagram of a purely-time-domain DR ADC . . . . . . . . . . . 176

List of Figures xxv

List of Tables

Table 2.1 Performance summary of different ADC architectures . . . . . . . . 26Table 5.1 Measurement summary of the CT DSM ADC with digital

calibration and shaped SC DAC . . . . . . . . . . . . . . . . . . . . . . . . . 100Table 5.2 Measurement summary of the CT DSM ADC with

capacitive local feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106Table 6.1 Measurement summary of the two-step open-loop

VCO-based ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124Table 7.1 Measurement summary of the 0–2 MASH

VCO-based DR ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150Table 8.1 Measurement summary of the fully-VCO-based 0-2 MASH

DR ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

xxvii

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