show daily - solid-state · that our 450mm development activities can be restarted if and when the...
TRANSCRIPT
The worldwide semiconductor capital equip-
ment market is forecast to increase 20.8 per-
cent this year to $38.44 billion, compared with
2013’s $31.82 billion, and another 10.8 percent
in 2015 to $42.6 billion, according to Semicon-
ductor Equipment and Materials International.
Also on Monday, the Semiconductor Indus-
try Association reported that global sales of
semiconductors were $26.86 billion in May, an
8.8 percent increase from a year earlier and a 2
percent improvement from April of this year.
Jonathan Davis, SEMI’s global vice presi-
dent of advocacy, said Monday that the semi-
SEMI Forecasts Double-digit Business Growth in 2014, 2015BY JEFF DORSCH
JULY 10, 2014
MOSCONE CENTER | SAN FRANCISCO, CALIFORNIA
THURSDAYSHOW DAILYSHOW DAILYSHOW DAILY8:00am-5:15pm Global Summit for Advanced ManufacturingSan Francisco Marriott Marquis
9:00am-12:00pm STS SESSION: 450mm Technology Development UpdateMoscone North, Hall E, Room 131
10:00am-4:45pm FLEXTECH ALLIANCE WORKSHOP: Flexible Hybrid Electronics for Wearable Applications—Challenges and Solutions San Francisco Marrriott Marquis
10:30am-12:30pm3D Printing: Science Fiction or the Next Industrial Revolution?SESSION PARTNER: SEMICO ResearchTechXPOT South, South Hall
1:30pm-3:30pm IoT Startup Showcase An SK Telecom Americas Innopartners ProgramTechXPOT North, North Hall
1:30pm-3:30pm Breakthrough Research TechnologiesTechXPOT South
continued on p 6Denny McGuirk, president and CEO of SEMI
DON’T MISS
Imagine being able to not only track and ad-
dress equipment degradation in real time, but
also analyze patterns in your factories’ equip-
ment and address potential issues before they
even present a problem.
It may sound too good to be true, but Mi-
crosoft’s Sanjay Ravi explained in Wednesday
morning’s keynote that this innovation is be-
coming available now to manufacturers.
In his keynote “The Art of Possible: How
Manufacturers are Leveraging Digital Tech-
nologies to Drive Business in a Connected
World,” Mr. Ravi gave his audience a glimpse
of the brave, new world that leveraging mo-
bility, social, cloud and big data offers them,
specifically siting product offerings and de-
velopments from Microsoft.
“The key priority is taking advantage of the
connected business networks and enabling
connected customer experience,” Mr. Ravi
shared. Building a data culture across one’s
organization can drive the right business pro-
cesses and models, he explained.
He used examples from Samsung and
AMD, who both utilized Cloud-based data
analytics programs to reduce costs, manage
energy and increase data warehouse perfor-
mances by jaw-dropping percentages. AMD,
The Connected Experience: A Manufacturer’s Dream? BY SHANNON DAVIS, WEB EDITOR
continued on p 6
SEMICON West 2014 attendees enjoyed technical sessions and interesting exhibits.
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THURSDAY | JULY 10, 2014
3SHOW DAILY
The news hit the semiconductor industry like
a thunder clap late last year.
ASML Holding announced that it was hold-
ing back, or pausing, its development of lithog-
raphy systems that could handle 450-millime-
ter silicon wafers. That information shocked
many observers, since ASML had only the year
before got Intel, Samsung Electronics, and Tai-
wan Semiconductor Manufacturing to commit
1.38 billion euros (about $1.82 billion) toward
research and development at ASML of extreme-
ultraviolet lithography and 450mm technology
over four years.
One year after that financing commit-
ment, those three customers decided to put
the brakes on the transition to 450mm wafers.
As ASML stated in its 2013 annual report:
“In November 2013, following our cus-
tomers’ decision, ASML decided to pause
the development of 450mm lithography sys-
tems until customer demand and the timing
related to such demand is clear. We believe
that our 450mm development activities can
be restarted if and when the industry demands
the introduction of 450mm. Since 450mm re-
quires both generic developments and wafer
size-specific developments, many of our em-
ployees involved in the 450mm project are do-
ing work that is just as relevant for future DUV
and EUV platforms. The teams and people
have therefore been reassigned
to different projects.”
Pundits quickly declared that
the industry transition to 450mm
was absolutely, completely dead.
The reality is more nuanced than
that.
Ryan Young of ASML says of
450mm, “Customers are not ask-
ing for it right now. The work is
sitting on the shelf.”
And ASML is not the only
game in town. Nikon Precision
has been working the Global
450mm Consortium (G450C) to
successfully develop a 450mm
immersion tool.
The three giant chipmakers aren’t embrac-
ing 450mm as avidly as they did a little while
ago, but that doesn’t mean 450mm is dead and
buried. At SEMICON West, the new Semicon-
ductor Technology Symposium will include a
450mm Technology
Development Up-
date on Thursday
morning, July 10, in
Moscone North.
Executives of
the G$50C will be
among the speak-
ers at that session.
Earlier this year, at
the SEMI Industry
Strategy Sympo-
sium, Paul Farrar,
general manager of
the G450C consor-
tium, said early work
has demonstrated
good results and that
he sees no real barri-
ers to implementing
450mm wafers from a technical standpoint.
Farrar showed impressive results from, etch,
CVD, PVD, CMP, furnaces, electroplating, wet
cleans and lithography processes and said the
inspection/metrology tools were in place to
measure results. “I don’t believe we will find
fundamental technology limiters,” he said.
“But we will have to keep working to find ways
to maximize the efficiency.”
G450C and its related group, the Facility
450 Consortium, formed a year ago, continue
their operations at the College of Nanoscale
Science and Engineering in Albany, N.Y., part
of the State University of New York system.
Also presenting in today’s STS session will
be Hamid Zarringhalam, Executive Vice Presi-
dent at Nikon Precision. He notes that “When
looking at advanced lithography system de-
velopment–450 mm scanners must simulta-
neously satisfy the aggressive performance
requirements for scaling (imaging, overlay,
focus, etc.) and the wafer size transition (pro-
ductivity, cost, and footprint). While there are
questions regarding how lithography tooling
benefits from the wafer size transition, Nikon
is taking full advantage of this opportunity to
build the next-generation tool platform with
an emphasis on 450 mm productivity enhance-
ments and performance innovation.”
So, although no real technical barriers are
seen, the 450mm transition seems to be on life
support for now, unless and until chipmakers
with big capital-expenditure budgets give it
the green light.
450mm: No Technical Challenges but Questions AboundBY JEFF DORSCH
A 450mm wafer is more than double the size of a 300mm wafer.
Ribbon CuttingKicking off SEMICON 2014 with the ceremonial ribbon-cutting cer-
emony (left to right): Karen Savala, president of SEMI North Ameri-
cas; Mark Adams, President, Micron and opening keynote speaker;
André-Jacques Auberton-Hervé, chairman, CEO and president of
Soitec, and chairman of the SEMI Executive Committee; and Denny
McGuirk, president and CEO of SEMI.
MOSCONE CENTER | SF, CA
4
Research forms the DNA of the semiconductor
industry — few other industries invest as much
as a percentage of revenue. Semiconductor
research has always driven the Moore’s Law
Mantra of continuously making things “cheap-
er, better, faster, and smaller.” This brought
the industry into the realm of nanotechnol-
ogy, where manipulation of just a few atoms
yields complex quantum effects. This requires
multi-faceted innovation — in materials, pro-
cessing and characterization techniques, and
advanced patterning to fabricate these tiny
devices. To explore the various dimensions
of this innovation, SEMICON West 2014 fea-
tures a session on “Breakthrough Research
Technologies.”
Dr. Thorsten Lill from Lam Research, who
will present at this session, explains, “As de-
vice dimensions and their allowed tolerances
approach the same order of magnitude as inter-
atomic distances, atomic scale processing will
soon be a necessity. We will discuss the frame-
work of developing production-worthy atomic
layer etch (ALE) to achieve layer-by-layer re-
moval with atomic fidelity.” This is nanotech-
nology at its best — where we are engineer-
ing materials by each atomic layer. Precision
engineering also requires precision simulation
and modeling, as Dr. Peter Ventzek of Tokyo
Electron will describe for plasma chemistries
used in etching and other processes.
We also need novel techniques to charac-
terize materials at the atomic level. Dr. John
Mardinly of ASU, also presenting at this
session, describes one such technique: “Ab-
erration-Corrected Transmission Electron
Microscopy provides numerous advantages
over conventional Field-Emission Trans-
mission Electron Microscopes. Resolution
is improved by 2-3 times, and imaging and
analysis can be conducted with lower accel-
erating voltages so that specimen damage is
reduced.” In conventional bright field imaging,
delocalization is eliminated so that interfaces
between materials are imaged precisely. In
Scanning Transmission Electron Microscopes,
the beam current density can be 8-10 times
higher than in a convention Field-Emission
Scanning Transmission Electron Microscope.
This dramatically improves the visibility of fea-
tures and enables chemical mapping through
Electron Energy Loss Spectroscopy (EELS)
or Energy-dispersive
X-ray Spectroscopy
(EDS) with atomic
resolution.”
Aside from tech-
nology drivers, new
market forces are
now re-shaping the
industry: the rise of
the individual con-
sumer as the domi-
nant end-user; the
application of tech-
nology to diverse
fields such as energy,
transportation and
healthcare; and the
rapid proliferation of the Internet of Things.
These entail complex functionality, which of-
ten requires complementing nanoscale digital
devices with “More-than-Moore” functions
like biological sensors, better analog and
power devices other silicon. Prof. Oliver Brand
will describe research advances in the “More-
than-Moore” areas of chemical microsensors,
inertial sensors and micromachined ultrasonic
transducers at the Center for Microelectrome-
chanical Systems (MEMS) and Microsystem
Technologies on the Georgia Tech campus.
This multi-dimensional, fast-paced re-
search requires academia, research institutes,
and the industry to work closely together, not
just to push the research, but also to imple-
ment it in the “real world” successfully. Prof.
Douglas A. Keszler from OSU will describe
how the Center for Sustainable Materials
Chemistry focuses on breakthrough research
to enable next-generation capabilities in semi-
conductor and display manufacturing, high-
lighting the technologies of spin-outs Inpria
and Amorphyx. Dr. Michael Khbeis of the
Washington Nanofabrication Facility (WNF)
at the University of Washington will describe
advances in packaging/3D integration, silicon
photonics, magnetic materials, superconduc-
tivity, photovoltaics, and quantum informa-
tion systems.
It is exciting to imagine what capabilities
such breakthrough research will enable in the
future. From cramming more than a billion
electronic transistors on a thumbnail, decod-
ing the human genome, and placing a powerful
computer in everyone’s pocket, how will tech-
nology change the world? Besides richer com-
puting, communications, and entertainment,
we can now also tackle large and meaningful
topical challenges, such as climate change,
energy and water conservation, implementa-
tion of renewables, and affordable, effective
healthcare. Information Technology and the
Internet of Things are already making a dent
in these challenges and enabling research as
discussed will accelerate this and help us im-
prove our lives and our planet.
University and research institutions are
increasingly important to help accelerate
technology advances. Learn more about the
latest — from speakers working in research
at Arizona State University, Georgia Institute
of Technology, Lam Research/KU Leuven/
imec Joint Project, Oregon State University,
TEL, U. of Washington — at the Breakthrough
Research Technologies session at SEMICON
West 2014.
Research underway at Georgia Institute of Technology.
Breakthrough Research in the Semiconductor IndustryBY PUSHKAR P. APTE
SHOW DAILY 5SHOW DAILY
Intel, Samsung Electronics, and Taiwan Semi-
conductor Manufacturing have made their
moves into three-dimensional semiconduc-
tors. Now it remains to be seen how the rest
of the semiconductor industry will make the
transition to 3DICs.
It’s not going to be another dimension
shrink, by any means. As difficult as the transi-
tion to fabrication with 28-nanometer features
was for many chipmakers (and remains so for
many second-tier semiconductor manufactur-
ers), that scaling shift will seem like child’s
play as integrated device manufacturers and
silicon foundries deal with silicon interposers,
through-silicon vias, and other accoutrements
of the 3D chip world.
Yole Développement estimates the value of
semiconductors with TSVs in 3DIC and 3D wa-
fer-level chip-scale packages – including ambi-
ent light sensors, CMOS image sensors, power
amplifiers, and inertial and radio-frequency
microelectromechanical system devices – was
$2.7 billion in 2012. It forecasts that such chips
will represent 9 percent of the semiconductor
market in 2017, with nearly $40 billion in value.
Transparency Market Research has a more
modest forecast for 3DICs. It estimates the
value of 3D chips in 2012 was $2.4 billion and
will rise at a compound annual growth rate of
18.1 percent over the next five years, hitting
$7.52 billion in 2019.
“Customers like to scale their devices for
greater performance or better battery life,”
says Brian Trafas, chief marketing officer of
KLA-Tencor. “They’re moving
from 2D to 3D.”
“The logic leader” (generally
known as Intel) made its move at
the 22-nanometer process node,
Trafas notes, while “the foundry
leader” (that would be TSMC) migrated to 3D
at 16nm, Trafas notes. In advanced 3D memory
chips, “one leader is out front,” he says, an-
nouncing that its wafer fabrication facility in
China is producing 3D NAND flash memories
(that’s Samsung).
As the technology leaders enter the brave
new world of 3D chips, “we do now see some
spending for 14- and 16-nanometer by found-
ries,” Trafas says.
Making 3DICs calls for multiple patterning
in photolithography and “more process steps,”
the KLA-Tencor executive says, which is good
for sales of process control equipment. “The
logic leader” experienced yield issues when
it started making 3D chips, and “we’re seeing
the same thing with foundries,” Trafas says.
“It’s very challenging.
“It’s somewhat like 28-nanometer. It’s typi-
cal of what you see at all new nodes,” he adds.
Despite the challenges in defects and yield
with 3DICs, “it should be successful,” Trafas
concludes.
At SEMICON West, 3DICs are under
discussion in several forums, including the
TechXPOT programs in Moscone Center’s
North and South halls.
3DICs Have Finally ArrivedBY JEFF DORSCH
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MOSCONE CENTER | SF, CA
6
conductor industry is seen growing 5 percent
to 10 percent in 2014, and noted that all world
regions posted growth in sales during May, a
statistical factor not recorded
since August 2010.
Discussing expenditures
on capital equipment, Da-
vis said, “The nature of the
spending is changing.” The
number of new wafer fabs
has dwindled in recent years,
and more spending is direct-
ed these days to upgrading
existing fabs.
2015 promises to be the
biggest year for semicon-
ductor equipment spend-
ing since 2000, Davis said.
While the equipment mar-
ket is growing more than 20
percent this year, the semiconductor materials
market will see more modest growth in 2014,
at 6 percent, he added.
Karen Savala, the president of SEMI Ameri-
cas, reviewed economic and technology trends
in the equipment and materials business dur-
ing Monday’s SEMI press conference. The
industry has gone through “one of the largest
consolidation periods in our history,” includ-
ing the pending blockbuster merger between
Applied Materials and Tokyo Electron Ltd.
(TEL), she noted.
The longstanding economics of Moore’s
Law is being challenged, she added. The In-
ternet of Things is a tremendous opportunity
for the chip-making business, yet it doesn’t
involve leading-edge technology, Savala said.
“Traditional node scaling seems to be slow-
ing,” she observed. Scaling is apparently de-
celerating below the 32-nanometer process
node, according to Savala,
but it may be advanced with
the introduction of new ma-
terials, new substrates, and
2.5D/3D packaging.
SEMI now forecasts that
wafer processing equipment
will grow 22.7 percent in
2014 to $31.12 billion, from
$25.36 billion in 2013, and
advance 11.9 percent more
in 2015 to $34.81 billion. Test
equipment is expected to see
a 12.5 percent increase this
year to $3.06 billion and pick
up by 1.6 percent next year to
$3.11 billion. Assembly and
packaging equipment is forecast to reach $2.52
billion in 2014, an 8.6 percent improvement
from last year, and growing 1.2% in 2015 to
$2.55 billion. Other equipment categories will
be up 22.5 percent this year to $1.74 billion
and up 21.8 percent next year to $2.12 billion.
SEMI 2014 mid-year equipment forecast.
Forecast� continued from p 1
for example, used Microsoft BI solutions to
improve operational agility and was reportedly
able to reduce resource support work needed
by 90 percent. Samsung, he reported, analyzed
10 times more data to make more efficient deci-
sions about energy management, using trend
statistics and histograms – decreasing their
costs by 75 percent.
“Given the explosion of the Internet of
Things, all of our equipment can be connected,”
said Mr. Ravi. “This means gathering big data
from embedded devices and transforming big
data into business information and insight.”
The implications are mind-boggling: manu-
facturers could anticipate production disrup-
tions remotely and take corrective action any-
time, anywhere.
And if that wasn’t enough to capture his
audience’s imagination, Mr. Ravi also shared
the Smart Elevator project Microsoft has in de-
velopment. When used in an office setting, the
Smart Elevators have the ability to learn office
workers behaviors and analyze their Cloud-
based work schedules to know 1) if they need
to get on the elevator as they approach it and
2) where they will need to go once they get on
the elevator. The result is a completely button-
less elevator, an elevator that anticipates your
schedule and is there right when you need it.
Whether it’s leveraging big data or Smart
Elevators, the connected workplace isn’t sci-
ence fiction: it’s possible and its potential is
undeniable.
Ravi� continued from p 1
Sanjay Ravi, Microsoft
Show�Daily�StaffPublished by Tradeshow Media Partners and Extension Media in partnership with SEMICON West.
Tradeshow Media PartnersMark [email protected]
Extension MediaVince [email protected]
Kevin ClarkeLayout and [email protected]
SEMIMichael DroegerDirector, Global [email protected]
Pete [email protected]
Jeff DorschContributing [email protected]
Ed KorczynskiContributing [email protected]
Shannon DavisContributing [email protected]
SHOW DAILY
THURSDAY | JULY 10, 2014
7SHOW DAILY
Everybody loves FinFETs!
Well, not everybody, really, is behind dou-
ble-gate or multiple-gate field-effect transis-
tors. There is a camp in the semiconductor
industry making the case for the leading al-
ternative, using fully-depleted silicon-on-
insulator technology. On balance, however,
most chipmakers are betting on the chips with
the tiny “fins.”
There’s also some disagreement and fudg-
ing on what is and isn’t a FinFET process. It’s
not a precisely defined term for many people.
Intel, for instance, was a leader in implement-
ing the architecture, but it doesn’t use the word
“FinFET,” preferring to describe its architec-
ture as a “3-D Tri-Gate transistor.”
Intel started using the Tri-Gate architecture
at the 22-nanometer process node and now is
employing it at 14nm.
Taiwan Semiconductor Manufacturing, the
world’s largest pure-play silicon foundry, is
using FinFETs at the 16nm process node. The
foundry has introduced its 16nm FF+ process,
a second-generation FinFET technology.
“Most of the major manufacturers are doing
FinFETs,” says Aaron Thean, vice president of
process technology and director of logic de-
velopment at imec. “Everyone is transition-
ing to FinFETs. The industry is moving in that
direction.”
Brian Trafas, chief marketing officer of
KLA-Tencor, says, “Most companies chose
FinFET.” With his company’s emphasis on
process control and yield management, KLA-
Tencor knows about some of the struggles in
implementing FinFET architectures. There is
some residual contamination with the etch-
ing and cleaning process steps, according to
Trafas. This often takes the form of “very small
residue on the sidewall of fins,” he says.
What about fully-depleted silicon-on-in-
sulator? “FD-SOI can help with some of the
scaling,” Trafas says. It is, however, what he
describes as “a niche area.”
STMicroelectronics has been the industry
champion of FD-SOI technology, and that’s
been a lonely position, for the most part, al-
though it continues to collaborate with CEA-
Leti and Soitec on implementing the technol-
ogy. GlobalFoundries committed to using ST’s
FD-SOI tech for 28nm and 20nm production
in 2012, and expects to put it into volume pro-
duction by the end of this year, for 28nm and
14nm processes.
In May, STMicroelectronics announced
that Samsung would use ST’s 28nm FD-SOI
tech for foundry customers. Samsung plans to
offer the process in early 2015.
“The agreement [for 28nm FD-SOI] con-
firms and strengthens further the business
momentum that we have experienced on this
technology,” ST Chief Operating Officer Jean-
Marc Chery said. “We foresee further expan-
sion of the 28nm FD-SOI ecosystem, to include
the leading EDA and IP suppliers.”
Meanwhile, process technologists are plan-
ning for FinFETs at 10nm, 7nm, and 5nm. Be-
yond that, it’s anyone’s guess what architecture
will prevail.
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MOSCONE CENTER | SF, CA
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The introduction of new materials, such as
III-Vs, into high-volume manufacturing of
semiconductors, likely will occur sometime
around the 7nm and/or 5nm nodes. III-V’s
introduction, along with the potential tran-
sition to 450mm wafers, and the increasing
expansion of global regulatory requirements,
will heighten environmental, health and safety
(EHS) concerns that must be addressed as the
industry goes forward. The Sustainable Man-
ufacturing Forum, held in conjunction with
SEMICON West 2014, features experts
in the manufacture of semiconductors, micro-
electronics, nanoelectronics, photovoltaics,
and other high-tech products.
One of the Sustainable Manufacturing Fo-
rum speakers, Richard Hill, Technology Infra-
structure manager at SEMATECH, will discuss
how the addition of III-V materials into the
high-volume manufacture of semiconductors
will bring sustainability issues to the forefront,
primarily driven by the toxicity of arsenic that is
used in much greater quantities in III-V produc-
tion. Challenges include wastewater treatment,
toxic gas detection control and abatement, and
the need for robust protocols to ensure opera-
tor and maintenance personnel safety. Hill will
speak at the Next Generation Eco Fab session
Wednesday, today.
SEMATECH recently completed a joint
study of III-V EHS challenges with the College
of Nanoscale Science and Engineering (SUNY
CNSE). The assessment consisted of running
300mm wafers through a representative 5nm
III-V process flow (Figure 1). (Many semicon-
ductor industry experts agree that III-V materi-
als will enter the process flows in high volumes
at 5nm.) Among the processes that will pose
the greatest challenges with respect to III-V
materials are MOCVD, CMP, wet etch/clean,
dry etch, and film deposition. The project was
heavily focused on understanding the levels
of arsenic that would be present in wastewa-
ter, as well as loading of other III-V materials.
The impact of III-V outgassing that could occur
during processing and the amounts of gases
that could be released when a tool is opened
for maintenance were of particular interest in
the project.
Among the high-level challenges associ-
ated with wet etch are the potential for arsine
and phosphine outgassing (during process-
ing). “Wet etch tools are designed to have a
controlled environment,” said Hill, “but they
are not like high-vacuum systems that are de-
signed to contain toxic gases.” Hill told SEMI
that if the exhaust system fails during the
processing of a wafer, it is critical to know the
risks and ensure mitigation. The SEMATECH/
CNSE project looked at a range of different
chemistries and identified those that are low
risk for arsine and phosphine generation (and
therefore, a low risk of outgassing) and those
that had a high risk of outgassing. The low risk
chemistries are, naturally, the ones that the
industry should try to design into a III-V flow.
The joint project also evaluated the III-V
loading in wastewater from the wet etch pro-
cess. “There were measurable quantities of
arsenic in the waste stream,” said Hill. Though
he added that while the levels weren’t signifi-
cantly high, some treatment of the waste water
would have to be done depending on what’s
allowable within local discharge limits and per-
mits. With the industry looking ahead to 5nm
and already designing the fabs of the future,
Hill believes that these results will be impor-
tant for specifying wastewater treatment.
The joint SEMATECH/CNSE project also
evaluated the wastewater stream from the burn
wet scrubber when III-V materials are used in
a contact etch (dry) process. The study found
measurable arsenic in the wastewater. “Fabs
of the future will need wet treatment facilities
for arsenic and indium,” Hill told SEMI. “In
recent years, concerns about indium have been
elevated, and we believe that tighter restric-
tions on it will be introduced in the future.”
Chamber clean is also critical when etching
(dry) III-V materials. “If you don’t do the right
type of cleaning regimen, you could have next-
Industry Sustainability Efforts Mount with III-Vs and other Advanced TechnologiesBY DEBRA VOGLER, SEMI
Example 5 nm III-V flow: key ESH challenges
1
III-V MOCVD • Pyro/toxic chemistry • MOCVD abatement • Post epi AsH3/PH3 outgassing
CMP • AsH3/PH3 outgassing • Waste water treatment
Dry Etch • Vac system contamination • Abatement & waste water treatment
Wet Etch & Clean • AsH3/PH3 outgassing • Waste water treatment
Film Deposition • Outgassing, contamination • Abatement & waste water treatment
Figure�1. Example 5nm III-V flow: key ESH challenges. SOURCE: SEMATECH continued on p 10
SHOW DAILY
THURSDAY | JULY 10, 2014
9SHOW DAILYSCW14-ED_Jpn14_PQ.pdf 1 6/12/14 3:33 PM
Logitech demonstrates Tribo CMP SystemLogitech’s Tribo system offers nano-
meter level material removal capability
on either individual die or wafers up to
100mm diameter. This CMP solution is
suitable for a wide variety of wafer/
substrate materials used in todays de-
vice fabrication processes. The Tribo
CMP system has been designed from
the ground up to achieve the highest
possible standards of processing con-
trol. This benchtop solution is ideal for
research of wafer processes, including
their associated wafer, pad and slurry
interactions. This highly versatile so-
lution achieves industry standards in
control and layer removal for CMP
while producing laser quality surfaces
(0/0 scratch dig) and Ra to subnano-
meter levels. Logitech is in Booth 429.
YES ovens for proper curing of polyimide layersThe YES-VertaCure automated, high
temperature cure series of ovens is
designed for today’s most advanced
MEMS and semiconductor process ap-
plications (including WLP and RDL).
Up to 50 wafers (200mm or
300mm) are loaded into a stainless
steel cassette-type rack on the oven
chamber door and, when loading is
complete, it is lifted into the vacuum
chamber. Yield Engineering Systems
is in Booth 1228.
MOSCONE CENTER | SF, CA
10
wafer contamination.” Additionally, without
the proper protocol, maintenance personnel
could be exposed to arsine or phosphine when
the chamber is opened, depending on the pro-
cess. The cleaning protocol is highly dependent
on the type of etch being done, and each type
could have different requirements.
For Hill, the key takeaway from the joint
evaluation was that, while there are risks
when processing III-V materials, there are no
showstoppers — solutions can be engineered.
“People should take these risks seriously, but
they shouldn’t be scared off by them,” said Hill.
Sustainability and the Role of Collaboration and StandardsSteve Moffatt, CTO, Front-end Equipment at
Applied Materials (also a speaker at the Next
Generation Eco Fab session at the Sustainable
Manufacturing Forum at SEMICON West),
told SEMI that many established procedures
for dealing with arsine and phosphine already
exist. He views the efforts by the industry going
forward as one of accurately quantifying the
size and scope of the problem. “The methods
are in place, but the absolute quantities of III-
Vs will be substantially higher,” said Moffatt.
Additionally, other emissions (e.g., PFCs)
that are well regulated and generally under-
stood, will see an increase in the quantities as
a result of more layers being processed for 3D
chips. Even the potential transition to 450mm
wafers will figure into the industry’s need for a
more accurate scope of the EHS challenges in-
volved. The increase in wafer size will naturally
lead to larger manufacturing equipment noted
Moffatt and that, in turn, will drive increases in
energy, water, and process chemical consump-
tion at both the tool and fab levels.
As regulatory pressure increases on a global
scale, the situation also becomes more com-
plex. Beyond the use of new materials such as
III-Vs and nanomaterials, Moffatt commented
that new methods of energetics (i.e., ways of
putting energy into a processing system) will
require very careful and close assessment of
the risk control measures. Another sustain-
ability issue arises
from the basic fact
that, as opposed to
the highly prevalent
element of silicon
in the earth’s crust,
many of the newer
materials being used
in higher quantities
for semiconductor
manufacturing (e.g.,Ga, As, etc.) are much less
abundant. These exotic materials, of necessity,
must be handled in the most efficient of ways.
Going forward, there will be increased
regulatory pressure to reduce a fab’s car-
bon footprint and produce more sustainable
products. Moffatt says the industry can ex-
pect more pressure to reduce greenhouse gas
(GHG) emissions along with adhering to con-
flict minerals regulations and managing EHS
concerns throughout the entire life-cycle of a
product (Figure 2). “One company can’t do it
on its own, it’s a life-cycle consideration,” said
Moffatt. “If we have the right collaboration
together, we have a greater probability with
the right kinds of standards of bringing good,
effective green chemistry solutions to high-
value problems.”
Regarding standards activities on energet-
ics, Moffatt pointed to ongoing collabora-
tion and hazard assessment between SEMI,
SEMATECH and other industry groups. “We
will need to continually evaluate the need for
additional standards activities — both new
and updates — in addition to industry collabo-
ration on “Green” chemistry,” said Moffatt.
“As a starting point, sustainability concerns
could be built into the initial assessment of
new chemicals and processes, which will
begin the discussion and raise awareness of
these issues.”
Hill (SEMATECH) and Moffatt (Applied
Materials) will be joined by speakers from
IMEC, Intel, Samsung, Air Products, and MW
Group at the “Next Generation Eco Fab” ses-
sion of the Sustainable Manufacturing Forum.
Figure�2. Consensus building in multi-stakeholder life-cycle risk assessment of manufacturing technology and products. SOURCE: Applied Materials (used with permission of ITRS)
Sustainability� continued from p 8
“Wet�etch�tools�are�designed�to�have�a�controlled�environment,�but�they�are�not�like�high-vacuum�systems�that�are�designed�to�contain�toxic�gases.”
—RICHARD�HILL,�SEMATECH
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MOSCONE CENTER | SF, CA
12
Technology innovation isn’t slowing down. But
its steady acceleration isn’t happening spon-
taneously, and Tuesday’s Silicon Innovation
Forum keynote from Professor of Innovation
Dr. Bob Metcalfe outline how he believes to
effectively drive the complex cycle that is mod-
ern-day innovation.
“Change in itself is not improvement – the
crux of the matter is in innovation manage-
ment,” said Dr. Metcalfe. “Ideas are a dime a
dozen, and most are bad ideas.”
When it comes to innovating, Dr. Metcalfe
has a lengthy resume to prove he knows what
he’s talking about: Internet pioneer, inventor
of Ethernet, co-founder of 3Com Corpora-
tion, publisher-CEO of IDG/Info-World – his
credentials are seemingly endless. So, when
he began to explain the ecology he believed
needed to develop the most effective innova-
tion system, his audience sat up and took notes.
Dr. Metcalfe explained that, in his experi-
ence, the most effective, successful innova-
tion ecology is comprised of seven key players:
funding agencies, research professors, gradu-
ating students, scaling entrepreneurs, venture
capitalists, strategic investors, and early adopt-
ers. In discussing funding agencies, he also ad-
dressed the sometimes-sticky role of research
universities in driving innovation.
“Are research universities up to it? Are they
up to doing our research for us?” he mused.
“They’re not well-managed; they’re heavily
governed – we need to keep universities com-
peting with each other and that will improve
their management.”
“Universities don’t like it when I say that,”
he joked.
Research universities are also up against
a new kind of challenge, he pointed out – the
growing popularity of online campuses. Dr.
Metcalfe said that the affect of this on universi-
ties’ abilities to effectively carry out research
has yet to be seen, but it certainly something
that manufacturers ought to consider when
discussing partnerships with research univer-
sities in the future.
Dr. Metcalfe also suggested that giving IP
to researching professors or students, the true
inventors, might provide added incentive for
increased participation in research programs
at institutions.
So, where will the next great innovation be?
Dr. Metcalfe said he, albeit biasedly, supports
more innovation in networking, but encour-
aged the audience to seriously consider pursu-
ing entirely new and crucial forms of innova-
tion, such as making solar energy affordable.
“The world’s most important problems
will not be solved by yet another website,” said
Dr. Metcalfe. “We need to address how to get
this new generation to think about innovating
things that matter.”
SEMI announced this week that Martin An-
stice, president and CEO, Lam Research
Corporation; Kevin Crofton, president and
COO, SPTS Technologies; Tien Wu, COO,
ASE Group; and Guoming Zhang, executive
vice president, Sevenstar Electronics, were
elected as new directors to the SEMI Interna-
tional Board of Directors in accordance with
the association’s by-laws.
Six current board members were re-elected
for a two-year term: Nobu Koshiba, president
and representative director, JSR Corporation;
Yong Han Lee, chairman, Wonik; Sue Lin, vice
chairman, Hermes Epitek; Toshio Maruyama,
chairman, Advantest Corporation; Tetsuo
Tsuneishi, vice-chairman of the board, Tokyo
Electron, Ltd.; Natsunosuke Yago, president
and representative director, chairman of the
board, Ebara Corporation.
Additionally, the SEMI Executive Com-
mittee confirmed the continued leadership by
André-Jacques Auberton-Hervé, chairman,
CEO and president of Soitec, as SEMI chair-
man and Yong Han Lee, chairman of Wonik,
as SEMI vice-chairman.
The leadership appointments and elected
board members’ tenure becomes effective at the
annual SEMI membership meeting, to be held
Wednesday, July 9, during the SEMICON West
2014 exposition in San Francisco, California.
“We are honored to have four distinguished
industry leaders joining the SEMI Board and
appreciate the continued service of those that
have been reelected,” said Denny McGuirk,
president and CEO of SEMI. “The SEMI Board
reflects the regional and market diversity of
our worldwide membership. Their service,
commitment and leadership are tremendous
assets for our association and our industry.”
SEMI’s 20 voting directors and 11 emeritus
directors represent companies from Europe,
China, Japan, Korea, North America, and Tai-
wan, reflecting the global scope of the associa-
tion’s activities.
How to Drive and Motivate Modern-day InnovationBY SHANNON DAVIS, WEB EDITOR
SEMI Announces New Board Elections and Leadership Appointments IPG Photonics
Micromachining WorkstationIPG Microsystems (Booth 1345) is show-
ing the new IX-280-ML system which
provides maximum micromachining
flexibility by supporting up to two la-
ser types in a single micromachining
workstation. The system combines a
Class-1 workstation including part-han-
dling stages, vision systems and control
electronics, integrated with either one or
two lasers. Each laser is equipped with
its own beam delivery system appro-
priate for the application, with options
including fixed focused beam, fixed
shaped beam, scanning galvanometer,
and thermal cutting heads. Both fiber-
delivery and free-space laser types are
supported. Applications include R&D,
where extreme equipment flexibility is of
paramount importance, and production
applications where both very fine mi-
cro machining, and also thicker-material
micromachining functions are required.
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MOSCONE CENTER | SF, CA
14
Solid State Technology and SEMI yesterday
announced the recipient of the 2014 “Best of
West” Award — Nikon Corporation — for its
NSR-S630D Immersion Scanner. The award
recognizes important product and technology
developments in the microelectronics supply
chain. The Best of West finalists were selected
based on their financial impact on the industry,
engineering or scientific achievement, and/or
societal impact.
Nikon has clearly demonstrated leadership
with ArF immersion tools, particularly in the
area of 450mm.
At SEMICON West this week, a collection
of the first fully patterned 450mm wafers —
using a Nikon immersion lithography tool —
were on display at the newly merged SUNY
CNSE/SUNYIT exhibit, booth 517, located in
the Moscone Center’s South Hall.
The Nikon immersion scanner will join
existing 450mm infrastructure at the Albany
NanoTech Complex in April of 2015 in accor-
dance with the project timeline. This critical
milestone will enable G450C founding mem-
bers and CNSE to perform 10nm and below,
full wafer photolithography, while optimizing
tool configuration and performance.
The Best of West award-winning NSR-
S630D ArF Immersion Scanner leverages the
well-known Streamlign platform, incorpo-
rating further developments in stage, optics,
and autofocus technology to deliver unprec-
edented mix-and-match overlay and focus
control with sustained stability to enable the
10/7 nm node. The Nikon Corporation booth
is in South Hall, Booth 1705.
Nikon Precision Executive Vice President,
Hamid Zarringhalam, commented that “Nikon
Corporation is honored to receive this presti-
gious award. Our global Nikon team continues
to extend immersion technology with innova-
tive solutions like the NSR-S630D to meet our
customers’ aggressive next generation produc-
tion requirements. This award caps off an ex-
citing SEMICON for us, following the CNSE/
SUNYIT announcement of the Nikon delivery
of the world’s first fully patterned 450mm im-
mersion wafers.”
The NSR-S630D leverages established
immersion technology, while incorporating
key innovations to deliver MMO capabilities
below 2.5 nm and throughput greater than 250
wafers per hour, in addition to critical overlay
and focus “sustained stability.”
Six speakers discussed developments in de-
signing and manufacturing silicon photon-
ics devices in a TechXPOT North session on
Wednesday morning.
Attendees heard from representatives of
IBM, Oracle, Compass-EOS, Luxtera, CEA-
Leti, and Aurrion.
IBM’s Jean Trewhella said her company has
been working on optical interconnect for a long
time, and “we’re moving the technology into
our Burlington fab.” In developing a “flexible
platform” for silicon photonics, IBM is shoot-
ing for bringing the cost down to 2.5 cents per
gigabit per second, she noted.
IBM designed built-in self-test into its sili-
con photonics devices, so it could do wafer-lev-
el test on the chips, Trewhella said. Fabrication
was slotted at Burlington, Vt.’s 200-millime-
ter wafer fabrication facility in the interest
of containing costs. Dimensions on the chip
fell into the range of 90 nanometers down to
65nm, according to Trewhella. “There is no
additional cost benefit from scaling photonic
components,” she said.
Working with IBM in silicon photonics is
Aurrion, a startup based in Santa Barbara,
Calif. Eric Hall, the company’s vice president
of business development, said Aurrion is in-
tegrating III-V semiconductors atop silicon
waveguides to develop large wavelength-di-
vision multiplexing arrays. Indium phosphide
and silicon chips are being employed in its
products, along with indium-gallium-arsenide
absorbers in its photodiodes.
“Integrating on silicon allows photonics to
leverage the cost/volume/yield of established
fabrication and packaging infrastructure,”
Hall said. He added, “Aurrion is hiring!”
The session also heard from Jack Cunning-
ham of Oracle, Shuki Benjamin of Compass-
EOS, Peter De Dobbelaere of Luxtera, and
Hughes Metras of CEA-Leti.
Solid State Technology and SEMI Announce the 2014 “Best of West” Award Winner
Development of Silicon Photonics Devices Discussed in ForumBY JEFF DORSCH
Intel’s experimental photonics chip can move data at 50Gbps.
Receiving the Best of West award: Holly Magoon, senior marketing manager, and Butch Berry, service order administration manager, Nikon Corporation.
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ClassOne DailyNewsCov4.indd 1 6/19/14 11:24:16 PM