semiconductor technology for integrated circuit front...

NSS-MIC Short Course, October ‘06Giovanni Anelli, CERN

IEEE Nuclear Science Symposium & Medical Imaging Conference

Short Course 3: Integrated Circuit Front Ends for Nuclear Pulse Processing

29th October 2006

Giovanni AnelliCERN - European Organization for Nuclear Research

Physics DepartmentMicroelectronics Group

CH-1211 Geneva 23 – [email protected]

Semiconductor Technology for Integrated Circuit Front Ends

2NSS-MIC Short Course, October ‘06Giovanni Anelli, CERN

Outline

• Operation and characteristics of MOS and Bipolar transistors

• Sub-micron CMOS and BiCMOS technologies

• Feature size scaling

• Radiation effects and reliability

• Mixed-signal circuits


Outline


MOS transistor equations and characteristicsMOS transistor small-signal equivalent circuitBipolar transistor equations and characteristicsBipolar transistor small-signal equivalent circuit

• Sub-micron CMOS and BiCMOS technologies• Feature size scaling• Radiation effects and reliability• Mixed-signal circuits

In this section we will see (or maybe review for many of you!) the basic operating principles and most important formulas for MOS and bipolar devices.


The MOSFET

The basic idea behind Field Effect Transistors (FETs) was first patented by

J. Lilienfeld in 1930 for the MESFET (MEtalSemiconductor FET) and in 1933 for the MOSFET (Metal Oxide Semiconductor

FET). But we had to wait until 1960 to have a technology capable of producing

working devices.

The first working MOSFET was made in 1960 at the Bell Laboratories byD. Kahng andM. M. Atalla.


The (N)-MOS transistor

Y. Tsividis, Operation and Modeling of The MOS Transistor, 2nd edition, McGraw-Hill, 1999.

x

y

z

GATE

SOURCE

DRAIN

SUBSTRATE

What is a MOS transistor?

Analog circuits: amplifier (V to I)

Digital circuits: switch

This slide shows a simplified NMOS transistor. It is a 4 terminal device. The gate is on top of a thin layer of silicon dioxide. Underneath the silicon dioxide we have the channel, which puts in communication source and drain. The bulk (or body or substrate) is the fourth terminal (not to be forgotten).

The direction y is also called “vertical”, direction x “horizontal”. The distance between the source and drain diffusions in the x direction is called gate length L. The channel width W is the width of the source and drain diffusions in the z direction.

The gate is normally made with highly doped polysilicon.

The example in the slide is for a NMOS. For a PMOS we have something very similar, but with all the dopings changed. Source and drain are p-doped diffusions for a PMOS. The gate is normally polysilicon with a high n-doping for NMOS and p-doping for PMOS. The “substrate” of a PMOS will be n-doped. In a p-substrate CMOS technology the PMOS transistors will therefore be built in an n-well. In advanced CMOS processes we might have a well for the NMOS transistors too.

The symbol for a PMOS is similar but the arrow for the source terminal goes towards the gate. In textbooks and papers you can also find other symbols.

We will spend quite some time explaining how a MOS transistor works, but essentially we can say that for analog circuits it is normally used as a voltage to current amplifier (more precisely as a voltage to current converter), and for digital circuits as a switch.


Linear and Saturation regions

n+ n+

SG

D

n+ n+

SG

D

LINEAR REGION (Low VDS):Electrons are attracted to the SiO2 – Siinterface. A conductive channel is created between source and drain. We have a Voltage Controlled Resistor (VCR).

SATURATION REGION (High VDS):When the drain voltage is high enough the electrons near the drain are insufficiently attracted by the gate, and the channel is pinched off. We have a Voltage Controlled Current Source (VCCS).

Rising Vg first depletes the p-type silicon under the gate from holes. This means that the acceptor ions of the p-doped substrate become negatively charged. Rising Vg again will call more electrons form the source and drain, where they are zillions! A conductive channel is formed.

When we apply a Vds we will have less electrons close to the drain than to the source. Why? Because the space charge region close to the drain is larger, and therefore it has already more negative charges (ions) to compensate for the positive charges on the gate. Therefore we will have less free electrons close to the drain than to the source. Rising Vds at a certain point the channel close to the drain is pinched off, and the device enters the saturation region.

For Vds small enough compared to Vgs (I will be more quantitative later) the current flowing between source and drain depends linearly on Vds. We have a resistor. The resistance depends on the “size” of the channel. The more voltage on the gate, the more electrons in the channel, the less resistance we will have.

For Vds big enough compared to Vgs the channel is “pinched-off”, Ids does not depend as a first approximation on Vds anymore and we have a current source. The amount of current is again controlled by Vgs.

Another way to look at saturation is the following. The current is constant along the channel: charge carriers are slower closer to the source and faster closer to the drain. Thus more electrons are needed on the source side than on the drain side, and the channel is pinched-off.


Drain current vs Drain voltage

0.0E+00

5.0E-06

1.0E-05

1.5E-05

2.0E-05

2.5E-05

3.0E-05

0.0 0.5 1.0 1.5 2.0 2.5

VDS [ V ]

I DS [

A ]

Saturation region (VCCS)

Linear region (VCR)

Output conductance

@ three different VGS

This is a real device measurement !

Locus of IDS_SAT vs VDS_SAT

Here we better illustrate with a real measurement what explained in the previous slide.

Let’s first focus on one of the 3 curves, for example the topmost. Here we have a fixed VGS and we increase the VDS from 0 to VDD. When VDS < VDS_SAT (the drain-to-source saturation voltage), the transistor is in linear region and it behaves as a Voltage Controlled Resistor (VCR). The value of the resistor is the inverse of the slope of the curve. When VDS is high enough (> VDS_SAT) then the channel is pinched off close to the drain. From now on, the current does not depend from VDS anymore (but only as a first approximation), and the device is a Voltage Controlled Current Source (VCCS). As it is seen in the curves, the current still increases with VDS, due to an effect called Channel Length Modulation (see later). The slope of the IDS vsVDS characteristics in the saturation region is called Output conductance.

In the linear region (VCR), the value of the resistor is controlled with the gate voltage. In the plots, the higher the slope the higher the gate-to-source voltage. This makes sense, as a bigger VGS means that the channel is richer in electrons, so less resistive, so the conductance (slope of the plot in linear regions) is higher.

In the saturation region (VCCS), the device behaves as an almost ideal VCCS, and the current is controlled again by VGS. The higher VGS, the higher the current.


Drain current vs Gate voltage

This is also a measurement, same device.

0.E+00

2.E-04

4.E-04

6.E-04

8.E-04

1.E-03

1.E-03

1.E-03

2.E-03

-0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4

VGS [ V ]

I DS [

A ]

Su

bth

resh

old

re

gio

n

Lin

ear

reg

ion

(g

reen

) an

d

satu

rati

on

reg

ion

(re

d)

High field (vertical and longitudinal)

effects

red

green

The SLOPE of this plot is called

Transconductance, and is a very

important parameter for

analog design (is the “gain” of the

V-to-I “amplifier”).

THRESHOLD VOLTAGE

This plot shows how the drain-to-source current varies with VGS, for two different VDS voltages: the lower plot is with VDS < VDS_SAT (device in the linear region), the higher is for VDS > VDS_SAT (device in saturation).

In both cases, we can see that the current is practically 0 for VGS voltages below a value called threshold voltage (VT). For VGS voltages above VT, the device current increases, more or less rapidly depending on the value of VDS.

The region in which VGS is below VT is called Subthreshold region. For VGS > VT we will be in the linear region or in saturation, depending on the value of VDS.

The slope of the IDS vs VGS plot is called transconductance, which tells us how much the drain-to-source current varies when varying the gate-to-source voltage. It expresses the “gain” of our voltage to current “amplifier”, and it is one of the most important parameters in analog design.

When VGS and/or VDS are sufficiently high, the vertical and longitudinal electric fields in the device become high enough to cause some problems, such as, for example, a reduction of the transconductance and the saturation of the carrier speed. We will discuss these issues a bit more in detail later.


Log(IDS) vs VGS

Exactly same measurement as before, but semi log scale

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

-0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4

VGS [ V ]

I DS [

A ]

LEAKAGE CURRENT

THRESHOLD VOLTAGE

STRONG INVERSION

WEAK INVERSION

SUBTHRESHOLD SLOPE

red

green

This plot is the same as before (Ids current vs Vgs voltage), but the y axis is in log scale. We can see from this plot that there is a current flowing in the device even for voltages Vgs smaller than Vt.

This current (called subthreshold current) is orders of magnitude smaller than the current flowing above threshold, but it has the important property of varying exponentially with the Vgs voltage (linear part of the characteristic). The MOS transistor behaves here almost as a bipolar (as we will see later).

The subthreshold region (Vgs < Vt) is also called weak inversion region, opposed to the strong inversion region (for Vgs > Vt).

Another important parameter to be defined is the leakage current, which is the current flowing in the device when Vgs = 0 V.


Equations: strong inversion

2TGSDS )VV(

n2I −β=

DSTGSGS

DSm I

n2)VV(

nVI

gβ=−β=

∂∂=

SATURATION REGION:

SAT_DSTGS

DS Vn

VVV =−>

Transconductance:

LW

Cox μ=βx.1g

ggn

m

mbm ≈+=ox

SiOox t

C 2ε

=BS

DSmb V

Ig

∂∂=

DSDS

TGSDS V)2

nVVV(I −−β=

LINEAR REGION:

SAT_DSTGS

DS Vn

VVV =−<

DSGS

DSm V

V I

g β=∂∂=Transconductance:

Here we have the equations for the MOS transistor in Strong Inversion (Vgs > Vt).

The voltage (Vgs – Vt) is also called gate overdrive, and tells us how much we have biased the gate above threshold. The drain-to-source saturation voltage is linked to the gate overdrive.

Linear region: for small Vds voltages, the current varies (almost) linearly with Vds (we have a resistor). How much it deviates from linearity depends on the value of Vds compared to the gate overdrive (and therefore Vds-sat). The closer we are to the transition between linear region and saturation, the more it deviates from linearity. The slope of the Ids vs Vds plot (inverse of the resistance of the VCR) is given by Beta*(Vgs – Vt –n*Vds). For a fixed gate overdrive, we have an almost constant value resistor only when Vds <<< Vgs – Vt. The transconductance in this region is not very interesting, as it is very small.

Saturation region: here the current does not depend on Vds anymore (we have already mentioned that this is true only as a first approximation), and it depends on the square of the gate overdrive voltage. The transconductance can be expressed as a function of the gate overdrive voltage or as a function of the drain-to-source current (this is a useful equation when designing a circuit).

In all the equations we have the parameter Beta. This is given by the product of the aspect ratio W/L of the transistor, of the mobility and of the gate oxide capacitance per unit area Cox. W and L are respectively the transistor gate width and length. The mobility of the carriers depends on the kind of carrier: electrons are faster than holes. Cox depends on the gate oxide dielectric constant and is inversely proportional to the gate oxide thickness.

n is a number which is close to one. It is expressed as a function of the bulk transconductance and of the gate transconductance. What is the bulk transconductance? We can vary the current in the device also varying the bulk-to-source voltage, not only varying the gate-to-source voltage. This is a somewhat less effective way of modulating the drain-to-source current. Therefore, the bulk transconductance is normally only a fraction of the gate transconductance.

Another thing to notice: the transconductance (we always refer to the gate transconductance if not differently specified) can be expressed as a function of Beta and of the drain-to-source current. Therefore it depends on:

uCox, a technology parameter: this is fixed once the technology is chosen

W/L, a geometrical parameter: this is specified by the circuit designer, but is fixed once the circuit is fabricated

IDS, a design parameter: this is also specified by the designer, and can be made variable in the real circuit.

One last important aspect to stress is that all these equations are valid only as a first approximation. They are all good for back-of-an-envelope calculations and to understand better how the device works and how the parameters, voltages and currents are linked between each other. But in a modern MOS device there are many effects which make the real device behavior departing from these ideal formulae.


Equations: weak inversion

)e(1eLW

II t

DS

t

GS

nV

nV

D0DSφ

−φ −=

t

DS

GS

DSm n

IVI

gφ

=∂∂=

K300mV25q

kTt @ ≈=φ

tDS n4V φ>

Almost like a bipolar transistor (see later)!

t

GS

nV

0DDS eLW

II φ=

If then the drain current does not depend on VDS any longer (saturation)

In weak inversion, the drain-to-source current depends exponentially on Vgs. The (normally unwanted) dependency of the current on Vds can be eliminated at relatively low Vds voltages, just a few thermal voltages (this becomes very interesting at low temperatures!). When Vds is high enough, the device becomes an excellent VCCS.

What is very important here is that the transconductance depends only on the drain-to-source current, and not on the device dimensions anymore (as long as the device is in weak inversion).

Also, in this region the transconductance is proportional to the current (and not to the square root of it, as it is the case in strong inversion).


Output conductance

ΔVΔI

VDSVD VD’

IDS

ID

ID’

L-LL

VI

VI

G Dout Δ

Δ⋅Δ

=ΔΔ=

n+ n+

SG

D

ΔLL

0.0E+00

5.0E-06

1.0E-05

1.5E-05

2.0E-05

2.5E-05

3.0E-05

0.0 0.5 1.0 1.5 2.0 2.5

VDS [ V ]

I DS [

A ]

Dashed lines:ideal behavior

The non-zero output conductance is related to a

phenomenon calledchannel length modulation

As we have already mentioned, in strong inversion and in saturation our MOS transistor is a VCCS, but it is not ideal. The current still changes with Vds. The slope of the Ids vs Vds characteristics in saturation is called output conductance of the transistor, and gives an indication of the amount of non ideality of the current source. As we will see later, together with the transconductance the output conductance is another very important parameter for analog design.

The fact that Ids increases with Vds is due to a phenomenon called channel length modulation. Increasing the drain voltage increases the space-charge region around the drain. This moves the pinch-off point in the channel towards the source; it is like shortening the channel, and therefore the current increases.

It can be shown that the output conductance decreases (i.e. becomes better) for longer channels: this can be easily understood, as in a longer channel a variation in the position of the pinch-off point will have a smaller effect.

For a given device dimension, the output conductance increases with the current.


Output conductance / resistance

)V1(I)V1()VV( n2

I DSSAT_DSDS2

TGSDS λ+⋅=λ+−β=

SAT_DSDS

DSdsout I

VI

gg ⋅λ=∂∂==

Drain-to-source current in saturation

Output conductance Output resistance

Remember: λ is proportional to 1/L

SAT_DS

E

SAT_DSds0 I

LVI

1g1

r⋅=

⋅λ==

)N,V(fLLL

LV1

DopingDSDS

where =ΔΔ−

Δ⋅=λ

The dependency of the drain-to-source current in saturation on the drain-to-source voltage has to be modeled in the equations. This is done with a parameter called “lambda”, which in the ideal case is = 0.

The output conductance can then be expressed as the product of lambda and of Ids at the onset of saturation (i.e. @ Vds = Vds_sat).

The inverse of the output conductance is called output resistance (ideally infinite).

As we have already mentioned, lambda depends on the channel length L. lambda can be expressed as a function of L and of a voltage (per unit channel length !!!), in a way similar to what is done for the bipolar transistor (Early voltage),

The output conductance is a very difficult parameter to model, especially in advanced deep submicron processes, as it is influenced by many effects.


Equations: addendum

Sm

m'm Rg1

gg

+=

( )SiSisbT VV φ−φ+⋅γ=ΔBulk effect

)VV(nL2

1Cg

21

f TGS2gs

mmax −μ

π=

π= in s.i.Maximum

frequency

Source parasitic resistance

Vertical electric field effect )VV(1 TGS

0

−θ+μ=μ

K. R. Laker and W. M. C. Sansen, Design of Analog Integrated Circuits and Systems, McGraw-Hill, 1994, Chapter 1.

ox

aSi

C

Nq2 ε=γ

There are a few more effects / equations which we need to add:

-Bulk effect: the threshold voltage depends on the source-to-bulk voltage.

-There are several parasitic resistors in an MOS transistor. One of the most disturbing is the source parasitic resistance, which results in a decrease in the transconductance.

-The voltage applied to the gate results in a vertical electric field, which reduces the mobility of the carriers in the channel (and therefore the transconductance). The exact value of the carrier mobility depends on the gate overdrive and, of course, on the doping in the channel region

-Maximum operation frequency: it depends on the transconductance and on the gate-to-source capacitance. It can also be expressed as a function of gate overdrive and gate length L. As it can be seen, the dependency on length is quite strong (square): as long as the device stays in strong inversion and does not enter velocity saturation (see later), there is a gain in speed going to more advanced processes (shorter L).


Equations: velocity saturation

Lv

21

Cg

21

f sat

gs

m.S.Vmax_ π

=π

=

scm

10v with)V(VvWCI 7satTGSsatoxDS_V.S. =−=

satox.S.V_m vWCg =

For low values of the longitudinal electric field, the velocity of the carriers increases proportionally to the electric field (and the

proportionality constant is the mobility). For high values of the longitudinal electric field (3 V/μm for electrons and 10 V/μm for holes)

the velocity of the carriers saturates.

The saturation of the carrier velocity is a phenomenon which became more and more important in more advanced CMOS processes.

The equations valid in strong inversion do not hold anymore in velocity saturation.

Ids, for example, does not depend anymore on the square of the overdrive voltage but only on the overdrive voltage. Also, Ids does not depend on L anymore.

The transconductance loses the dependence on L and on Ids. This means that once in velocity saturation it is useless to increase Ids again: we would waste power and not gain anything.

The maximum frequency of operation is not depending on the gate overdrive anymore and has a weaker dependence on L.


gm / ID vs log(ID / W)

0

5

10

15

20

25

30

1E-11 1E-09 1E-07 1E-05 1E-03

ID / W

gm

/ I D

W.I.

M.I.

S.I. &

V.S.

Weak Inversion (W.I.)

t

DSm n

Ig

φ=

tD

m

n1

Ig

φ=

Strong Inversion (S.I.)

DSm In

2gβ=

DSD

m

I1

n2

Ig β=

Velocity Saturation (V.S.)

satoxm vWCg =DS

satox

DS

m

IvWC

Ig =

Moderate Inversion (M.I.): No Simple Equations

An interesting plot can be obtained showing how the gm / Ids ratio varies with the current density (plot in a log scale). The gm / Ids ratio is an indication of the “power efficiency” of the device: it tells us how much transconductance I get for a given current (power) expense.

We can see that this ratio varies depending on the inversion region of the device: it is maximum in weak inversion, and then decreases going to moderate inversion, strong inversion and velocity saturation.

This is a quite useful information, especially for low power design: for a given device dimension, in weak inversion we get the maximum power efficiency. The absolute value of the transconductance is much smaller than what we can get for the same device in strong inversion, but the power efficiency is much higher. But, as always in analog design, there is a trade off here: for a given current, making the device larger pushes it towards weak inversion, increasing the gm but decreasing the speed at the same time (due to the increase in the size).

The gm / Ids ratio does not change with Ids in weak inversion, is proportional to the inverse of the square root of Ids in strong inversion and is proportional to the inverse of Ids in velocity saturation. These trends can be better seen plotting the curve with log scales for both axis, as it is done in the next slide.


0.1

1

10

100

1E-11 1E-10 1E-09 1E-08 1E-07 1E-06 1E-05 1E-04 1E-03

ID / W

gm

/ I D

Log(gm / ID) vs log(ID / W)

Slope = - 0.5Strong inversion

Slope = - 1Velocity saturation


The poor PMOS transistor

2TGSDS )VV(

n2I −β−=

DS

TGS

GS

DSm

In

2

)VV(n

V I

g

β−=

=−β−=

=∂∂

=

-3.0E-05

-2.5E-05

-2.0E-05

-1.5E-05

-1.0E-05

-5.0E-06

0.0E+00

-2.5 -2.0 -1.5 -1.0 -0.5 0.0

VDS [ V ]

I DS [

A ]

p+ p+ n+

n-well

SG

D well

GATE

DRAIN

SOURCE

WELL

VT < 0 V

VGS < 0 V

IDS < 0 V

-2.E-03

-1.E-03

-1.E-03

-1.E-03

-8.E-04

-6.E-04

-4.E-04

-2.E-04

0.E+00

-2.4 -2.0 -1.6 -1.2 -0.8 -0.4 0.0 0.4

VGS [ V ]

I DS [

A ]

Let’s do some justice to the poor PMOS transistor!

There is not much to say here, a part from the fact that almost everything is the same but opposite!

One important difference: the mobility of holes is smaller than the one of electrons. In pure silicon (which is not the case of a MOS transistor channel!!!) there is a factor 3 difference: 1417 cm^2/V*s for the electrons, 471 cm^2/V*s for the holes. These values are much smaller for the electrons and holes in a MOS transistor. The ratio between them depends on the technology, and can vary from 2 to 4 (roughly).

There are a few more subtle differences which we will not discuss here.

NOTE: usually schematics are designed in a way that node potentials rise going from the bottom to the top of the sheet. This is why I have drawn the source above the drain.


Small-signal equivalent circuit

gsmvg 0r

G

S

D

gsmds vgi ⋅=

)V1()VV( n2

I DS2

TGSDS λ+−β= This equation fixes the bias point

This equation defines the small signal behavior

Valid only in saturation and at

very low frequencies

No bulk effect

This slide illustrates the simplest small-signal equivalent circuit of a MOS transistor. Small signals are small variations of the bias currents and voltages.

In the equations in the slides, capital letters are used for bias quantities, and small letters for small signals.

This circuit shows that the transistor can be seen as a Voltage Controlled Current Source (VCCS) between drain and source. The control voltage is the gate-to-source small signal voltage. r0 is the output resistance of the transistor. It is in parallel to the VCCS and represents the non ideality of the current source.

At low frequencies the gate is completely isolated from all the other terminals of the device.

In the slide we have taken the equation for the bias current in strong inversion. In other inversion regions the correct equations have to be taken.

The equation which defines the small signal behavior is valid no matter which inversion region we are in: it is just the value of the transconductance which will have to be calculated accordingly with the equations we have already seen. From the small signal equation we can see that the transistor can be seen as a voltage-to-current amplifier: modulating the gate-to-source voltage with a small signal, we obtain a modulation of the drain-to-source current. The transconductance is the gain of the amplifier.


A very simple amplifier

VGS

VDS

VDD

RD

D

DSDDDS R

VVi

−=

For a small signal:

vds = -vgs*gm*RD

K. R. Laker and W. M. C. Sansen, Design of Analog Integrated Circuits and Systems, McGraw-Hill, 1994.

Here we see a simple voltage-to-voltage amplifier. A small signal on the gate is converted through the transconductance into a signal current. The resistor RD converts this signal current into a signal voltage at the output.

The plot illustrates well that the transistor is biased in the bias point Q, and that the small signal is a variation of this bias situation. The voltage at the output can be found on these plots as the intercept between the transistor and the resistor characteristics.

Here we did not consider the bulk effect, as we assumed the bulk and the source shorted.

Also, as it can be seen in the Ids vs Vds characteristics, we assumed the output conductance of the transistor to be zero (output resistance infinite). In fact this is never the case: the gain of the amplifier is therefore not gm*RD but gm*(r0//RD), where r0 is the output resistance of the transistor and // means the parallel of the two resistors: this means that the maximum (theoretical) gain of a single transistor MOS amplifier is given by gm*r0 (and this quantity is called intrinsic gain). This tells us how important the output resistance is!


A better equivalent circuit

gsmvg bsmbvg 0r

sbC

gsC

dbCgbC

gdC

G

S

D

B And we should also add the series resistances…

This is a much better small signal equivalent circuit of a MOS transistor in saturation.

First of all we note that when source and bulk are not shorted, there is another Voltage Controlled Current Source (VCCS) between source and drain, controlled by the source-to-bulk small signal voltage, in parallel to the VCCS controlled by the gate-to-source voltage.

Then we see that we have capacitances connecting all the nodes between each other. The two most important are Cgs and Cgd, as they make a path for the signal between the gate and the source and drain. This has a very important impact on the frequency behavior of CMOS circuits.


The First Transistor

First Point Contact Transistor

Bardeen and Brattain, 1947Bell Laboratories

The first point contact transistor was created by Bardeen and Brattain in December 1947.

The junction transistor was invented by Shockley in July 1951.

William Shockley, John Bardeen and Walter Brattain won the Nobel price in Physics in 1956, “for their researches on semiconductors and their discovery of the transistor effect”.

Bardeen won it again in 1972, together with Leon Cooper and John Schrieffer “for their jointly developed theory of superconductivity, usually called the BCS-theory” .

Shockley joined Beckman Instruments in 1955, where he was appointed as the Director of the Shockley Semiconductor Laboratory division.

In late 1957 eight of his researchers left and started Fairchild Semiconductor. This moment is often considered as the birth of Silicon Valley. Among these researchers there were Robert Noyce and Gordon E. Moore, who will then leave Fairchild to create Intel. Other offspring companies of Fairchild were National Semiconductor and Advanced Micro Devices.


The Bipolar Junction Transistor (BJT)

Emitter Base Collector

N P N

C

E

B

In normal operation condition (also called normal active region) the Emitter – Base diode

is forward biased and the Base – Collector diode is reverse biased. Electrons are injected

from the Emitter into the Base. They diffuse then towards the Collector, where they are

collected.

At the same time holes are injected from the base into the emitter, but in a much smaller

number since the base is normally much less doped than the emitter.

A fraction of the electrons injected into the base will not reach the collector because it will recombine with holes in the base. To make this a negligible effect the electrons lifetime must be

long so that their diffusion length is much larger than the base width.

A bipolar transistor consists basically of two diodes connected back to back. The central terminal is in common between the two diodes (it is the same piece of silicon!) and must be very narrow for the transistor to work (this will be clearer later).

A basic explanation of the working principle of the transistor is given in the slide.

Note that a bipolar transistor is a minority carrier device, as the working mechanisms is determined by electrons in the p doped base.

In the slide we discuss the case of an npn transistor. Pnp transistors also exist, they are similar to npntransistors but with the dopings and the applied voltages changed.

The symbol of a npn transistor is shown in the slide. The arrow on the emitter indicates the direction in which the current flows.


Currents in a bipolar transistor

InE

IpE

Irg

InC

InE - InC

InCO

IpCO

Electron flux Hole flux

IB

IE IC

InE: electron current injected into the baseInC: electron current collected by the collectorIrg: emitter space-charge-layer recombination currentInCO and IpCO: collector reverse saturation currents (InCO + IpCO = ICO)

-IE=IpE+InE+Irg

IB=IpE+Irg+(InE -InC)-ICO

IC=InC+ICO

IE+IB+IC=0

E. S. Yang, Microelectronic Devices, McGraw-Hill, 1988.

Here we see all the current components flowing in a bipolar transistor. InE is the electron current injected from the Emitter into the Base. Some of the electrons recombine with holes in the base, but the majority of them (InC) gets to the collector. For this to happen efficiently the base must be narrow enough. InE - InCrepresents one component of the hole base current. The other components of the (unwanted) base current are the holes injected from the base into the emitter and the recombination current in the emitter space charge layer.

The equations of the TOTAL base, emitter and collector currents are shown on the slide.


Currents in a bipolar transistor

IB

IE

ICVCE

VBE

Common base current gain TrgpEnE

nC

E

COC

IIII

I-I-I β⋅γ=

++==α

Emitter injection efficiencyrgpEnE

nE

IIII

++=γ

Base transport factornE

nCT I

I=β

γ, βT and therefore α are normally very close to 1 (but not 1)

CEOBFECO

BC IIh1-I

I1-

I +⋅=α

+⋅α

α=hFE is the common emitter current

gain (sometimes also called β).If α is 0.99 hFE is 99!

The emitter injection efficiency gamma specifies the portion of minority carriers injected into the base. Only these carriers may be collected by the collector junction to become a useful output current. The other components (IpE and Irg ) should be reduced as much as possible. The space-charge recombination current Irgis determined by the quality of the starting wafer, and is normally quite small. IpE is determined mainly by the dopings.

The carriers injected into the base will traverse it by diffusion, and some of them will recombine. The base transport factor tells us how many will survive. This is determined by the carrier lifetime and by the base width. The carrier lifetime (and so the diffusion length) must be much larger than the base width.

The common base current gain is given by the product of the emitter injection efficiency and of the base transport factor, and it tells us how much of the input current gets to the output.

The common emitter current gain tells us how much current is flowing in the base for a given collector current. This is a very important difference from the MOS, in which we had no gate current.


Current vs voltage equations

t

BEV

BaB

2i

nEBnE eWN

nDqAI φ=

t

BEV

EdE

2i

pEBpE eWN

nDqAI φ= EdEn

BaBp

WND

WND1

1

+=γ

2n

2B

T 2LW

1-=β nnn DL τ=

t

BEV

rg eI φ∝ 2 t

BE

nV

B eI φ∝

t

BEV

n

poBEBnCnEnB e

2

nWqAIII φ

τ=−=

AEB: E-B junction area

D: diffusion constant (=μφt)ni: intrinsic carrier conc.N: dopant concentrationW: E or B widthφt: thermal voltage

npo: equilibrium electron density in the base (=ni2/NaB)

τn: electron lifetime in the baseLn: diffusion lengthn: number between 1 and 2

The electron current injected into the base depends on the emitter-base area, on the inverse of the base doping concentration and exponentially on the base-to-emitter voltage.

This exponential behavior is one of the MOST important and useful and well known characteristic of a bipolar transistor.

The emitter injection efficiency gamma is determined mainly by the ratio between emitter and base doping (as the emitter and the base widths and diffusion constants are similar). To have gamma close to one the emitter must be doped much more than the base.

As already mentioned, the base transport factor is optimized through the carrier lifetime and the base width.

The total base current (which includes the emitter-base space charge layer recombination current) depends on the exponential of VBE/(n*phi), where n is a number between 1 and 2 and phi is the thermal voltage. This change in the slope can be noticed plotting the log of the current as a function of the base-emitter voltage (see next slide).


Bipolar transistor characteristics

E. S. Yang, Microelectronic Devices, McGraw-Hill, 1988.

VCE [ V ]

I C[

mA

]

VBE [ V ]I [

A ]

IBIC

t

BE

nV

e φ

t

BEV

e φ

hFE

The left plot shows the collector current as a function of the collector – emitter voltage for a bipolar transistor with the emitter grounded (common emitter).

In the cutoff region both emitter and collector junctions are reverse-biased. The normal active region is when the emitter junction is forward-biased and the collector junction is reverse-biased.

In the saturation region (which has nothing to do with the saturation region of a MOS transistor!!!) both junctions are forward-biased.

A bipolar transistor is used as an amplifier in the normal active region.

The maximum power dissipation allowed to the transistor is also shown. The transistor should not be operated beyond this curve due to overheating.

As we can see in this plot, a bipolar transistor is also, like a MOS transistor, a non ideal Voltage Controlled Current Source (VCCS). The non ideality comes from the modulation of the base-collector space charge region width with the collector-emitter voltage.

In the right plot we find the base and collector currents (in log scale) as a function of the base-emitter voltage. We can see the importance of the space-charge recombination current at low base currents (change in theslope). Note also how the collector current depends EXPONENTIALLY on the VBE for many decades of current.


A “few” important equations

t

C

BE

Cm

IVI

gφ

=∂∂=

m

FE

B

BE

gh

IV

r =∂

∂=π

2B

nT W

2D=ω

Transconductance

Collector current t

BEV

SnEC eIII φ=≈BaB

2i

nEBS WNn

DqAI =

K 300 @ 38.5 1

Ig

tC

m ≈=φ

Input resistance

Output resistance

Max frequency

jC

BaBBCE C

WNqAV =

T

m

n

2B

mBE

BD

g2DW

gVQ

Cω

==∂∂=Diffusion capacitance

C

E

C

CE0 I

VI

Vr =

∂∂=

Here is the list of the important equations for bipolar transistors.

The key issues to be retained are:

•The collector current varies exponentially with the base-emitter voltage.

•The transconductance is linearly proportional to the collector current, and the transconductance to current ratio is equal to almost 40 at room temperature

•The input resistance is given by the inverse of the transconductance multiplied by the common emitter current gain.

•The output resistance is given by a voltage called Early Voltage divided by the collector current. The active region part of all the output characteristics (IC vs VCE) projected towards the left would cross the VCE axis on the same point. The absolute value of this voltage is the Early voltage.

•The speed of the device is proportional to the inverse of the square of the base width

•A variation in the base-emitter voltage causes a variation in the injected charge QB. This represents a capacitance, called diffusion capacitance.


Small-signal equivalent circuit

K. R. Laker and W. M. C. Sansen, Design of Analog Integrated Circuits and Systems, McGraw-Hill, 1994.

bemvgjEC

)μ(C CjCBr

DC πr 0r CSC

E

B C

SUBπC

bev

The hybrid-π model

rB is the base resistance, which is layout dependent

In this slide we present the small signal equivalent circuit of a bipolar transistor in the active region.

As already mentioned, we have a non ideal voltage controlled current source. The output resistance r0represents the non ideality.

Another important resistor is the base-emitter resistor rπ, which is the input resistance of the transistor for a signal.

rB is the base resistance. It is a physical resistor which depends on the actual transistor layout.

CjC and CjE are two capacitances associated with the junctions, and CD is the already discussed diffusion capacitance.

The diffusion capacitance is proportional to the transistor current, and in normal operation is bigger than the junction capacitance.


Comparison MOS - Bipolar

Higher for MOS than for bipolar transistors1/f noise

4kT (0.5/gm + rB)4kT (0.7/gm + RG)Thermal Noise

vsat / WBvsat / LeffMax fT @ high I

gm / CDgm / CgsMax fT @ low I

> 5 decades~ 2 decadesI range

φtW / LDesign parameters

v.s. - WCOXvsat / IDS = 1 / (VGS-VT)

s.i. - 2 / (VGS-VT) = 1 / φt

w.i. - 1 / nφt

gm / I

few φt(VGS-VT) / nVDSsat / VCEactive

rπ + rB∞RIN

IC / hFE0IIN

Bipolar TransistorMOS Transistor

)DS/(nI2β

Here we have an interesting comparison between MOS and bipolars. The most noticeable differences are:

•The input resistance of a bipolar is much smaller than the one of a MOS.

•The saturation voltage of a bipolar does not depend on the transistor size, as it is the case for a MOS. Also, the saturation voltage is normally smaller for a bipolar.

•A bipolar transistor is always more power efficient than a MOS.

•A MOS transistor has more design parameters to play with (not necessarily an advantage!). In a bipolar transconductance and current are linked only by the thermal voltage (which is fixed). In a MOS we have the transistor sizes, which have to be determined by the designer.

•A bipolar transistor has a “reliable” exponential characteristic over many decades of current. A MOS transistor is in strong inversion for only a few decades, and this range becomes smaller and smaller in newer technologies.

•At low currents a MOS can be faster, as Cgs can be made smaller than CD (making the transistor small). At high currents a bipolar is normally faster (but MOS are catching up!)

•Noise: the thermal noise is comparable in the two transistors. The 1/f noise is higher for MOS.


Outline


• Sub-micron CMOS and BiCMOS technologiesCMOS technologyIntegrated Bipolar TransistorsTechnology price comparison

• Feature size scaling• Radiation effects and reliability• Mixed-signal circuits

In this section we will see a few details on the technologies in which MOS and Bipolar transistors are fabricated.


Complementary MOS technology

n+ n+p+ p+ p+ n+

n-well

SG

D SG

Dsub well

p-substrate

NMOS PMOS

PolysiliconOxideElectronsHoles

NMOS layout

n+ sourceG

n+ drain

Gate length

Gate width

This slide shows a (very simplified) representation of a NMOS and a PMOS transistors in a (p-substrate) CMOS technology.

CMOS stands for Complementary MOS

This is a simplified representation because many things are missing: Epitaxial layers, double wells, retrograde wells, …..

The simplified layout of an NMOS is also shown: with one mask we define the active area (S/D diffusions). The polysilicon gate shields the silicon from the S/D implant (self-aligned processes).

To keep the source, drain and gate resistances low, these regions are covered with metals (for example, Ti, Ta, or Co), which react with silicon and form a “disilicide”. This process is referred to as a self aligned silicide (or salicide) process.


Why is CMOS logic so attractive?

THE INVERTER

GND (Logic 0)

VDD (Logic 1)

VOUTVIN

GND (Logic 0)

VDD (Logic 1)

VOUTVIN

Truth table

IN OUT

01

10

To better understand the beauty of CMOS, let’s see how a CMOS inverter (the simplest logic gate) works. I hope I do not offend anybody…

It is made by an NMOS and a PMOS transistors connected as in the picture: common gates (input), common drains (output), source of the NMOS to GND (logic 0) and source of the PMOS to VDD (logic 1).

When the input is at 0, the NMOS is off. The PMOS has the channel formed, and therefore the output is at 1 (as the channel connects it to VDD).

Vice versa for the input at 1.

The two transistors can therefore be seen as two switches.

Since one of the two switches is always open (off, open circuit) with the input at 0 or 1, there is no current flowing in these two conditions. So, when CMOS logic is not doing something, it is not dissipating any power! This is one of the most important advantages of CMOS!!

There will be a current flowing only when the gate is switching, as at a certain moment the two transistors will be on at the same time. This can be seen in the following slide. Most current is used to charge and discharge the capacitive load represented by the following stages and interconnects.


Dynamic current in an inverter

Simulation of a chain of two inverters in a 0.25 μm CMOS technology

VinVout, Iout

-800-600-400

-2000

200400

600800

0 1 2 3 4 5 6 7 8 9 10Time [ ns ]

Iou

t [μ

A ]

0

0.5

1

1.5

2

2.5

0 1 2 3 4 5 6 7 8 9 10

Time [ ns ]

Vin

, Vo

ut [

V ]

VinVout

Here we simulate a chain of two inverters: the second inverter is there just to load the first one. We can see here that the dynamic current which we have while the transistors are switching can be quite large, but it is normally very fast. For example, in a 0.13 um technology the propagation delay of an inverter with fanout=1 (loaded with another inverter) and no interconnection parasitics is ~25ps.


Integrated Bipolar Transistors

C

E

BNPN

n+

p

n

n+

p (substrate)

n

EB C

ppVertical NPN

p-type pockets to isolate devices one from another

This is a fairly reasonable representation of a modern integrated bipolar transistor in a p-substrate CMOS technology. A better one will be shown later. It is called vertical NPN because the current is flowing in a direction perpendicular the the wafer surface. Practically all high-speed bipolar transistors are made this way.

The n+ region underneath the collector is called subcollector, and is used to make an electrical contact to the collector at the surface.

Starting from a p-type silicon wafer, the subcollector is formed by ion implantation and diffusion. The n-type collector is then formed by epitaxial growth. The p-type base is then ion implanted in the epitaxial layer. The n+ emitter is finally made by ion implantation and diffusion or by depositing a heavily doped n-type polysilicon layer on top of the base region.

Transistors are isolated from one another by p-type pockets or by oxide-filled trenches.


Integrated Bipolar Transistors

E

C

BPNP

p

n

p (substrate)

EB C

pp

n+

p

n

p (substrate)

CB

pp

n+ p

E

p

C

Vertical PNP (Common collector!)

Lateral PNP

Vertical PNP are also called substrate PNP, as the substrate acts as collector. All the vertical PNPs have therefore the same collector: this is an important limitation when we use them in circuit design. The epitaxial n region which is normally used as collector for a vertical npn is here the base, which is contacted by a n+ diffusion (the emitter in a npn transistor). The emitter is realized with the same diffusion which is used for the base of a vertical npn.

The lateral pnp uses again the epitaxial layer n as base. Emitter and collector are p diffusion (the base of a vertical npn).

The dopings of all these regions are optimized for npn transistors. Therefore, the performance of pnptransistors fabricated as just explained is quite poor.

Technologies with good performance npn and pnp transistors exists, but they are normally quite expensive and/or might not be easily accessible. In these technologies vertical PNPs are normally not substrate PNPs, as the collector is a separate terminal (they are built differently).


A modern npn BJT

Y. Taur and T.H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 1998.

Deep-trench-isolated, double-polysilicon, self-aligned bipolar technology

This is an example of a modern npn bipolar transistor. The important features to be noticed are:

•Deep-trench isolation between transistors: this results in a much higher density. The area of a diffusion isolated bipolar transistor is completely dominated by the isolation. Trenches can be made much smaller than diffusions (which are normally as wide as deep).

•Polysilicon emitter

•Self-aligned polysilicon base contact


Main innovations in modern BJTs

• Deep trench isolations: reduce significantly the device horizontal dimensions. p-type diffusions were normally used in the past, but they are as wide as they are deep

• Polysilicon emitter: compared to a diffused emitter, it gives smaller emitter junction depth and has a lower thermal cycle

• Self-aligned polysilicon base contact: reduces dimensions and allows thin-base transistors to be made more easily

• SiGe graded-base-bandgap transistors (also referred to as Heterojunction Bipolar Transistors – HBTs): Germanium is incorporated into the base region of a standard Si bipolar transistor. This is normally done with the ultrahigh-vacuum chemical vapor deposition epitaxial growth technique. The many advantages are discussed in the next slides


SiGe bipolar transistors

The bandgap of Germanium (0.66 eV) is smaller than that of Silicon(1.22 eV). Incorporating Ge into the base region of a Si bipolar transistor modifies the bandgap in the base region. Ge concentration is normally higher closer to the collector, so that an electric field is created in the base which helps the electrons drifting from Emitter to Collector. This has an important impact on the collector current and does not change

the base current.

EC

EV

EC

EV

EmitterBase

Collectorn+ Si

n Si

p Si or SiGe

Without Ge

With Ge

A 100 meV change of the bandgap across a base width of 100 nm gives a 10 kV/cm field


SiGe bipolar transistors

The effects of base-bandgap grading obtained by the inclusion of Ge in the base are all beneficial:

• The collector current increases while the base current does not change the current gain increases (x4)

• The Early voltage increases (x12)

• The base transit time decreases (x2.5), and therefore the speed increases

(The factors in parenthesis refer to a total base bandgap narrowing of 100 meV)


Why is CMOS so widespread?

• The IC market is driven by digital circuits (memories, microprocessors, …)

• Bipolar logic and NMOS - only logic had a too high power consumption per gate

• Progress in the manufacturing technology made CMOS technologies a reality

• Modern CMOS technologies offer excellent performance (especially for digital): high speed, low power consumption, VLSI, relatively low cost, high yield

CMOS technologies occupies the biggest portion of the IC market

BiCMOS technologies offer, in addition, high performance npn bipolar transistors, but are more expensive

Bipolar logic circuits have a too large power consumption per logic gate. This puts an upper limit on the numbers of gates that can be reliably integrated on a single die.

Despite the fact that the MOSFET original principle came in 1925 (and the first patent in 1930), manufacturing MOSFETs reliably came only after a few decades.

MOS digital integrated circuits took off in 1970. In the late 1970s NMOS-only logic circuits were limited again (as with the bipolar before) by power consumption.

The enormous progresses in technology manufacturing made CMOS a reality.

Before about 1977 practically all analog circuits were done with bipolars, and MOS where used for memories and digital circuits. After that date many people started to do everything in CMOS.


How much does all this cost?

Price for50 mm2 [k$]



Number of Metal Levels

TechnologyVendor

150 - 45575 – 227.530 - 9140.25 μm SiGe BiCMOSIHP

32.416.250.25 μm CMOSUMC

60.830.460.18 μm CMOSUMC

110.855.4Min price

given for

25 mm2

80.13 μm CMOSUMC

EUROPRACTICE

77.247.22150.25 μm CMOSIBM

144895670.18 μm SiGe BiCMOSIBM

126.8703660.18 μm CMOS MixModeIBM

825412.516570.13 μm SiGe BiCMOSIBM

250.1135.157.580.13 μm CMOS MixModeIBM

MOSIS

These prices have been taken from the web, and are intended for prototyping. Prices taken without discounts.

UMC: dimensions should be multiple of 5 mm. For example, a 6 mm by 6 mm chip would cost, in 0.13 um, 55.4K * 4!!!


SOI CMOS from IBM


Metallization examples (IBM)


Outline


• Sub-micron CMOS and BiCMOS technologies• Feature size scaling

A bit of historyA look into the futureCMOS scaling: how does it work?Scaling of Bipolar TransistorsScaling impact on CMOS analog circuits

• Radiation effects and reliability• Mixed-signal circuits

Transistors became and are becoming smaller and smaller and smaller…

In this section we will understand why and we will explain how scaling works and what is its impact on integrated circuits performance (mainly CMOS).


The first IC

First integrated circuit

Jack S. Kilby, 1958Texas Instruments

The first IC had 5 components (transistors, resistor and cap)


Moore’s law

1965: Number of Integrated Circuit components will double every yearG. E. Moore, “Cramming More Components onto Integrated Circuits”, Electronics, vol. 38, no. 8, 1965.

1975: Number of Integrated Circuit components will double every 18 monthsG. E. Moore, “Progress in Digital Integrated Electronics”, Technical Digest of the IEEE IEDM 1975.

The definition of “Moore’s Law” has come to refer to almost anything related to the semiconductor industry that when plotted on semi-log paper approximates a straight line. I don’t want to do anything to restrict this definition. - G. E. Moore, 8/7/1996P. K. Bondyopadhyay, “Moore’s Law Governs the Silicon Revolution”, Proc. of the IEEE, vol. 86, no. 1, Jan. 1998, pp. 78-81.

1996:

http://www.intel.com/

An example:Intel’s Microprocessors

In April 1965 Moore was director of research at Fairchild Semiconductor (created in 1957).

Intel was created in 1968. Moore was one of the co-founders.

Examples of the broad definition of Moore’s law (1996) are, for example, Intel’s net revenue and Intel’s investment in R&D.


The Intel Microprocessors

http://www.intel.com/

400411 / 1971

230010 μm

108 KHz

800804 / 1972

350010 μm

200 KHz

808004 / 1974

45006 μm

2 MHz

808806 / 1979

290003 μm

8 MHz

8028602 / 19821340001.5 μm12 MHz

Intel386TM

10 / 19852750001 μm

16 MHz

Intel486TM DX04 / 1989

1.2 M1 μm

25 MHz

Pentium®03 / 1993

3.1 M0.8 μm66 MHz

Pentium® Pro11 / 1995

5.5 M0.6 μm

150 MHz

Pentium® II05 / 1997

7.5 M0.35 μm233 MHz

Pentium® III02 / 1999

9.5 M0.25 μm500 MHz

Pentium® 411 / 2000

42 M0.18 μm1.5 GHz

For each microprocessor picture, we have indicated the name (blue), the date of introduction (red), the number of transistors (light blue), the minimum feature size of the technology used (green) and the clock speed (pink).


The Roadmap History

• The National Technology Roadmap for Semiconductors (NTRS):

Sponsored by the Semiconductor Industry Association (SIA)

Edited in 1992, 1994 and 1997

• The International Technology Roadmap for Semiconductors (ITRS):

Sponsored by:

• Semiconductor Industry Association

• European Semiconductor Industry Association

• Korea Semiconductor Industry Association

• Japan Electronics and Information Technology Industries Association

• Taiwan Semiconductor Industry Association

Edited in 1998 (Update), 1999, 2000 (Update), 2001, 2002 (Update), 2003,2004 (Update), 2005

These documents always contained a 15-year outlook of the semiconductor industry major trends


Future perspectives

Data taken from the International Technology Roadmap for Semiconductors (2004 Update)

Tra

nsi

sto

rs p

er c

hip

[B

illio

n]

Min

imu

m S

up

ply

Vo

ltag

e [V

]

On

Ch

ip C

lock

[G

Hz]

Ph

ysic

al G

ate

Len

gth

[n

m]

0

5

10

15

20

25

30

35

40

45

50

55

2003 2006 2009 2012 2015 20180.1

1

10

Year

Note here that the right scale is log.

Physical gate length and on chip clock refer to the left scale, transistors per chip and minimum supply voltage to the right scale.

The density doubles every 3 years.

Transistors per chip: data taken for high volume microprocessors at production.


Why CMOS scaling?

Pstatic = Ileakage · VDD

Pdynamic = CL ·VDD · f2

PDP = CL · VDD2

Power-delay product

Example: CMOS inverter

GND

VDD

GND

CL

VOUTVIN

CL VDDtox

Scaling improves density, speed and power consumption of CMOS digital circuits

The static power dissipation is given by the drain-source subthreshold leakage, the junction leakage (negligible) and by the leakage through the gate.

The dynamic power dissipation is given by the charging and discharging of the load capacitance, and it is frequency dependent.

With scaling we reduce the gate oxide thickness tox. This means that the power supply voltage has to be reduced as well (otherwise we risk breaking the oxide). Reducing tox increases the gate capacitance per unit area Cox, but the capacitance of a gate is nevertheless reduced as both W and L of each transistor are reduced.


Constant field scaling

B. Davari et al., “CMOS Scaling for High Performance and Low Power - The Next Ten Years”, Proc. of the IEEE, vol. 87, no. 4, Apr. 1999, pp. 659-667.

VqN2

x biA

Sid +φε=

The aim of scaling is to reduce the device dimensions (to improve the circuit performance) without introducing effects which could disturb

the good operation of the device.

α > 1

To scale the depletion region width xd the substrate doping NA has to be increased.

The constant field scaling is called like this because the electric fields in the device are kept constant, to avoid undesirable effects.


Constant field scaling

1/α3Transistor power-delay product1Power dissipation per unit of chip area

1/αTransistor transit time (τ)1/α2Power dissipation for a given circuit

1/√αBody effect coefficient (γ)1/αBias currents

1Electric field intensity1/αBias voltages and VT

1Charges per unit areaαDoping concentration (NA)

1/α2Chargesα2Devices per unit of chip area (density)

αCapacitances per unit area1/α2Area

1/αCapacitances1/αDevice dimensions (L, W, tox, xD)

Scaling factor

QuantityScaling Factor

Quantity

Summary of the scaling factors for several quantities

α > 1ox

SiOox t

C 2ε

=


Constant field scaling problem

Subthreshold slope and width of the moderate inversion region do not scale. This can have a devastating impact on

the static power consumption of a digital circuit.

VGS

log ID

0 V

pA

nA

VT

The problem of constant field scaling is that the width of the moderate inversion region and the subthreshold slope do not change.

With scaling, the power supply voltage is reduced, and so the threshold voltage of the transistors. This means that with constant field scaling the leakage current of the transistors increases.

For digital circuits with millions of gates this can be a big problem.

This issue has caused the departure from the classical constant field scaling (see next slide).

Another important remark is that in modern CMOS technologies very often we find different kind of devices with different threshold voltage values. Lower threshold voltages (high performance devices) give higher speed but also higher power consumption. Higher threshold voltages (Low Power devices) are used when power is an issue. This has been done to give more flexibility to designers and to partially solve the problem given by the fact that with ANY kind of scaling the threshold voltages tend to become smaller and the leakage currents tend to increase.


Generalized scaling

Y. Taur et al., “CMOS Scaling into the Nanometer Regime”, Proc. of the IEEE, vol. 85, no. 4, Apr. 1997, pp. 486-504.Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 1998, p. 186.

• The dimensions in the device scale as in the constant field scaling

• Vdd scales to have reasonable electric fields in the device, but slower than tox, to have an useful voltage swing for the signals

• The doping levels are adjusted to have the correct depletion region widths

• To limit the subthreshold currents, VTscales more slowly than Vdd

Let’s review a few of the already mentioned issues: the aim of scaling is to reduce the device dimensions (to improve the circuits performance) without introducing effects which can disturb the good operation of the device.

Constant field scaling does this keeping the electric field in the device constant. The problem is that the subthreshold slope and the width of the moderate inversion region do not scale. Due to the problem mentioned before, several other scaling approaches have been proposed.

One is the constant voltage scaling. This approach has been proposed to make the compatibility between different logic families easier. The power supply voltage is not scaled and the oxide thickness is scaled less drastically to avoid too large electric fields in the oxide.

The constant voltage scaling still has several inconveniences, the major being that the electric field in the thin gate oxide increases too much. To overcome them, the generalized scaling has been proposed.

With the generalized scaling the voltages are scaled but not at the same rate as the oxide thickness. This allows having acceptable electric fields in the device and at the same time a useful voltage swing for the signals. Also, the threshold voltage scales less abruptly than tox and also than Vdd, to limit the subthreshold currents.


Scaling of interconnectionsAn accurate scaling of the interconnections is needed as well, so that we can

profit at the circuit level of the improvements made at the device level. Interconnections are becoming more and more important in modern

technologies because the delay they introduce is becoming comparable with the switching time of the digital circuits.

Y. Taur et al., “CMOS Scaling into the Nanometer Regime”, Proceedings of the IEEE, vol. 85, no. 4, Apr. 1997, pp. 486-504.T. N. Theis, "The future of interconnection technology", IBM Journal of Research and Development, vol. 44, no. 3, May 2000, pp. 379-390.

Wires with

square section

The delay caused by interconnections was negligible in the early days of CMOS logic circuits. Now that circuits are bigger and logic gates are much faster, this is not true anymore, and interconnections can be the limiting factor of the speed of a digital circuit. The plot shows the delay of a wire with square section as a function of its length, for three different sections of the wire. From this plot we can see that:

-If the wire is not made big enough, a 1 mm long wire can easily cause delays above several tens of picoseconds

-For a given wire length, increasing the wire size can help up to a certain limit, as we hit the limit determined by the speed of an electro-magnetic wave

-For wires of the order of a few tens of microns the delay of the wire is not a problem as it can easily be kept below 1 ps.


“Reverse” scaling

G. A. Sai-Halasz, "Performance trends in high-end processors", Proceedings of the IEEE, vol. 83, no. 1, January 1995, pp. 20-36.

The scaling method is different from the one applied to devices

tm

Wtox

L

If W, L, tm and tox are decreased by α

• Current density increases by α

• R increases by α, C decreases by α

• RC (delay) does not scale!!!

In practice, wires dimensions are reduced only for local

interconnections (but not tm). At the chip scale, tm and tox are increased (reverse scaling).SUBSTRATE

To scale the wires, we could shrink everything by alpha (>1): the wire dimensions W and tm, the wire length L and the distance between different metal planes (oxide thickness) tox (not to be confused here with the gate oxide thickness of a MOS transistor). With scaling the currents are reduced by a factor alpha, but if we scale the wire section by alpha squared we increase the current density by alpha. An increase of the current density in the wire is normally very dangerous, as it can cause electromigration, which has a deadly impact on reliability (see also later). Also, if we shrink everything by alpha we reduce the capacitance of the wire by alpha but we increase its resistance by the same factor. This means that the delay of the wire (the RC delay) does not scale.

So, shrinking everything does not work.

In practice, different scaling rules apply to wires at different metallization levels.

For the metal levels closer to the transistors, where we need relatively short wires for local interconnection, we can shrink everything by alpha EXCEPT the wire thickness. This allows having narrow wires, which are needed to connect the smaller and smaller transistors, but at the same time we have that the current density does not change (good for reliability) and that the resistance does not change while the capacitance is reduced by alpha: we have then a faster wire (faster by a factor alpha). This of course as long as we do not have another wire close to it (the lateral C would dominate!)

At higher metal levels, we need even faster wires, as chips tend to become bigger. So for “global”interconnection not only we do not scale the thickness of the wires and of the oxide, but we might even want to increase it: this is why this is called “reverse” scaling.


Bipolar transistors scaling

Scaling has been much less emphasized for bipolar than for MOS transistors, but reducing the lateral and vertical

dimensions of a BJT has a beneficial impact on its performance.

Reducing the lateral dimensions increases the density and reduces the parasitic resistances and capacitances

( speed increases).

Reducing the vertical dimensions (in particular the base width / depth WB) increases the collector current density,

the current gain and the speed.

Scaling must be performed adjusting doping levels and bias voltages accordingly (breakdown voltages!).

I have only this slide on bipolar transistor scaling and its impact on the transistor performance. We will see the scaling of CMOS much more in detail.

I use here base width / depth because it depends on how we look at the device (vertical – horizontal). What I mean is that it is beneficial to reduce the path of the minority carriers in the device.

The breakdown voltage is the avalanche breakdown voltage of the reverse biased collector-base junction.


Scaling impact on CMOS analog ICs

tox scales for the same device dimensions

• Threshold voltage matching improves

• 1/f noise decreases

• Transconductance increases (same current)

• White noise decreases

W LtConst

σ oxΔVth

⋅=

DSoxm ILW

Cn2

g μ=

α=f1

WLCK

Δf

v2ox

a2

f/1_in

Here we have a summary of some of the important analog performance parameters which IMPROVE with scaling of CMOS technologies.

We assume here that we are moving to a more advanced process ( the gate oxide thickness tox scales) BUT we keep the same transistor dimensions. This is a choice that we always have in analog design.

•Threshold voltage matching: identically designed transistors will newer be exactly identical. There are a number of things which can be slightly different in the two devices. As an example, the number of dopantatoms in the channel will never be identical, as ion implantation is a statistical process. These differences in the devices give, for example, a difference in the threshold voltages. If we fabricate 100 transistor pairs and we measure the threshold voltage differences between the 2 transistors of each pair, we should normally find a gaussian distribution of these differences. The mean, if the designer has done his job properly, should be zero. A non zero mean means that there is a systematic effect, affecting all the time the same device in the pair. The sigma of the gaussian is what we call mismatch, and we can not eliminate it. The sigma of the distribution of the threshold voltage differences is given in the slide. We can see that bigger devices match better. We can also see that matching improves going to more advanced technologies (for the same device dimensions), as it is proportional to tox.

•The input referred 1/f noise formula is given in the slide. Ka is a technology dependent parameter. To make a comparison between technologies is fundamental to know its value for each technology. Assuming that it does not change with scaling, we see that 1/f noise improves with scaling (for the same device dimensions), as Cox increases. Note that Cox is not always found squared in the formula (it depends on the textbook).

•Transconductance: for the same device dimensions and the same bias current, the transconductance increases as uCox increases.

•For the same reason, the input referred white noise (proportional to 1/gm) decreases with scaling. We assume here that we do not have phenomena which can cause noise in excess.


Scaling impact on CMOS analog ICs

• New noise mechanisms

• Modeling difficulties

• Lack of devices for analog design (not anymore an issue)

• Reduced signal swing (new architectures needed)

• Substrate noise in mixed-signal circuits

• Velocity saturation. Critical field: 3 V/μm for electrons,

10 V/μm for holes

satox.sat.vel_m vWCg =

Here we have a summary of some of the important analog performance parameters which DO NOT IMPROVE with scaling.

•With scaling we can have new noise mechanisms which can increase the 1/f noise parameter Ka or increase the white noise excess factor.

•Deep submicron transistors are difficult to model, especially for some analog parameters

•Especially in their early stages, deep submicron CMOS processes did not have devices which are used in analog design (high precision linear capacitors, resistors, …). CMOS processes were optimized, at the beginning, for memories and for digital circuits. Analog components were normally added later. This is practically not a problem anymore, as most CMOS processes have today a very large offer of devices.

•The power supply reduction with scaling imposes new circuit architectures (we can not stack too many transistors between VDD and GND)

•CMOS processes were used, at the beginning, mostly for digital circuits, as the analog performance of the transistors was much worse than the one of bipolar transistors. Scaling of CMOS technologies and the improvement in the transistor performance pushed towards system integration on chip using only CMOS processes. In modern CMOS technologies it is possible to integrate analog and digital blocks on the same substrate. This imposes to deal with the problem of noise propagating from the digital blocks to the sensitive analog blocks. This point will be addressed in more detail at the end of the presentation.

•The problem of velocity saturation (that we have already seen) becomes more and more important in scaled down devices.


From weak inversion to velocity saturation

μ= sat

.s.v_to_.i.s

vnL2V

LW

Coxμ=β

t.i.s_to_.i.w n2V φ=

DS.i.s_m In

2gβ=

t

DS.i.w_m n

Ig

φ=

satox.s.v_m vWCg =

2TGS.i.s_DS )VV(

n2I −β=

t

GS

nV

0D.i.w_DS eLW

II φ=

)VV(vWCI TGSsatox.s.v_DS −=

IDS

VGS

w.i.s.i.

v.s.

Weak inversion (w.i.)

Strong inversion (s.i.)

Velocity saturation (v.s.)

gm

VGS

w.i.

s.i.

v.s.

Vs.i._to_v.s. decreases with scaling!!!

This slide shows a resume of the Ids and gm formulae for week inversion, strong inversion and velocity saturation.

We have also calculated here the Vgs voltages which delimit the weak inversion to strong inversion transition and the strong inversion to velocity saturation transition.

We can see that the first does not change with scaling, whereas the second decreases. This means that the width of the strong inversion region becomes smaller, and that, as already mentioned, it is easier to end up working in velocity saturation (and we do not want to!).


Scaling impact on power, speed, SNR

Assuming constant field scaling and strong inversion:

1/α

α

α

1/α

1/α

Δt = Q/I

11/α1α1αα31/αα

1/α11α1/α21/αα11

1/α3/2α1/21/α11/α31/α2111/α

1/α1/21/α1/21/α11/α1α21/α1

1/α11/α21/α1/α21/αα1/α1/α

SNRwQCox*W*LPWRIDSβLW 2white_nv

m

2white_n g

1kTn4v γ=

2white_n

DDw

v

VSNR =

DDDS VIPWR ⋅=

To maintain the same SNR we do not gain in Power !!!

In this slide I made a little “game”: using the basic equations that we have seen and applying constant field scaling (all this is obviously a rough approximation) I have calculated how several quantities vary with scaling, for different choices of the W and L dimensions of the transistor. We refer here to analog circuits.

Each row in the table represents a different choice of W and L. We consider here only thermal noise, and the Signal-to-Noise ratio (SNR) is defined as VDD divided by the thermal noise.

A few interesting things to note:

•We always gain in power (except last line)

•We always loose in SNR (except again last line)

•Speed is linked to L only (not W): we gain in speed only decreasing L

•The last line in the table represents the case of constant power consumption, constant dynamic range in a thermal noise limited system. We see that to keep the SNR constant with scaling we have to increase W! We also see that we do not gain in power. In the literature we can find that, in the reality, things are even worse! To keep the same SNR with scaling we even have to burn more power at the certain point. There is a kind of optimum, which seems to be around 0.25 um technologies. All this is of course pretty much dependent on the circuit type.


Outline


• Sub-micron CMOS and BiCMOS technologies• Feature size scaling• Radiation effects and reliability

IntroductionTotal Ionizing Dose (TID) effectsDisplacement DamageSingle Event Effects (SEE)Solutions to the problems induced by radiation in CMOS technologiesReliability issues

• Mixed-signal circuits

This section is about:

•radiation effects on integrated circuits

•how to make radiation tolerant circuits in non rad hard CMOS technologies

•reliability

I will most likely NOT have the time to explain all this during the course, but I have put the slides anyway because I believe it is an interesting topic when talking about electronics for nuclear physics. I hope you will find the slides + the comments useful.

This is a quite complex topic, so some of the slides (like the first ones) are simplifying the matter a bit.


Interaction radiation-matter

The two most important phenomena to be considered are ionization and nuclear displacement.

Neutrons give origin mainly to nuclear displacement.

Photons give ionization.

Charged hadrons and heavy ions give both at the same time.

For ionization we talk about Total Ionizing Dose (TID), for nuclear displacement about Fluence

Note: It is obviously quite important to know the radiation environment in which our circuits will have to work (and survive): kind of particles, energies, fluences…


Interaction radiation - ICs

Cumulative Effects

Single Event Effects (SEE)

TID

Displacement

MOS

Bipolars

Bipolars

Optoelectronics

Non Catastrophic (SEU, SET)

Catastrophic (SEGR, SEL)

MOS, Bipolars

MOS

TID: total ionizing dose

Cumulative effects are gradual effects taking place during the whole lifetime of the electronics exposed in a radiation environment. A device sensitive to TID or displacement damage will exhibit failure in a radiation environment when the accumulated TID (or particle fluence) has reached its tolerance limits. It is therefore in principle possible to foresee when the failure will happen for a given, well known and characterized component.

On the contrary, Single Event Effects are due to the energy deposited by one single particle in the electronic device. Therefore, they can happen in any moment, and their probability is expressed in terms of cross-section. A device sensitive to SEE can exhibit failure at any moment since the beginning of its operation in a radiation environment.

From this slide we can see that MOS transistors are sensitive to TID and SEE but not to nuclear displacement.


Ionizing particles through a MOST

Threshold voltage shift

Threshold voltage shift

Mobility degradation

Swing degradation

Other degradations:• Transconductance• Noise• Matching

Problems due to ionization in the thin gate oxide

F. B. McLean and T. R. Oldham, Harry Diamond Laboratories Technical Report, No. HDL-TR-2129, September 1987.

Let’s now start to see the problems given by TID. We will see the SEE later.

We start with TID effects in a MOS. The slide shows the band diagram of a MOS structure under bias (positive bias applied to the gate with respect to the bulk).

When ionizing radiation goes through the MOS layers, it creates electron-hole pairs everywhere. In polysilicon (M) and in silicon (S) which are conductive (with lots of free carriers) the e-h pairs recombine immediately.

In the oxide (O) only a fraction of them recombines. Most of them are separated by the electric field. Electrons have a mobility in the oxide which is many orders of magnitude higher than the holes, and they leave immediately the oxide. Holes move more slowly (the transport phenomenon is called “polaronhopping”) through the oxide towards the Silicon Dioxide – Silicon interface. Some of the holes are trapped in the oxide (normally close to the interface where the trap density is higher). Some other holes gets to the interface where they create some new interface traps.

What is the electrical result of all this mess?

Holes trapped in the oxide move the threshold voltage: one way to understand this is to think that these holes will attract some electrons at the interface. This means that, for example in an NMOS, we need a smaller VGSto get the same channel, which means that the threshold voltage is smaller. As we always trap holes, the threshold voltage shift is negative in both NMOS and PMOS transistors.

The new traps created at the interface can also trap charges. Under normal bias conditions, they trap electrons in NMOS transistors and holes in PMOS. This means that the threshold voltage shift is positive in NMOS and negative in PMOS.

It is important to mention that the two processes:

•Hole trapping in the oxide

•Interface states creation

Have a very different temporal dynamic. The hole trapping is much faster, interface states come normally later. This means that, after irradiation, we can measure different threshold voltage shifts in time.

Since interface traps degrade the Silicon Dioxide – Silicon interface, they also degrade the mobility of the carries (and then the transconductance), the slope of the subthreshold region, the noise (especially 1/f) and the matching.


Transistor level leakage (NMOS)

Bird’s beak

Field oxide

Parasitic MOS

Trapped positive charge

Parasitic channel

Thin gate oxide

Problem due to ionization in the thick field (lateral) oxide

R. Gaillard, J.-L. Leray, O. Musseau et al., “Techniques de durcissement des composant, circuits, et systemes electroniques”, Notes of the Short Course of the 3rd European Conference on Radiation and its Effects on Components and Systems, Arcachon (France), Sept. 1995.

The problems we have explained in the previous slide refer to TID damage in the thin gate oxide of a MOS transistor. But in CMOS ICs there is plenty of oxide everywhere.

Oxide is also used to isolate devices between each other. At the edges of the channel, the thin gate oxide has to become thick isolation oxide. This used to be done with a process called LOCOS (LOCal Oxidation of Silicon), which gave to this region the characteristic shape of a bird’s beak. Below roughly 0.35 um, this process was substituted by another one called STI (Shallow Trench Isolation). In both cases, we have at the channel edges a region with a quite thick oxide. This oxide can trap quite a lot of holes during irradiation, which can then attract electrons just underneath. These electrons can form a parasitic path between source and drain. It is just like having two parasitic transistors in parallel to the main one, one on each side of the main transistor. This phenomenon is important only for NMOS transistor (as we always trap holes in the oxide).


BIRD’S BEAKS

GATE

Transistor level leakage (NMOS)

“CENTRAL”(MAIN) MOS

TRANSISTOR

log ID log ID

VGS VGS

To understand a bit better the effect of irradiation at the bird’s beaks, we can think at this region as if it was made up by many transistor is parallel, each one with a different gate oxide thickness. Being this thickness much larger than the one of the main transistor, the ID vs VGS characteristic of these transistors is much different: the threshold voltage is much higher and the saturation current is much smaller.

But with the irradiation the threshold voltage of these parasitic transistors can shift so much that their characteristics get overlapped to the one of the main transistor. Two possible examples are shown in the slide. This is a qualitative explanation of the shape of the characteristics that we can measure after irradiation.


Transistor level leakage: example

1.E-13

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

-1 -0.5 0 0.5 1 1.5 2 2.5 3 3.5

VG [V]

I D [

A]

Prerad

After 1 Mrad

NMOS - 0.7 μm technology - tox = 17 nm

Threshold voltage shiftμA!

This slide shows the measurement of a NMOS fabricated in a 0.7 um CMOS technology. We can see the IDSvs VGS characteristic before irradiation and after 1 Mrd. We can easily notice the negative threshold voltage shift and the devastating impact of the leakage at the bird’s beaks. The leakage problem is an issue especially for digital circuits. For analog circuits with transistors working in strong inversion it has a smaller impact.


Field oxide leakage

INTERCONNECTION

N+ WELL CONTACT N+ SOURCE

FIELD OXIDE

N-WELL

P-SUBSTRATE

+ + + + + + + + + + + + +++

+

VDD SSV

Radiation induced leakage

between VDDand VSS

Again problem due to ionization in the thick field (also called lateral or isolation) oxide

As already mentioned, in a CMOS IC we have thick oxide everywhere (wherever we do not have transistors). This oxide is called field oxide, and it can be charged by trapped holes. This induces leakage paths a bit everywhere!

The effect is lethal. Here we show an example in which we have leakage between an N-well (connected to VDD) and the source of a NMOS, connected to GND (VSS). The radiation induced leakage path creates a short between VDD and GND!

This can be easily verified experimentally: if we take a rad soft CMOS IC and we irradiate it monitoring at the same time the power supply current, we will see it rising sharply after a given dose (which is technology dependent).

The effect of radiation can be made even worse if there is an interconnection on top of the field oxide. This acts as a gate, making the effect of radiation even more pronounced (see next slide).


1.E-12

1.E-10

1.E-08

1.E-06

1.E-04

0 10 20 30 40

VGS [ V ]

ID [

A ]

n+ source

n+ drain

PRERAD AFTER 1 Mrad

Post-irradiation leakage currents depend on

Total Dose

Bias conditionsGate Material

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

-5 0 5 10 15 20VGS [ V ]

I D [

A ] Metal Gate

Polysilicon Gate

The Field Oxide Transistor

Field oxide quality

To better study the problems created in the field oxide, we have fabricated and measured some “field oxide transistors”. These transistors have as a gate oxide the thick field oxide used for isolation. As a gate one can use polysilicon or metal.

In the left plot wee see that these transistors behave exactly as standard transistors, but their threshold voltage is in the order of a few tens V.

After irradiation we immediately see that the leakage current (the current at VGS = 0) increases by many orders of magnitude.

We can also see that the case of a polysilicon gate is much worse than the one of a metal gate: this is because, for the same applied bias, the electric field in the oxide is higher when the gate is in polysilicon. A higher electric field is more efficient in avoiding recombination between the electrons and the holes created by irradiation.


TID damage in bipolar devices

Substrate, sidewall and surface inversion (in oxide-isolated processes)

R.L. Pease et al., IEEE Trans. Nucl. Science. Vol.32, N.6, 1985E.W. Enlow et al., IEEE Trans. Nucl. Science. Vol.36, N.6, 1989

The text for this slide is from Federico Faccio, CERN.

The TID effects in bipolar devices are also due to charge trapping in the oxide and creation of interface states. The effects can be divided in two categories:

1) inversion of the silicon under a thick oxide, opening a conductive channel

2) effects decreasing the gain of the transistor

The inversion channel can be formed in several places, depending on the technological characteristics:

a) Substrate: opening of the channel between two buried layers

b) Sidewall: inversion near the sidewall oxide, shorting collector and emitter of npn transistors

c) Surface: inversion of the surface. Even though the surface oxide is generally thinner than the isolation recess oxide, the effect might be important when the transistors are working at low current levels.



Gain degradation:Increase of the surface component of the base current

R. N. Nowlin et al., IEEE Trans. Nucl. Science. Vol. 39, N. 6, 1992

The text for this slide is from Federico Faccio, CERN

TID acts on the gain by increasing the surface component of the base current (the bulk component being mainly sensitive to displacement damage).

The increase in this surface current component is mainly due to an increase of interface states at the surface of the base and a positive charge buildup near the emitter-base junction (both increasing the minority carrier recombination rate).

Excess base current is in general the dominant effect, with the collector current being constant.

The sensitivity is higher at lower injection levels, as in this case there is more sensitivity to surface phenomena.



Factors affecting TID response of bipolar transistors

• Transistor polarity• Oxide thickness over base-emitter region• Oxide trap efficiency• Vertical and fringing electric field• Base and Emitter surface concentration• Emitter perimeter-to-area ratio• Transistor geometry (ratio of lateral to vertical current flow)• Injection level• Dose rate• Temperature

The text for this slide is from Federico Faccio, CERN

Oxide thickness: the thicker the oxide above emitter-base junction area, the grater the TID effects

Oxide trap efficiency: the more degraded the oxide (during manufacturing), the grater the TID effects

Electric field: difficult to have a clear picture of the electric fields, and to generalize to several technologies

Surface doping concentration: the more heavily doped the base or emitter surface, the lower the TID effects

Emitter perimeter-to-area ratio: the grater the ratio, the grater the TID effects

Transistor geometry: vertical structures have lower sensitivity to TID effects than surface lateral structures (or substrate PNP, where 20% of the current is lateral)

Injection levels: in almost all cases, degradation is higher at low injection


Displacement damage

Displacement increases the recombination of minority carriers in the silicon bulk.

MOS transistors are not sensitive to displacement damage, since they are majority carrier devices and the transistor

action takes place close to the SiO2-Si interface (not in the silicon bulk).

Bipolar transistors, on the other hand, are sensitive to displacement damage, since they are minority carrier devices and the transistor action takes place in the silicon bulk. The

increased recombination in the base increases the base current and reduces the gain.

Scaling of bipolar transistors helps reducing the sensitivity to displacement damage, since it reduces the transistor

active volume.

Up to now we have seen the total ionizing dose effects in MOS and Bipolars.

In this slide we briefly mention the displacement damage effects.


Single Event Latch-up (SEL)

Latch-up can be initiated by ionizing particles (SEL).

If the supply is not cut quickly enough, it can be destructive!

VDD

VSS

R1R2

R3R4

R5R6

n well

p substrate

VDDcontact

n +p + p +n +

VDDsource

VSSsource

VSScontact

R1 R2R4

R3

R5R6

Electrical latch-up in CMOS processes might be initiated by electrical transients on input / output lines, elevated T or improper sequencing of power supply biases. These modes are normally addressed by the

manufacturer.

We now see 3 Single Event Effects, which are very important for CMOS processes.

The first is the Single Event Latch-up (SEL).

In every CMOS process there is a parasitic structure called thyristor (shown in the slide). Electrical latch up in a CMOS process happens when this parasitic thyristor turns on, shorting VDD and GND. This can destroy the circuit if the power supply is not cut on time. Electrical latch up is something which is normally addressed by the manufacturer, which tries to reduce resistances R1 and R6 (which are responsible for turning on the device) and tries to reduce as much as possible the current gain (beta) of the two bipolar transistors making up the thyristor.

SEL is a Latch-up which can be initiated by ionizing particles, which can create electron hole pairs in strategic points of the IC and turn on the thyristor. As already mentioned, this can be a destructive effect.


Single Event Upset (SEU)

GND

VDD

GND

VDDStatic RAM cell

1

10

01 0

Highly energetic particle

Never destructive, always (very) annoying.

Fighting SEU in a chip is a matter of risk management!

We explain now the Single Event Upset (SEU), illustrating it in the case of a Static RAM cell.

A highly ionizing particle can deposit enough energy to produce a “soft error”. A SEU occurs if the charge deposited on the critical node where the information (represented by a charge) is stored is higher than a minimum charge quantity, called critical charge. To produce a SEU particles with a sufficiently high Linear Energy Transfer (LET) are therefore needed. The Linear Energy Transfer expresses the energy per unit length which the particle deposits in the material.

The SEU is NOT a destructive effect.

What is very important with SEU is to know well the radiation environment in which the IC has to work, to be able to estimate the SEU rate. We have then to decide if we can afford to have this rate of SEU in every block of the IC.

The third SEE (no slide for this one) is called Single Event Gate Rupture. It is a destructive effect, which is caused by an ionizing particle which crossing the gate of a transistor causes the rupture of the thin gate oxide (we do not enter here in the physics of this phenomenon).


TID damage and CMOS scaling

tox [nm]1 10 100

-ΔV

FB

/ 1M

rd (

Si)

[V

/rd

]

ΔV FB∝

t ox2

104 20 40 100tox [nm]

-ΔD

it/ M

rdN. S. Saks et al., IEEE TNS, vol. 31, no. 6, Dec. 1984, and vol. 33, no. 6, Dec. 1986.

MOS transistor gate oxide (thickness tox)

We now enter a new “chapter”: what is the effect of scaling on the radiation tolerance of CMOS processes?

Let’s start with the Total Ionizing Dose (TID) damage of the thin gate oxide.

Already more than 20 years ago it was understood that reducing the gate oxide thickness tox was improving the radiation tolerance of the gate oxide.

The two plots show the damage in the oxide (left) and at the interface (right) normalized to 1 Mrd dose as a function of the gate oxide thickness.

The y axis of the left plot represents the flat-band voltage shift with radiation (normalized to 1 Mrd dose), which is an indication of the amount of holes trapped in the oxide. The y axis of the right plot represents the increase of the interface state densities. The two series of points in this plot correspond to two different electric fields in the oxide during irradiation.

Let me remind you the typical gate oxide thicknesses of a few CMOS technologies:

•0.7 um technology: tox = 17 nm



•0.25 um technology: tox = 5.5 nm

•0.13 um technology: tox = 2.2 nm

As we can see from the two plots, we have a huge increase of the radiation tolerance with scaling. For oxide thicknesses below 10 nm this improvement becomes even larger.

We can therefore expect, from this slide, that the gate oxide of a deep submicron CMOS technology is inherently radiation hard! To be verified…


( )itNΔ⋅α+μ=μ

10

DD

T

T

TT V

V ,

VV

,VΔΔΔ

Decreasing tox we decrease the degradation of: Transconductance

Subthreshold slope

Noise

TID damage and CMOS scaling

So, decreasing the gate oxide thickness tox we reduce the following radiation induced degradations:

•Threshold voltage shift.

•The threshold voltage shift normalized to the absolute threshold voltage value or to VDD also decreases. This is important because with scaling VT and VDD decrease.

•The radiation induced mobility degradation, which is a function of the increase in the interface traps density, is also reduced with scaling.

•In general, all the radiation induced degradations linked to the thin gate oxide or to its interface with the silicon become smaller with scaling.


ΔVT and CMOS scaling

Measurements done in our group @ CERN: it is really true!!!

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1 10 100

tox (nm)

ΔV

th/M

rd(S

iO2)

[m

V/r

d(S

iO2)

]1.61.2

0.80.7

0.50.5 - A0.5 - B

0.350.25 - A0.25 - B

0.13 N0.13 P

tox^2Points taken after 100 Mrd

This is an interesting plot which shows several measurements done in the Microelectronics Group of CERN (only 4 points are taken from the literature: the 1.6, 1.2, 0.8 and one of the 0.5). What was shown already 20 years ago is really true!

All the points except the two for the 0.13 um technology were taken immediately after irradiation and after doses of the order of 100 krd. This was done to try to have only the component from the oxide traps (we remind here that the threshold voltage shift is given by two components: the one from the oxide and the one from the interface states. These components are both negative for a PMOS and have different signs for a NMOS. Also, the dynamic behavior of the creation of these two components is very different: the interface state component comes normally more slowly).

The two points for the 0.13 um technology need some comments: they were measured after 100 Mrd, which means that here we have the components from the oxide traps and from the interface states summed.

The reason why we have taken the values after 100 Mrd was to have a better measurement (at least for the PMOS), as the values are very small!

The point for the PMOS is probably higher than expected because of the interface states (whose contribution goes in the same direction as the contribution from the oxide traps).

The point for the NMOS is not so much representative, as after 100 Mrd the shift was only 1 mV and as we have the sum of the two components!

Anyway, the key message here is that even after doses of the order of several tens of Mrd we can expect, using a deep submicron CMOS technology, a threshold voltage shift of the order of a few mV or tens of mV.


SEL and scaling

• Retrograde wells• Thinner epitaxial layers• Trench isolation• VDD reduced

Modern CMOS technologies have:

All these issues help in preventing SEL,but they might not be always effective

VDD

VSS

R1R2

R3R4

R5R6

R1 and R6 reduced

A. H. Johnston, IEEE Transactions on Nuclear Science, vol. 43, no. 2, Apr. 1996, pp. 505-521.

Modern CMOS technologies became more and more tolerant to electrical latch-up (and therefore to Single Event Latch-up). This is linked to the introduction of several novelties in the process: retrograde wells (which are wells doped more heavily at the bottom than at the top), thinner epi layers, shallow trench isolation (STI). All this reduces resistances R1 and R6, making it more difficult for the parasitic thyristor to turn on. Also the fact that the power supply voltage VDD is reduced with scaling helps, as to turn the thyristor on and keep it on we need at least 1 V.

All this is very much technology dependent. What we can also say is that in general it is good to have as many substrate and well contacts as possible, because this in any technology helps preventing the SEL.


SEU and scaling

• VDD reduced

• Node C reduced

BUT

• Charge collectedreduced

The SEU problem (may) worsen with scaling

P.E. Dodd et al., IEEE Transactions on Nuclear Science, vol. 43, no. 6, Dec. 1996, pp. 2797-2804.

The plot shown in this slide illustrates that the SEU was becoming more important with scaling. On the y axis we have the threshold LET, which is the LET at which we start to have SEUs.

An explanation for this plot is that with scaling we reduce both the power supply voltages and the node capacitances. The critical charge is therefore reduced, which means that an ionizing particle needs to deposit less charge to create an SEU.

But there is also another effect which is competing with the above one: due to the reduction in the device dimensions the charge deposited by the ionizing particle which is collected in the critical nodes becomes smaller.

These two effects are compensating each other. In the literature there is not a very clear trend, but SEU could become worse with scaling.


SEGR and scaling

Maximum electric field for a quarter micron technology

decreasing tox

SEGR: Single Event Gate RuptureIt is caused by a highly ionizing particle going through the

gate of a MOS. It is a destructive effect (gate rupture).

F.W. Sexton et al., IEEE Transactions on Nuclear Science, vol. 44, no. 6, December 1997, pp. 2345-2352.

The necessity imposed by scaling to make thinner and thinner oxides results in an improvement in the oxide quality.

This has a beneficial impact on Single Event Gate Rupture (SEGR).

This plot shows what is the electric field that we have to apply to the gate to have a SEGR (called critical field ECR) as a function of the LET of the ionizing particle. This is done for 4 different oxide thicknesses.

For each plot we see that the critical field decreases increasing the LET.

And we also see that thinner oxides seem to be better, as they have a higher critical field.

On the plot we have added the maximum electric field in the gate of a 0.25 um CMOS technology (5.5 nm gate oxide thickness, 2.5 V power supply voltage). We can see that even for quite high LETs the critical field is much higher than the one we can have in an even thinner oxide.

Which value of LET can we expect in different environments? To give a couple of examples, in LHC we can have up to 15, in space up to 100.


SEGR in ULSI CMOS

SEGR is not a problem even in the most advanced CMOS processes.

L.W. Massengill et al., IEEE Transactions on Nuclear Science, vol. 48, no. 6, December 2001, pp. 1904-1912.

Newer technologies have even thinner oxides than the ones considered in the previous slide. Also, simple silicon dioxide is not anymore the oxide being used in modern CMOS processes. Nitrided oxides are already in use since a few years, and several other high-k dielectric materials are under study for future generation CMOS processes. High-k materials allow increasing the gate capacitance per unit area without decreasing too much the gate oxide thickness (and therefore without increasing too much the gate leakage).

These two plots show results on oxides as thin as 2.2 nm and on different kind of oxides.

On the left plot we see the critical field that led to SEGR under exposure of particles with a LET = 80. We can indeed see that the critical field is increasing for thinner oxides. On the same plot we have the field needed to break the oxide before irradiation, were we see a similar trend (but an even bigger slope): this is an indication of the increasing quality of these this oxides.

On the right plot, the y axis represents the voltage which needs to be applied to the gate to break it (always under irradiation). On the same plot the maximum power supply voltage VDD for technologies with those gate oxide thicknesses is shown.

From these two plots one can see that SEGR does not seem to represent a problem.


Summary of problems in CMOS

• TID in thin oxide Mainly VT shift Smaller in deep sub-μCMOS processes.

• TID in Field Oxide Leakage (in NMOS transistors and between transistors) Might be better in more advanced technologies, but still a very big issue to be solved.

• SEU Is it a Problem? This has to be evaluated and, in case it is, solved. Might become worse in deep sub-μ CMOS.

• SEL Does not seem to be a problem, but care should be taken anyway.

• SEGR Not a problem in deep sub-μ CMOS.

Let’s now make a summary of radiation induced problems in CMOS and of the effects of scaling on them.

As we can see from this slide, using a deep submicron technology solves most of the problems.

The two problems left are:

-Leakage currents (Total Dose in the field oxide and at the edges of the NMOS transistors)

-SEU


Enclosed Layout Transistor (ELT)

SD

G

S D

G

ELTs solve the leakage problem in the NMOS transistors

At the circuit level, guard rings are necessary

LEAKAGE PATH

Here we explain a way to solve the leakage problem in an NMOS.

On the left we have a standard transistor layout, with the indication of the leakage paths. On the right we see a different layout: the gate is annular, and it is completely surrounding the source (or it could be the drain).

We call these transistors Enclosed Layout Transistors.

This layout works very efficiently in cutting any possible leakage path between source and drain: the source is completely surrounded by thin oxide!

To cut leakage paths between different transistors, we will have to use guard rings (see next slide).


Guard rings

N+ WELL CONTACT N+ SOURCE

OXIDE

N WELL

P SUBSTRATE

P+ GUARD

VSS

++ + ++ +

+ ++ + ++ +

+

The heavily doped p+ guard ring“interrupts” possible conductivepaths (inverted p substrate), preventing inter-device leakage currents

VSSVDD

OXIDE

P+ guard rings have to be used around each n-well or n+ diffusion (at different potentials). This method is very effective in cutting the radiation induced leakage path (which is always made by electrons as we always trap holes in the oxide).


Effectiveness of ELTs


1.E-13

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

-1 -0.5 0 0.5 1 1.5 2 2.5 3 3.5

VG [V]

I D [

A]

Prerad

After 1 Mrad

After 1 Mrad (ELT)

This plot shows the effectiveness of Enclosed Layout Transistors. We have designed two transistors with exactly the same W/L ratio. One has a standard layout, the other is an ELT.

Before irradiation the two characteristics are coincident.

After irradiation we can see that the ELT completely eliminates the parasitic leakage paths at the edges of the channel.

The threshold voltage shift is nevertheless still present in this technology, as the gate oxide is still relatively thick. This still gives a quite high leakage current, even for the ELT.


ELT & deep submicron

1.E-131.E-12

1.E-111.E-10

1.E-091.E-081.E-07

1.E-061.E-05

1.E-041.E-03

1.E-021.E-01

-0.6

0

-0.3

4

-0.0

8

0.18

0.44

0.70

0.96

1.22

1.48

1.74

2.00

2.26

2.52

2.78

VG [ V ]

I D [

A]

Prerad andafter 13 Mrad


No leakageNo VT shift

Going to a smaller feature size, we completely eliminate the problem!

Here we see two measurements done on an ELT before irradiation and after 13 Mrd. The two plots are coincident!


A radiation-hard inverter

metal polysilicon

n+ diffusion p+ diffusion

p+ guard ring n+ guard ring

INO

UT

VSS VDD

This slide shows the layout of a radiation tolerant inverter. We can notice:

•The NMOS is an ELT

•The PMOS is not, as it is not necessary

•The p+ guard ring is essential to cut parasitic paths between the external n+ diffusion of the ELT and any other n region around (at different potential)

•The gates of the NMOS and of the PMOS have to be connected by metal. A connection made by polysilicon would open the guard rings

•The n+ guard ring around the PMOS is not really necessary, but it helps to fight SEL (it is a robust n-well contact).


Total Ionizing Dose tolerance

ΔVth ∝ toxn + ELT’s and

guard rings =TID

RadiationTolerance

Deep sub-μm means also:

speedlow powerVLSIlow costhigh yield

To summarize, we can obtain Total Ionizing Dose (TID) tolerance using a deep submicron process (<= 0.25 um) and ELTs and guard rings.

This is a much more efficient way of making radiation tolerant ICs compared to using a rad-hard technology: with deep submicron technologies we also gain in speed, power consumption, density, cost and yield!

This is because all the rad-hard processes available today are much less developed compared to a modern CMOS process.


Single Event Effects

SEGR

The systematic use of guard rings is ALSO an effective tool against SELSEL

Never observed in our circuits

SEUThe higher gate capacitance of ELTsdecreases the sensitivity, but other techniques might be necessary (at the circuit level)!

What about tolerance to Single Event Effects (SEE)?

•Single Event Latch-up (SEL): As already mentioned, guard rings are quite effective in preventing SEL

•Single Event Gate Rupture (SEGR): In many circuits we have done in a 0.25 um CMOS process, we have never had this problem. Results found in the literature are also quite positive.

•Single Event Upset (SEU) is definitely something we have to deal with. The use of ELTs increases a bit the node capacitance. Minimum size ELTs are bigger than the standard minimum size transistors, and therefore their gate capacitance is larger. This decreases a bit the sensitivity to SEU, but still in many occasions this is not enough. So one needs to investigate other solutions at the circuit level (redundancy, special memory cell architectures, …)


Reliability

Reliability: probability that a circuit will perform a required function under stated conditions for a stated period of time.

Reliability has become very important due to the aggressive scaling of device dimensions (without a corresponding scaling of

the voltages).This implied:

• Higher electric fields

• Higher current densities

• Higher power dissipation

• Higher chip temperature

• Higher technology complexity (e.g. number of metal levels)

http://www.imec.be/mtc/G. Groeseneken et al., “Reliability, Yield and Failure Analysis”, IMEC Microelectronics Training Center Course, Leuven, Belgium, 24-26/11/03

This slide and the next one are on reliability. This is a huge, complex topic. Very far from treating it in detail, we would like here just to mention a few key points.

Why are some words in red in the definition?

•Probability: the definition involves statistics: we have to accept that a few devices may fail (how many???)

•Required function: we have to define the failure

•Stated conditions: we have to define them all

•Period of time: involves the concept of lifetime of a circuit


Failure mechanisms at the chip level

• Devices:Oxide breakdown due to high electric field in the oxideHot Carriers create interface traps and charge trapping @ the drainElectro Static Discharge (ESD) discharge of static charge coming from human bodyLatch-up

• Interconnects:Electromigration (wires and contacts) mass transport of metal ions by momentum exchange with conduction electrons

• Packages:Thermomechanical fatigueDie crackingBond aging

A few more comments:

Oxide breakdown: Prevention: improve oxide quality, alternative dielectrics, screening

Hot carriers: non destructive. High energy electrons injected into the oxide. Shifts the Id-Vg curve. Prevention: Special Drain Layout, increase oxide quality, decrease VDD

Electromigration: due to high current densities. Prevention: design rules, new materials.

ESD: Prevention: antistatic measures, ESD protection circuits


Outline


• Sub-micron CMOS and BiCMOS technologies• Feature size scaling• Radiation effects and reliability• Mixed-signal circuits

Analog design in digital CMOS processesDigital noise in mixed-signal circuits

The last part of the presentation addresses some of the issues that we encounter when designing a mixed-mode (or mixed-signal) circuit, i.e. a circuit in which analog and digital blocks coexist.


Analog design in digital processes

• E. A. Vittoz, "The Design of High-Performance Analog Circuits on Digital CMOS Chips", IEEE JSSC, vol. 20, no. 3, June 1985, pp. 657-665.• W. Sansen, "Challenges in Analog IC Design in Submicron CMOS Technologies", Proceedings of the 1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design, Pavia, Italy, 13-14 September 1996, pp. 72-78.• C. Azaredo Leme and J. E. Franca, "Analog-Digital Design in Submicrometric Digital CMOS Technologies", Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, Hong Kong, 9-12 June 1997, vol. 1, pp. 453-456.

The integrated circuit market is driven by digital circuits, such as memories and microprocessors. This led to an increasing interest in

integrating analog circuits together with digital functions in processes optimized for digital circuits, making what it is called a System on a Chip

(SoC). This approach has several advantages and disadvantages.

ADVANTAGES:

• Lower wafer cost

• Higher yield

• Higher speed

• Lower power consumption (not always)

• Complex digital functions on chip (DSP)

DISADVANTAGES:

• Low power supplies

• Lack of “analog” components

• Inadequate modelingOutput conductanceDifferent inversion regions

• “Digital” noise

Using a standard digital CMOS process (I mean with this a CMOS process which is not optimized also for analog design) has some advantages and some complications: we will see some of the points in more details in the following slides.

Some more comments to this slide:

•Price: CMOS processes used to be relatively inexpensive. This is not quite true anymore: the price of a mask set for a 130 nm CMOS process is around 400K USD! Anyway, adding bipolars to that would make it even more expensive!

•Modern CMOS processes allow making very dense and high performance digital circuits. One has to take this into account when designing the chip at the system level, as the partition line between analog and digital might move more towards having more done with digital and less with analog. This means that some of the signal processing can be done more efficiently with digital circuits.

•Lower power consumption: we have already seen that this is true mainly for digital!

•Low power supplies are very good for the digital power consumption, but can create problems in the choice of the analog circuit architectures.

•The lack of analog components and the inadequate modeling of a few analog parameters are true especially in the early stages of development of a process. When a process is more mature these problems are normally at least partially solved. Also, as we have already mentioned, the lack of analog components is not really a problem anymore. The push to make System On Chip (SOC) circuits and RF CMOS circuits made these processes evolve, so that today we do have a quite large choice of analog components.


Analog components availability

Analog design needs high-quality passive components. These are not always present in processes optimized for digital design, or at

least not in the first stages of the process development. These analog “options” are:

• High-resistivity polysilicon for resistors

• Diffusion resistors

• Trimming options

• Linear and dense capacitors

Metal to metal (at least one special metal layer required)

Metal to poly

Poly to poly


Integrated capacitors

• A. T. Behr et al., "Harmonic Distortion Caused by Capacitors Implemented with MOSFET Gates", IEEE JSSC, vol. 27, no. 10, Oct. 1992, pp. 1470-1475.• D. B. Slater, Jr. and J. J. Paulos, "Low-Voltage Coefficient Capacitors for VLSI Processes", IEEE JSSC, vol. 24, no. 1, February 1989, pp. 165-173.• J. L. McCreary, "Matching Properties, and Voltage and Temperature Dependence of MOS Capacitors", IEEE JSSC, vol. 16, no. 6, Dec. 1981, pp. 608.• S. Pavan, Y. Tsividis and K. Nagaraj, "Modeling of accumulation MOS capacitors for analog design in digital VLSI processes", Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, Orlando, Florida, USA, 30 May – 2 June 1999, vol. 6, pp. 202-205.

• High-linearity capacitors can be obtained with metal-to-metal structures. This requires adding a special metal layer to the technology, in order to reduce the dielectric thickness between the metal plates. The density reached is generally around a few fF/μm2.

• Dense capacitors can be obtained exploiting the high capacitance density of the thin gate oxide. This allows having dense and precise capacitors, good matching but very poor linearity. This solution can be adopted in any process.

• A third possible solution is suggested by the availability of many interconnection layers. Exploiting the parasitic capacitance between metal wires in a clever way, one can obtain linear capacitors with good matching and linearity and densities up to 1.5 fF/μm2. These capacitors can be integrated in any process!!


Multi-metal-layer capacitors

• Hirad Samavati et al., “Fractal Capacitors”, IEEE Journal of Solid-State Circuits, vol. 33, no. 12, December 1998, pp. 2035-2041.

This solution is a possibility, but it does not exploit the fact that in deep submicron processes the highest parasitic capacitance can be obtained “horizontally” rather than vertically, i.e. tox > s

t

s

tox

The plot shows that in modern submicron processes the wire thickness is becoming bigger than the distance between wires. This means that the parasitic capacitance between wires at minimum distance is increasing.

Making a capacitor exploiting the parasitic capacitance between different metal levels (eventually using several levels) it therefore a not very efficient way of doing, as the thickness of the oxide between levels is bigger than the minimum distance between two wires of the same metal level. A better way would then be using the parasitic capacitance between wires.


Multi-metal-layer capacitors

• Hirad Samavati et al., “Fractal Capacitors”, IEEE Journal of Solid-State Circuits, vol. 33, no. 12, December 1998, pp. 2035-2041.• R. Aparicio and A. Hajimiri, “Capacity Limits and Matching Properties of Integrated Capacitors”, IEEE JSSC, vol. 37, no. 3, March 2002, pp. 384-393.

These are a few examples of how we can make dense capacitors exploiting the parasitic capacitance between wires. More details can be found in the references. The fractal capacitor is an interesting solution as it maximizes the perimeter to area ratio, but I am afraid it is going to be slightly difficult to design…


NMOS

Inversion Region

MOS capacitors

p+n+ n+

p-substrate

GND

V

n+p+ p+

n-well

p-substrate

VDD

V

PMOS

Inversion Region

Another interesting option to make dense capacitors is to exploit the high specific capacitance of the gate oxide. There are 4 ways of doing this, shown in this slide and in the next one.

The left structure in this slide has the advantage that it can be shielded from the substrate noise by applying a fixed bias to the n-well.


MOS structure

Accumulation Region

NMOS in an N well

Accumulation Region

MOS capacitors

p+n+ n+

n-well

p-substrate

GND

V V

p+ p+

p-substrate

Here we have the two other possibilities. The structure on the right has the disadvantage that the bottom plate of the capacitor is AC grounded.


C-V characteristics

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

1.1

-2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5

NMOS in an N well

NMOS

Vbias [ V ]

C/C

ox

The NMOS in an N well capacitor is in accumulation for

V > 0 V.

The NMOS capacitor is in

inversion for V > 0.

These MOS capacitors can go to very high density values. In the case of a 0.13 um technology, for example, we have around 10 fF/um2. But the big problem with them is that they are highly non linear, and therefore they are unusable in many analog applications. This is a measurement we have done on two of the four structures we have illustrated, designed in a 0.25 um technology. The bottom plate here was grounded and the top plate was swept between -2.5 V and 2.5 V.

We can see that these structures are really highly non linear.

What is interesting for us is the part of the curve for V > 0. We can see that the NMOS in the N well capacitor is the best option, as it is the more linear of the two.


Digital noise in mixed-signal ICs

• A. Samavedam et al., "A Scalable Substrate Noise Coupling Model for Design of Mixed-Signal IC's", IEEE JSSC, vol. 35, no. 6, June 2000, pp. 895-904. • N. K. Verghese and D. J. Allstot, “Computer-Aided Design Considerations for Mixed-Signal Coupling in RF Integrated Circuits", IEEE JSSC, vol. 33, no. 3, March 1998, pp. 314-323.• M. Ingels and M. S. J. Steyaert, "Design Strategies and Decoupling Techniques for Reducing the Effects of Electrical Interference in Mixed-Mode IC's", IEEE Journal of Solid-State Circuits, vol. 32, no. 7, July 1997, pp. 1136-1141.

Integrating analog blocks on the same chip with digital circuits can have some serious implications on the overall performance of thecircuit, due to the influence of the “noisy” digital part on the “sensitive”analog part of the chip.

The switching noise originated from the digital circuits can be coupled in the analog part through:

• The power and ground lines

• The parasitic capacitances between interconnection lines

• The common substrate

The substrate noise problem is the most difficult to solve.GND

VDD

VOUTVIN

GND

VDD

VOUTVIN

The noise from the substrate affects the devices through the bulk transconductance and the parasitics between the substrate and the gate, source and drain.

As explained in the slide, there are three ways through which the noise originated by the digital circuits can disturb the analog circuits:

•The power and ground lines

•The parasitic capacitances between interconnection lines

•The common substrate

To solve the first problem, we can keep separated the bias lines for analog and digital circuits. This is quite effective.

For the second problem, we have to make the layout with extreme care.

For the third problem… see next slides!


Noise reduction techniques

• Quiet the Talker. Examples (if at all possible !!!):Avoid switching large transient supply currentReduce chip I/O driver generated noiseMaximize number of chip power pads and use on-chip decoupling

• Isolate the Listener. Examples:Use on-chip shieldingSeparate chip power connections for noisy and sensitive circuitsOther techniques depend on the type of substrate. See next slide

• Close the Listener’s ears. Examples:Design for high CMRR and PSRRUse minimum required bandwidthUse differential circuit architecturesPay a lot of attention to the layout

N. K. Verghese, T. J. Schmerbeck and D. J. Allstot, “Simulations Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits”, Kluwer Academic Publishers, Boston, 1994.

Also important is the position of the pins in the package!


Different types of substrates

There are mainly two types of wafers:

1. Lightly doped wafers: “high” resistivity, in the order of 10 Ω-cm.

2. Heavily doped wafers: usually made up by a “low”resitivity bulk (~ 10 mΩ/cm) with a “high” resistivityepitaxial layer on top.

TSMC, UMC, IBM and STM (below 180 nm) offer type 1

R. Gharpurey and R. G. Meyer, "Modeling and Analysis of Substrate Coupling in Integrated Circuits", IEEE JSSC, vol. 31, no. 3, 1996, pp. 344-353.


Substrate noise: how to reduce it

To minimize the impact of disturbances coming from the substrate on the sensitive analog blocks, we have mainly three ways:• Separate the “noisy” blocks from the “quiet” blocks. This is effective especially in uniform lightly doped substrates. For heavily doped substrates, it is useless to use a separation greater that about 4 times the epitaxial layer thickness.

• In n-well processes, p+ guard rings can be used around the different blocks. Unfortunately, this is again effective mainly for lightly doped substrates. Guard rings (both analog and digital) should be biased with separate pins.

• The most effective way to reduce substrate noise is to ground the substrate itself in the most “solid” possible way (no inductance between the substrate and ground). This can be done using many ground pins to reduce the inductance, or, even better, having a good contact on the back of the chip (metallization) and gluing the chip with a conductive glue on a solid ground plane.

• Separate the ground contact from the substrate contact in the digital logic cells, to avoid to inject the digital switching current directly into the substrate.

D. K. Su, M. J. Loinaz, S. Masui and B. A. Wooley, "Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits", IEEE Journal of Solid-State Circuits, vol. 28, no. 4, April 1993, pp. 420-429.


Acknowledgements

• Dr. Paul O’Connor (Brookhaven National Laboratory, USA) for inviting me to give this lecture!

• Prof. Dr. John D. Cressler (Georgia Institute of Technology, USA) for material on SiGe Bipolar Transistors

• Dr. Giovanni Mazza and Dr. Angelo Rivetti (INFN Torino, Italy) for material on application examples

• Dr. Federico Faccio (CERN) for useful discussions• Dr. Alessandro Marchioro (CERN) for material on application

examples• Dr. Federico Faccio (CERN) and Dr. Paulo Moreira (CERN)

for reading the slides and the text, and for many useful comments.

semiconductor technology for integrated circuit front...

Documents